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Design and Implementation of Verilog Based High Speed Low Power

UART
Ms. Banti Kumari1, Ms. Kanika Jindal2, Mr. Amit Bindal3
1,2,3
Noida Institute of Engineering and Technology, Greater Noida, India.
Emails: [email protected], [email protected], [email protected]

Abstract
The most crucial component of serial communication is a microcircuit called a universal asynchronous
receiver/transmitter (UART). Receive-transmitter asynchronous technology is known as UART, and it is
widely used for device-to-device communication protocols. Using asynchronous serial communication at
a speed that can be adjusted. A hardware communication technique called UART Asynchronous
conditions occur when the output of the transmitting device and the receiving end are not in sync with a
clock. In UART, receiving a signal is known as RxD, and transmitting a signal is known as TxD. In
comparison to the existing conventional UART design, we were able to reduce delay by 29% and power
usage by 33% using our approach. The effectiveness of the novel UART design is noticed with the
reduction in delay and power consumption. Synthesis and simulation are done in Xilinx ISE and Modelsim
and Verilog HDL is used to implement a unique UART design.
Keywords: UART; RS-232C; Transmitter; Receiver; Asynchronous.

1. Introduction
The term UART refers to the Universal number of IOBS etc [2]. Today, Numerous
Asynchronous Receiver Transmitter Protocol. By products use UART, including RFID-based
looking at the name alone, we can deduce that software, Bluetooth modules, GSM and GPRS
UART is used for serial transmission. Direct modems, GPS receivers, and wireless
communication between two UARTs occurs communication systems [17]. whereas in this
during UART communication [1]. Parallel data is project UART with RS232 standard is uses for
sent in serial form by a controlling device, like a transmission of data signal which gives some
CPU, to the sending UART. Following that in advantages over a conventional UART. UART
order to convert the data into its original with RS232 operates on the principle of
parallelize form for the accepting device, it is asynchronous meaning that the data is transmitted
transferred from the sending UART to the individual bits without the need for continuous
receiving UART. In UART, two cables are clock signal.RS232 is able to communicate up to
established, with one wire being used for 15 m at a rate of 1.492 kpbs without any
transmission and the other for receiving. The interruption between two devices [15].
main motive of this project is to provide a high- 2. Implementations of UART
speed low power UART with RS232 standard 2.1. UART Data Frame
signaling protocol that defines things like pin A universal asynchronous receiver/transmitter, or
assignments, voltage levels and so forth and show UART, enables full-duplex transmission and
the comparison results between existing receiving by converting data between serial and
conventional UART design on the basis of delay, parallel communication. It has a serial data stream
power consumption, number of logic gates, that bit by bit transforms the input serial data into

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byte transmission and the computer's parallel data line noise. In this paper RS 232 is used that allows
into output; data streams for input and output are parallel data for serial communication between
checked for parity; Include operations in the devices over relatively short distance. When we
output data stream, like removing start and stop refer UART with RS 232 we discuss UART
tags. Asynchronous communication often uses the communication with the RS-232 electrical
following frame format: 1 bit for the start, 5 to 8 standard. In this configuration. The UART is
bits for the data bit, optional parity bit, parity, or responsible for serializing and deserializing data
no parity, and stop bit (1, 1.5, or 2 bits). Format (converting between parallel and serial data
for UART data frames [3]. As seen in Below formats) and handling the timing aspects of
Figure 1. communication. RS-232 specifies the voltage
levels used for signaling. To represent binary data
(1s and 0s) on the transmit and receive lines, it
specifies both high and low voltage levels.
Usually, the voltage levels fall between -15V and
+15V, where negative voltages represent logical
Figure 1 UART Data Frame [31-36] 1s and positive voltages represent logical 0s. The
receiving eventually comes to an end, Both the
To speed up the process, the parity bit is not set in state and completed signals are pulled down and
this step. Eight bits of data, one bit for start, one up, respectively. Once every data bit has been in-
bit for stop, and no parity bit make up the format put, the sampling counter will count [16].
of a data frame. Rs-232 is the standard 3. Literature Survey
communication interface, and full-duplex İn paper [1], showed the implementation of the
communication mode is used.[37] UART in the Virtex II Pro FPGA processor
2.2. Transmission Module because of its quick time to market, high speed,
Sending the data is the sending module's primary low cost, and repro-grammable nature.The
job. Along with other modules, it includes FIFO, FPGA's high speed capabilities and register-rich
data sending logic unit, and monitoring logic unit. architecture make it the ideal UART
This module uses baud rate to determine the implementation. The Xilinx ISE8.2 software
corresponding transmission frequency division programme was used to implement the design.
coeffi-cient. TXFIFO receives the data to be Finally, Using the Xilinx xst tool for simulation
delivered from the buffer and, while it is not and synthesis, the RTL schematic of the filtering
empty, transmits a data frame, managed by the IC was produced.Author of [2] Has designed
counter. Normally, stays high in the absence of UART based on FPGA Verilog was used
data flow Second, the sending module will throughout the entire design process, and Xilinx
transform the sending of parallel data into serial ISE Webpack 14.7 was used to make it visible in
data sending by transmitting the content in the Spartan-3E FPGA. The design can operate at
accordance with the data's format specification. the maximum Spartan-3E FPGA clock frequency
2.3. Receiver Module of 218.248 MHz, according to test results. The
2.3.1. Receiver timing configuration UART controller can handle bits at a maximum
Every time the value changes from "0" to "1" the frequency of 192.773 MHz, which is why it only
beginning bit of a frame of data can be considered requires a tiny amount of storage. Author of [18]
to have arrived. However, to guarantee the Use System Verilog (SV) to develop and validate
accuracy of the information shared between the a complete du-plex UART module. Without the
communication partners, Logical "1" can need of a clock signal, systems can communicate
potentially shift to logic "0" due to transmission with one another thanks to this serial

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communication protocol. Data from parallel electrical and physical characteristics of the serial
streams is converted to serial format and sent. communication interface. Overall, the objective
There has been a lot of re-searches in the literature of a UART with RS-232 project is to create a
author Jiajing Li suggests an asynchronous FIFO stable and efficient serial communication
buffered APB bus-based UART communication interface that can be used in a wide range of
interface. With this design, the AMBA bus may applications, from simple data transfer between
be used to set the UART controller in a flexible two microcontrollers to more complex scenarios
manner for baud rate ad-justment, transmission like device control, monitoring, and data
bits, parity mode configurability, and other acquisition [6].
features. Additionally, asynchronous FIFO UART (Universal Asynchronous
buffering is implemented to facilitate Receiver/Transmitter): It is a hardware
communication between low-speed UART component, or a communication protocol used for
devices and high-speed devices [19]. This study serial communication between computers or
elaborates on numerous elements linked to UART microcontrollers and peripheral devices. It
transceiver and focuses on the theoretical handles the conversion of parallel data (inside the
foundation and application of UART. Since computer) to serial data that can be transmitted
UART was first invented fifty years ago, UART over a communication line (like a wire) and vice
transceiver technology has advanced steadily and versa. As UART connection is asynchronous, data
is now widely applied in many spheres of life. is transmitted without the use of a shared clock
UART transceivers are crucial in many facets of signal. In order for communication to be
contemporary life, including healthcare and the successful, the sender and recipient must agree on
Internet of Things. UART transceivers also the baud rate, or data rate, as well as the data bits,
improve the application of currently available stop bits, and parity settings [7].
technology [20]. In Paper [5], author is concerned RS-232 (Recommended Standard 232): The
with improvements in PDP and total power in electrical and mechanical properties of serial
relation to clock period changes. The Cadence communication between devices are described by
NCSIM Simulator and Compiler is used for the RS-232 standard [8].
simulation and synthesis, and 45 and 90 nm
GPDK library files are used for UART
implementation. Now a days A popular technique
for testing digital circuits is scan-based testing,
which improves the controllability of the circuit
being tested, according to the paper's author [8].
The suggested technique divides a scan chain into
numerous scan segments, therefore reducing the
amount of test data. Circuit topology is used to
determine how to partition the scan chain, which
im-proves the number of scan segments that can
be skipped. According to the results of the
simulation, the suggested approach lowers the test
power usage [4].
4. Motivation and Contribution
While UART is a physical communication
method used for serial transmission between
devices, RS-232 is a standard that describes the Figure 2 Pin Diagram of Rs232 [30]

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For serial communication, it specifies voltage In r_data, the transmitter rs232_tx transmits serial
levels, signal timing, and connection pin data based on bit count [12]. A done signal is
assignments. RS-232 is often used for connecting issued when the transmission is stopped by setting
devices over short to moderate distances, typically the state to low level when the bit count reaches
with DB-9 or DB-25 connectors. The physical 10 and the bit flag is at a high level [21-23].
connections between devices might involve DB-9 module test_uart_tx;
or DB-25 connectors and cables with specific pin // Inputs
assignments for transmit (TX), receive (RX), reg clk = 0;
ground (GND), and other control signals. The reg rst = 0;
primary goal of this project is to create a modified reg [7:0] current_test = 0;
UART architecture [9]. To do this, a 232- reg [7:0] s_axis_tdata = 8'd0;
communication protocol must be implemented in reg s_axis_tvalid = 1'b0;
the UART, and the results should be compared to reg [15:0] prescale = 0;
the conventional UART method. comparison has wire s_axis_tready;
been shown based on the factors like speed, delay, wire txd;
power consumption, number of IOBs, number of wire busy;
logic gates, etc. The main objective of a UART To avoid errors resulting from the fusion of two
(Universal Asynchronous Receiver/Transmitter) data sets, the data in data signal will be kept in
with RS-232 project is typically to provide a r_data. A low state level denotes an idle state, a
communication interface between two electrical high level denotes a working state, and state
devices or systems using these protocols. My signifies the working state [13]. The send flag is
contribution to this work is that we use the RS 232 represented by bit_flag, the bit counter by bit_cnt,
signaling proto-col to develop a novel architecture and the baud rate counter by baud_cnt.
for a high-speed, low-power UART. We then always @ (posedge clk) begin
compare the speed and power of this new if (rst) begin
architecture to those of the conventional UART s_axis_tready_reg <= 0;
that is currently in use [10] in Figure 2. txd_reg <= 1;
5. Organization prescale_reg <= 0;
The paperwork is structured into several section. bit_cnt <= 0;
Section 2 provides the implementation of UART busy_reg <= 0;
and literature survey. Section 3 provides end else begin
motivation and my contribution in this project. if (prescale_reg > 0) begin
section 4 is the organization of this paper. section s_axis_tready_reg <= 0;
4 show system model and problem formulation. prescale_reg <= prescale_reg - 1;
whereas section 6 has a simulation results section end else if (bit_cnt == 0) begin
7 discusses the results and section 8 provide the s_axis_tready_reg <= 1;
conclusion and future scope of this project [11]. busy_reg <= 0;
6. Experiment Codes The bit counter bit_cnt begins to count when the
6.1. UART Transmitter Module send flag bit_flag is high.Bit_cnt = 0 causes
Parallel data is available for transmission at [7:0] rs232_tx to transmit the initial bit (low level).
data can be parametric. The status is set at the Eight bits of r_data are sent from low to high by
elevated level, and r_data stores information from rs232_tx when bit_cnt is between 1 and 8.
the data signal. when the input start signal shows RS232_tx sends the stop bit (high level) when
high level. For every bit_flag high level, bit count bit_cnt = 9 [24-25].
rises by 1 in accordance with the baud rate setting.

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6.2. UART Receiver Module overrun_error_reg <= 0;

The transmitting module's sending data, or frame_error_reg <= 0;
Rs232, is also assumed to be the data that the
receiving module needs to receive in order to Bit_cnt is the bit counter that begins to count
confirm that the receiving module's design is when bit_flag, the receiving flag, is high. The
accurate. Comparable to the transmission module, eight-bit rs232_t2 data is received by rx_data
bit_cnt counts determine which order in which the from low to high when bit_cnt is between 1 and 8.
receiving end, rx_data, gets the eight-bit data from
rs232_t2, from low to high [26-27] in Figure 3, 4.
module uart_rx #
(
parameter DATA_WIDTH = 8
)
(
input wire clk,
input wire rst,
output wire [DATA_WIDTH-1:0] m_axis_tdata,
output wire m_axis_tvalid,
input wire m_axis_tready,
input wire rxd,
output wire busy,
output wire overrun_error, Figure 3 Data Transmission of UART With
output wire frame_error, Rs232 [29]
input wire [15:0] prescale
);

Set the clock signal to 50MHz after entering it.

Low-level reset signal is represent-ed by rst_n.
After successfully receiving the signal, the
receiving end (rx_data) generates the end
receiving signal done [14].

always @ (posedge clk) begin

if (rst) begin
m_axis_tdata_reg <= 0;
m_axis_tvalid_reg <= 0;
rxd_reg <= 1;
prescale_reg <= 0; Figure 4 Proposed Serial Data Exchange
bit_cnt <= 0; Between PC and Device Using RS232 Protocol
busy_reg <= 0;
overrun_error_reg <= 0; 7. Simulations Results
frame_error_reg <= 0; After synthesizing the top module of UART in
end Xilinx software we get the schematic of the
else begin waveform as shown in below fig 5 and
rxd_reg <= rxd; implemented on FPGA artix 7.

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Figure 5 Waveform of The Proposed UART Figure 8 Power Consumption Graph

with Rs232

Figure 6 Comparison Graph of Delay Fıgure 9 Graph of Number of Logic Gates Use

Figure 7 Overall Comparison Graph of Delay Fıgure 10 RTL View of Proposed Uart

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Table 1 Performance Comparison of Existed and Proposed UART Design

UART WITH
PARAMETERS CONVENTIONAL
RS232

Logic delay(ns) 0.79 0.5

Route dela(ns) 2.2 1.67

Combinational delay
delay(ns) 2.99 2.127

Total path delay (ns) 2.99 2.127

Static power (nW) 0.591 0.619

Leakage Power(nW) 2.26 1.293

Total power
2.851 1.912
consumption(nW)
No of logic gates
53120 46560
No of flip flops
83 64

8. Result and Discussion

The above proposed work is detailed in Verilog less num of logic gates and less IOBs which
HDL. Synthesis and implementation have been makes the overall speed of the UART faster. We
done using XILINX ISE 14.5 also simulation and also conclude that new proposed work
waveform has been done on MODELSIM and the successfully decreases the delay by 29% and
FPGA device used here is ARTIX -7. Fig7 shows power consumption by 33%. this can be possilble
the waveform of the proposed UART, where 8-bit beacause of the RS232 communication which is
data is transmitted and the other figure 5-10 shows relatively simple and doesn't require complex
the comparison analysis through graphical protocol handling or processing compared to
representation whereas comparison has been done some other communication standards. This can
on the basis of delay, power consumption, num. lead to lower power consumption in the sense that
of logic gates use, num of IOBs etc. Table 1 less computational power is required to manage
illustrates the various above-mentioned communication. Also, it provides a wide voltage
parameters and show the comparison analysis range which makes the transmission less prone to
between the conventional way of UART and the noise and distortion. so, in this paper we are trying
proposed UART design. from the above results to show the new implementation of UART design
we conclude that UART with RS232 transmit data where we replace conventional way of UART and
more efficiently without any distortion in the use a UART with RS232 and try to enhance the
signal data as compared to conventional way also speed and lower the power consumption and we
conclude that proposed UART design consume have done successfully. The results are shown in
less power and faster in speed as compared to the table 1.
conventional way [28]. Proposed work also uses

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Conclusions Computing and Control Systems (ICICCS

In this, we compare the implementation of UART 2019) IEEE Xplore Part Number:
design in terms of power, delay, No. of transistor, CFP19K34-ART; ISBN: 978-1-5386-8113-
No. of bonded IOBS etc. and we conclude that the 8
implementation of the proposed UART with [3]. R, Y., & V, R. M. Design and Verification
RS232 gives the better result in terms of power, of UART using System Verilog.
delay, and other parameters. It is achieved a 29% International Journal of Engineering and
reduction in delay as compared to the Existing Advanced Technology, 2020,9(5), 1208–
conventional UART and power consumption is 1211.
reduced by 33%. if we compare the overall results, [4]. Thai, N. P., Ngoc, B. H., Duy, T. D.,
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