Proceedings of the International Conference on Self Sustainable Artificial Intelligence Systems (ICSSAS 2023)

IEEE Xplore Part Number: CFP22DN7-ART; ISBN: 979-8-3503-0085-7

Industrial Application of the Serial Peripheral

Interface Protocol on Field Programmable Gate
Arrays
S.Navaneethan U.Dinesh V. Deepak Rajan
2023 International Conference on Self Sustainable Artificial Intelligence Systems (ICSSAS) | 979-8-3503-0085-7/23/$31.00 ©2023 IEEE | DOI: 10.1109/ICSSAS57918.2023.10331803

Department of Electronics and Department of Electronics and Department of Electronics and

Communication Engineering Communication Engineering Communication Engineering
Saveetha Engineering College Saveetha Engineering College Saveetha Engineering College
Chennai, India Chennai, India Chennai, India
[email protected] [email protected] m [email protected] m

Abstract— The Uni versal Asynchronous Recei ver components, including sensors, actuators, and control units.
Transmitter UART, Serial Peripheral Interface (SPI), Serial co mmunication protocols serve as the fundamental
and Inter -Integrated Circuit (I2 C) are wi del y utilized framework for transmitting data over considerable distances,
hardware communication protocols. The process of facilitating the smooth integration and coordination of
selecting one option from a set of alternati ves may numerous devices. The employment of FPGA technology
provi de di fficulties owing to the uni que benefits and facilitates the simultaneous explo itation of many
drawbacks connec ted wi th each choice. This article is a communicat ion protocols within a single device, hence
thorough examinati on of the three protocols, wi th a providing significant benefits across a wide range of
detailed expl anati on of their elements, functi ons, and industrial applicat ions [2]. This article aims to evaluate and
potenti al advantages and disadvantages. After doing a analyze several p rotocols to ascertain their suitability fo r
comparison i nvestigati on of the transmission ranges, it implementation in industrial environ ments. Specifically, the
becomes apparent that the modern SPI protocol comparison and contras t will focus on key factors such as
demonstrates a greater degree of superiority. The UART data rates, range limitations, noise immunity, and
protocol demonstrates enhanced reliability in scalability.
performance, however, the SPI protocol provi des greater
di versity i n terms of communication options wi th fewer II. LITERATURE REVIEW
resources. In the context of power consumption, it can be To facilitate efficient communication between two
observed that UART has superior performance electronic devices, it must adhere to a common protocol.
compared to the other two protocols. This study ai ms to Protocols serve as the official terminology for these
offer a fresh and uni que viewpoint on the i mportance of prescribed compilations of regulations. The process of
design. transmitting data ensures the maintenance of data integrity
[3]. The UA RT is a popular choice for serial data transfer.
Keywords—Serial Communicati on Protocols,
Both the UART Sender and the UART Receiver are crucial
Uni versal Asynchronous Recei ver Transmi tter, Serial
parts of the system. Shift register, odd/even parity generator,
Peripheral Interface , Inter-Integrated Circuit, Fiel d finite state machine (FSM), and several auxiliary blocks are
Programmable Gate Array.
only some of the important parts of a UART's transmitter
module. Since the baud rate generators in the transmitter and
I. INT RODUCT ION receiver are identical, it follows that the baud rate (also
known as the baud clock) will be stable between the two
The achievement of effective and reliable data devices. The maximu m length of a data frame transmitted
transmission between electronic equip ment in many over the UART is 11 bits. The concept of odd parity is used
industrial applications is unfeasible without the presence of in this investigation[4]. The transmission protocol is
serial co mmunicat ion standards. The utilization of s field composed of a solitary start bit, succeeded by eight data bits,
Programmab le Gate Array (FPGAs) as platfo rms for the one parity bit for parity indication, and a closing stop bit to
construction of serial co mmun ication interfaces has been denote the termination of the transmission. When the input
demonstrated, owing to its inherent adaptability, remarkab le system clock operates at a frequency of 64 M Hz, the
performance, and configurability [1]. Th is study investigates resulting baud rate at the output is 4 Mbps. Verilog HDL is
and evaluates various serial co mmun ication protocols often widely regarded as the preferred language for the
emp loyed in industrial environ ments and implemented on development and verification of UART. The Vivado 2020
FPGA. In industrial settings, the establishment of efficient software developed by Xilin x is utilized to simulate and
and dependable commun ication networks is vital to synthesize UART capabilities. The Zed FPGA board is
facilitate the interconnection of diverse equipment widely acknowledged as the most optimal choice for UART

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 Proceedings of the International Conference on Self Sustainable Artificial Intelligence Systems (ICSSAS 2023)
IEEE Xplore Part Number: CFP22DN7-ART; ISBN: 979-8-3503-0085-7

synthesis, garnering recognition in both educational and accompanied by suitable circumstances. The analysis
professional settings. When properly configured, the board commences by doing a thorough examination of the
can be utilized in setups linked to the Internet of Things structural and functional elements of the three discrete serial
(IoT) [5]. interface types [9-10]. The implementation of a multi-
A UART consists of three primary constituents: a function serial interface on the FPGA platform has the
transmitting unit, a receiving unit, and a baud rate generator. potential to substantially reduce hardware requirements by a
UART chips are extensively utilized within the industrial factor of three as compared to the utilization of three separate
sector. The UART possesses the capability to establish serial co mmunication interfaces. The user's writing lacks
communication links with both FPGA and Microcontrollers sufficient information or context to be rewritten
(MCUs). The study encompasses many application domains, academically.
namely the military forces, medical sector, communications
industry, and industrial control systems. In contrast to the III. SERIAL COMMUNICATION
SPI, which has faced ongoing restrictions arising fro m load PROTOCOL
capacitors despite extensive refinement efforts over the
A. UART
years, UART technology presents several advantages in
terms of cost-effectiveness, stability, and dependability. The UA RT is a co mmunicat ion protocol that enables the
Nevertheless, a considerable amount of untapped potential transmission and receipt of data at variable speeds. To
remains. Subsequent research endeavors could perhaps achieve precise synchronization, a method known as
exp lore the underlying factors contributing to the relative sequential transmission is employed, wherein data bits are
inferiority of UART in comparison to alternative serial ports transmitted in a specific sequence, progressing from the
[6]. least significant bit (LSB) to the most significant bit (MSB).
Within the given context, the abbreviation "I2C" The regulation of voltages for UA RT signals is
denotes the expanded term "Inter-Integrated Circuit." The accomplished by the utilization of a dedicated driver circu it.
credit for the development of the serial bus protocol is Frequently, in the realm of debugging, connections of a
commonly assigned to Philips Semiconductor. The I2C bus shorter kind are established, emp loying widely utilized
is extensively utilized in various applications due to its signal levels such as RS-232, RS-485, and raw TTL. The
inherent simplicity. The I2C protocol is employed by s initial versions of teletypewriters emp loyed current loops as
(CPUs) to establish communication with peripheral devices a mechanism for functioning as presented in Figure 1.
operating at low speeds. This technique enables efficient
communication across devices with varying processing
speeds while guaranteeing the integrity and retention of all
transmitted data. The I2C bus controller functions as the
intermed iate between the master and slave devices. The I2C
bus, implemented on an FPGA, is widely regarded as a
comparatively simpler bus architecture. This is mostly due to
its utilization of only two wires and a decreased number of
pin connections [7].
The primary focus of the development process [8]
for the master controller revolved around the utilization of
the I2C protocol. When connected to a computer or CPU,
this controller possesses the capacity to comprehend
instructions presented in the 8-b it I2C format. After
comprehending the instructions, they are transformed to
assure adherence to the SPI standard. To enable the Fig.1 Basic Transmitter and Receiver System
sequential transfer of data, a register with a length of 32 bits
is configured to conform to the established specifications of
the SPI. The emulation of the VHDL-based module can be The lack of a centralized clock signal is ascribed to the
efficiently achieved by utilizing the Model SIM program. In asynchronous nature of its operation. On the other hand, the
addition, the synthesis technique employed in Xilin x XST transmission protocol utilizes start and stop bits as a means
12.1 integrates enhancements on power consumption and of encapsulating the transmitted data. In the context of data
area utilization. The aforementioned methodology exhibits frames, it is customary for a low-level start bit to precede
extensive versatility in scenarios wherein a CPU requires each frame, which is then followed by one or more high -
interaction with an SPI device. The aforementioned level stop bits. The potential benefits of incorporating an
component acts in a reverse fashion, serving as a subordinate additional parity bit inside the UART protocol lie in its
to the CPU while assuming a superior position over the SPI ability to facilitate error detection [11]. To ensure efficient
device. The probability of experiencing data loss is low as a communication, all devices must maintain consistent baud
result of the optimization of the design to accommodate the rates, as this factor directly impacts the transmission speed.
slower transfer rate of the SPI device. Numerous The default configuration of the UART is half-duplex,
communication protocols have been developed to facilitate allowing for the transfer of data in both directions. The
the transport of data using universal serial communication necessity for device compatibility arises due to the
interfaces. Every individual needs to be positioned within a utilization of discrete voltage levels to symbolize logic 0
conducive atmosphere that fosters respect and is and logic 1.

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 Proceedings of the International Conference on Self Sustainable Artificial Intelligence Systems (ICSSAS 2023)
IEEE Xplore Part Number: CFP22DN7-ART; ISBN: 979-8-3503-0085-7

The UART is an integrated circuit chip that facilitates

serial data transfer between a host computer and a
connected peripheral device. Microcontroller chips
frequently incorporate one or more UA RT peripherals.
Specialized s (UA RTs) are emp loyed in several
applications within the automobile industry, as well as in
smart cards and SIM cards [12].
Fig. 3 Proposed SPI Interface
B. I2C
The interconnection of the master and slave MOSIs is
The protocol uses a two-wire interface in Fig 2 with SDA
evident. The Master Input Slave Output (MISO) of a master
and SCL lines. The efficient data transport is due to all bus
device is linked to the MISO of a slave device. The slave
devices sharing lines. A synchronous I2C connection
select signal, which has the same functionality as the chip
synchronizes data transfers with the master device's clock
select signal, is used as a substitute for any kind of
signal. The primary device's clock signal synchronizes data
addressing scheme. It is important to consider that in the
flows. The I2C bus gives each slave device a unique address
case of a device that is limited to functioning only as a
to improve communication between the master and slaves.
slave, there is a possibility that the MOSI and MISO labels
The addressing approach lets mult iple devices share a bus.
might be interchanged. The signal names listed above are
The I2C protocol uses "messages," which are packets of data
often used in modern electronics and may be emp loyed to
transferred between devices. Each byte is encoded into an 8-
indicate both the pins of the master and slave devices, as
bit block for transmission, and many bytes can be delivered
well as the signal lines that link them. It is necessary to
in a message.
adhere to consistent capitalization of pin names, such as
using "Chip Select" instead of "chip select". The lack of a
centralized clock signal is ascribed to the asynchronous
nature of its operation. On the other hand, the transmission
protocol utilizes start and stop bits as a means of
encapsulating the transmitted data. In the context of data
frames, it is customary for a low-level start bit to precede
each frame, which is then followed by one or more high -
level stop bits [15]. The potential benefits of incorporating
Fig. 2 I2C Interface an additional parity bit inside the UART protocol lie in its
ability to facilitate error detection. To ensure efficient
The clock frequency determines the I2C bus data communication, all devices must maintain consistent baud
transmission speed. The conventional I2C mode runs at 10 0 rates, as this factor directly impacts the transmission speed
kHz, whereas the fast mode runs at 400 kHz. High-speed [16]. The default configuration of the UA RT is half-
mode (3.4 MHz) and Fast-mode Plus (1 MHz) devices boost duplex, allowing for the transfer of data in both directions.
data transmission speeds. Regardless of master or slave The necessity for device co mpatibility arises due to the
status, the receiving device broadcasts an acknowledgment utilization of discrete voltage levels to symbolize logic 0
(ACK) bit after data reception. The gadget may not respond and logic 1.
or have an issue if there is no input. The I2C standard lets
several master devices share a bus. It is important to note that Embedded systems frequently utilize the SPI standard,
genuine and meaningful communication can only occur with which facilitates a synchronous serial co mmunication
one person with extraordinary expert ise or experience. In interface specifically tailored for short-range applications.
situations where numerous knowledgeable people fight for a The interface was initially designed by Motorola and has
bus spot, arbitration is used to determine authority. The subsequently garnered substantial ubiquity. LCD panels and
protocol's versatility and wide range of features enable Secure Digital cards are often seen imple mentations in
smooth data transmission across devices from different various contexts. Typically, SPI devices participate in full
manufacturers and with different characteristics. This duplex co mmunication with a sole master in a general
technology is used in embedded systems, sensors, EEPROM context [17].
memory chips, and integrated circuits [13]. The performance co mparison of serial protocols is listed
IV. PROPOSED SPI SERIAL COMMUNICATION in Table 1.
PROTOCOL
The SPI is occasionally referred to as a "four-wire serial
bus," a nomenclature that sets it apart from the more
common three-, two---, and one-wire serial buses. The
Synchronous Serial Interface (SSI) protocol, unlike the SPI,
functions as a synchronous serial interface. It uses four-wire
synchronous serial transmission. The SSI protocol uses
differential signaling and a single simplex channel to
transmit data [14]. The communication architecture utilized
by SPI is shown in Fig 3.

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 Proceedings of the International Conference on Self Sustainable Artificial Intelligence Systems (ICSSAS 2023)
IEEE Xplore Part Number: CFP22DN7-ART; ISBN: 979-8-3503-0085-7

Table 1. Performance Comparison of SPI, UART, I2C Table 2. Resource utilization of Protocols
SPI vs UART vs I2C Number Number The Number FPGA
of Slice of Slice number of LUT
Aspect SPI UART I2C registers LUTs used as Flip
Asynchronous Synchronous Synchronous logic Flops
Pairs
Protocol Serial Serial Serial used
Type Communication Communication Communication Shantha 356 547 98 230 Spartan
Selva 6
Master, Slave,
Kumari[4]
Transmitter, Serial Data
Jai Karan 460 398 102 378 Virterx
Key Receiver, Baud Master, Slave, Line (SDA), Singh[5] 5
Components Rate Generator Shift Registers Clock (SCL) 320 430 190 496 Spartan
Xingchun 6
1 Start Bit, 8 Variable Data Liu[6]
Data Bits, 1 Variable Data Bits, Proposed 120 145 93 148 Spartan6
Data Frame Parity Bit, 1 Bits, No Parity, Acknowledge SPI

Format Stop Bit No Stop Bit Bit, Stop Bit

up to 4 Mbps Up to 20 MHz Up to 1 Mbps

Speed (configurable) (configurable) (configurable)

More Multi-Master
Basic Error Advanced Error Bus,
Data Checking Checking Arbitration for
Integrity (Parity Bit) (CRC) Data Collision

Figure 4 Comparison of Slice registers

Different FPGA utilization of protocols are compared in
4 Lines (MOSI,
figure 4,5,6,7.
Pin 3 Lines (TX, MISO, SCLK, 2 Lines (SDA,
Connections RX, GND) SS) SCL)

IV. RESOURCE UTILIZATION

The Inter-Integrated Circuit I2C is a co mmonly
employed serial interface that facilitates the linkage between
s (CPUs) and low-speed devices. This enables effective
communication across devices that possess varying
processing capabilities. This study offers a comprehensive
examination of the SPI, IIC, and UA RT serial interfaces,
with a particular emphasis on their topologies, protocols, and
timing characteristics. The simu lation results offer empirical
support for the efficacy of the Verilog-based flexible mu lti-
function interface. The optimization of hardware resource Figure 5 Comparison of Slice LUTs
allocation can be accomplished in Table 2.

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 Proceedings of the International Conference on Self Sustainable Artificial Intelligence Systems (ICSSAS 2023)
IEEE Xplore Part Number: CFP22DN7-ART; ISBN: 979-8-3503-0085-7

FPGAacceleration", 2019 11th International Conference on

Electronics Computers and ArtificialIntelligence (ECAI), pp. 1-5,
2019.
[8] Hendra Saputra Gani, Sastra Kusuma Wijaya, and Z. Toresano La
Ode Husein, "Development of EEG Data Acquisition System Based
on FPGA Zedboard", 2017 5th International Conference on
Instrumentation Communications Information Technology and
Biomedical Engineering (ICICI - BME), pp. 1-5, 2017.
[9] 2. S. S. Nath, S. Navaneethan, M. S. Sakthekannan, M. Udaya
Krishnan and B. M. Yogavignes, "SD Card Interface Using FPGA for
Multimedia Applications," 2022 6th International Conference on
Electronics, Communication and Aerospace Technology, Coimbatore,
India, 2022, pp. 388-394
[10] P. Bala Gopal, K. Hari Kishore and B. Praveen Kittu, "An FPGA
Implementation of On-Chip UART T esting with BIST T echniques",
International Journal of Applied Engineering Research, pp. 0973-
Figure 6 Comparison of logic used 4562, 2015.
[11] Umakanta Nanda and Sushant Kumar Pattnaik, "Universal
asynchronous receiver and transmitter UART", 2016 3rd
International Conference on Advanced Computing and
Communication Systems (ICACCS), vol. 1, pp. 1-5, 2016.
[12] M. Mishra, "Design and Implementation of UART Using
Verilog", Doctoral dissertation, 2022.
[13] R. Sarkar, "Verification of UART", Doctoral dissertation, 2020.
[14] M. Koushik, R. Anushree, B. J. Sowmya, and N. Geethanjali, "Design
of SPI Protocol with DO-254 Compliance for Low Power
Applications," 2017 International Conference on Recent Advances in
Electronics and Communication T echnology (ICRAECT), Bangalore,
2017, pp. 186-190.
[15] K Aditya, M Sivakumar, F Noorbasha and P Thummalakunta,
"Design and functional verification of an SP I master-slave core using
system Verilog", Int. Journal of Computational Engineering
Research, 2018.
[16] Dr. G.B. Wakle, I. Aggarwal and S. Gaba, "Synthesis and
Figure 7 Comparison of LUT FlipFlop Pairs Implementation of UART using VHDL Codes", International
Symposium on Computer Consumer and Control, pp. 1-3, June 2012.
V. CONCLUSION [17] T.P. Blessington, B.B. Murthy, G.V. Ganesh, and T .S.R Prasad,
"Optimal Implementation of UART-SPI Interface in SOC", Devices
The standards of the protocol bus have been specifically Circuits and Systems (ICDCS) International Conference, pp. 673-67,
developed to facilitate co mmunication with devices that have 2012.
slower response times, while also providing the capability for
high-speed mode to efficiently transfer substantial volu mes
of data. The comparison of different serial protocols is
anticipated to remain a popular choice among a diverse range
of persons. The protocol standard exhibits a notable level of
versatility, allowing for effortless integration with low-speed
devices and permitting e xpedited data transfers. The SPI bus
is anticipated to retain its prevalence as a commonly utilized
serial interface for allo wing interconnections between
integrated circuits on electronic boards for a prolonged
duration owing to its favourable characteristics.
REFERENCES
[1] K. Shahu, "ASIC Design Implementation of UART using Synopsys
EDA tools", Doctoral dissertation, 2019.
[2] B. Liu, Z. Wang, Y. Lou, M. Zhang, and Q. Zhong, "Design and
implementation of UART based on FPGA", China Integrated Circuit,
vol. 6, pp. 38-41, 2016.
[3] M. Poorani and R. Kurunjimalar, "Design implementation of UART
and SPI in single FGPA", 2016 10th International Conference on
Intelligent Systems and Control (ISCO), pp. 1-5, 2016, January.
[4] U. Nanda and S. K. Pattnaik, "Universal Asynchronous Receiver and
Transmitter UART", 2016 3rd International Conference on Advanced
Computing and Communication Systems (ICACCS), pp. 1-5, 2016.
[5] Ashok Kumar Gupta, Ashish Raman, Naveen Kumar and Ravi
Ranjan, "Design and implementation of the high-speed universal
asynchronous receiver and transmitter UART", 2020 7th
International Conference on Signal Processing and Integrated
Networks (SPIN), pp. 295-300, 2020.
[6] Koren Israel, Computer arithmetic algorithms, AK Peters/CRC Press,
2018.
[7] Ovidiu Plugariu, Lucian Petrica, Radu Pirea, and Radu Hobincu,
"Hadoop ZedBoard cluster with GZIP compression

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