RESEARCH PAPERS

VERILOG BASED UART SYSTEM DESIGN

By
DHARMENDRA SINGH * UPENDRA SONI ** KARAN SHOBHANI ***
YASH KARKASHE **** SHUBHAM LIMJE ***** AAYUSH NAYAK ******

*-** Assistant Professor, Department of Electronics and Telecommunication Engineering, Shri Shankaracharya Institute of Professional
Management and Technology (SSIPMT), Raipur affiliated by CSVTU, Bhilai, Chhattisgarh, India.
***-****** UG Scholar, Department of Electronics and Telecommunication Engineering, Shri Shankaracharya Institute of Professional
Management and Technology, Raipur affiliated by CSVTU, Bhilai, Chhattisgarh, India.

Date Received: 24/04/2018 Date Revised: 16/05/2018 Date Accepted: 28/05/2018

ABSTRACT
Universal Asynchronous Receiver Transmitter (UART) nowadays become more popular for serial communication over a
computer or any other peripherals. UART is based on the serial communication protocol used for very short distance
communication. It works on full duplex transmitter and receiver mode. UART is specially designed for the interfacing
between RS232 line and Microcontroller so that any serial communicating device can easily connect with the other
peripherals. It allows the exchange of the data between the processor and peripherals. The serial communications are
assumed to have more reliable data transmission than the parallel communication. The parallel devices require more
hardware due to which the circuitry becomes more complex as compared to the serial communication device. In this
paper, verilog based UART has been proposed to design.
Keywords: Serial Communication, Transmitter, Receiver, Full Duplex, UART.

INTRODUCTION represents high state. Depending upon the status of the

The UART converts parallel data into serial data due to transmitter and receiver, the binary bit are set or reset that
which long distance communication takes place at low is either highest state or low state (Laddha & Thakare,
cost since the hardware requirement are less for serial 2013a). When the transmitter remains ideal then the data
communication device, whereas for parallel line will be at high logic state, whereas when the
communication device, the hardware requirement is transmitter is ready to transmit, the data line will become
more, which will increase the complexity as well as the cost low. To initialize this operation, “Start bit” is added to the
of the circuit (Fang & Chen, 2011). UART has numerous beginning of the word to be transmitted. This start bit is only
features in which we use very less in comparison to its full used to make the receiver active so that the data
feature. It allows full duplex communication in serial link. It is transmission can take place. During this operation, the
a very common technique used for the data clock used at both the ends should be synchronized in
communication or transferring of data between the such a way that no data can be lost during
devices. So it has large application in the field of data communication (Rawat & Ramola, 2015). UART contains
communication and control system (Kedar, 2014). Only three major sections or components that are transmitter,
two signal lines are used for the basic communication receiver, and baud rate generator which is a frequency
through UART i.e., RXD, TXD. These two lines are capable of divider. Asynchronous indicates that it can recover
performing full duplex operation through any media character timing information from the data stream on the
connected with it. The binary signals were used to basis start and stop bits provided in the starting and
distinguish between transmitter and receiver lines. These ending of the data stream (Yuan et al., 2010). The UART is
binary bits are 0 and 1. Zero represents low state and 1 used to Interface between slow and fast devices so that

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proper communication can take place. Due to these (Yu et al., 2007).
reasons, it is used for short distance communication at low 3. Objective
cost. Once you start to sent bits, the initial operation starts
The main objective of this paper is to design an UART
from LSB to the MSB bit. The transmission time for each bit
module so that a proper communication takes place
remains same so that each bit contains same time
between high speed peripheral devices and low speed
(Moussa et al., 2013).
peripheral devices.
1. Differences between Synchronous and Asynchronous
4. Review of Previous Work
Communication
From review of related work and released literature, it is
1.1 Synchronous Communication
observed that many researchers have designed UART by
In this communication, a number of data is to be sent at means of making use of specific techniques like
the same time either in the form of blocks or frames. algorithms, logical members of the family. The UART used
Transmission speed of this communication is faster since for the serial communication protocol provides the entire
more data is transmitted at same time. Due to this reason, duplex conversation in serial link. The design of the
it is more expensive. During the transmission of large data, hardware implementation has a high speed and UART
the gap between the data is not present. utilizing area Programmable Gate Array. The UART has
1.2 Asynchronous Communication three modules, i.e., receiver, transmitter, and baud rate
In this communication, either one byte or character is generator which also works as a frequency divider. These
transmitted or received at a time. Due to this reason, the modules are simulated on ModelSim SE 10.0a and
transmission speed is slow as compared to the designed through making use of Verilog description
synchronous transmission. Since single byte or character language, which has been synthesized on Field-
is transmitted at a time, it is less expensive and random in Programmable Gate Array (FPGA) kits like as Spartan 3 and
time interval, and the gap between the data is present in Virtex 4. On doing the comparative evaluation, there is a
this communication. change in between the number of slices, LUTs, and the
maximum frequency. The results are relatively good and
2. Differences of VHDL and Verilog
steady and have high-quality flexibility with high
VHSIC Hardware Description Language (VHDL) is a very
integration. In making the UART if we use FIFO, the design
high speed Integrated circuit based hardware
becomes more stable, reliable, and more flexible, which
description language, whereas verilog is the language of
supplies absolutely better bps rate (Longadge et al.,
verifying logics. The language is very similar to the pascal
2015). A UART is a full duplex receiver and transmitter. It is
language, which is an alternative language of VHDL to
the chip with inbuilt programming that offers controls on a
specify the RTL logic synthesis of the VHDL (Ansari &
computer's interface to its attached serial devices. It
Farooqi, 2012). VHDL comes under rich typed language.
controls the transmission of serial and parallel knowledge.
Ada programming language is the main source from
The whole mission of serial transmission is performing on
which the VHDL programming language is derived which
the principle of the shift register. In knowledge transmission
are more verbose than the verilog. Since VHDL does not
by means of the UART, once the baud rate has been
define availability, the strong typing requires additional
generated, both the transmitter and the receiver's inside
coding to explicit VHDL, which does not define any
clock are set to the same frequency (Shrivastava &
simulation control or monitoring capabilities within the
Sharma, 2014). Tenure is concerned, establishing a serial
language. In comparison to the VHDL, verilog is weak as
conversation protocol together with bit synchronization,
well as the language is of limited type. Verilog is derived
frequency division according to the input clock. All
from C programming language and an older HDL called
modules are simulated on Xilinx ISE (Kumar & Angadi,
Hilo. All the other data types used in verilog are predefined

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2012). This offers a design of an asynchronous FIFO and the signal in terms of serial through RXD pin, which are
structure of the controller. This controller is designed with being further converted and forwarded to the transmitter
UART circuit block and FIFO circuit within FPGA to set up modules. The UART frame format is shown in Figure 2.
communication in modern complex control systems with 6. Receiver
comfort. This controller can be used to establish
UART hardware operations are controlled by means of a
information exchange, when master equipment and
clock signal which runs at a different data rate. For
slavery equipment are set on the separate baud rate. To
instance, every knowledge bit could also be as long as 16
lower synchronization error between subsystems in a
clock pulses. On each clock pulse, the receiver tests the
approach with a few subsystems, we are also able to use
state of the incoming indicators, and looks for the
it. The controller is scalable and reconfigurable. There is
beginning of the start bit. If the apparent start bit finishes at
also large discipline difficulty (Laddha & Thakare, 2013b).
the least one-half of the bit time, then it is discovered to be
This work proposes an integrated architecture for a UART
valid signals to establish a new character (Patel et al.,
module to be used with MIMO-OFDM hardware platform,
2012). If not, then the duplicate pulse will be eliminated.
the cause of this module is to enable the communication
After ready for the other bit time, the state of the line is
process between FPGA board and MATLAB. There is also
again sampled and the resulting level clock becomes a
design complexity (Moussa et al., 2013). There are various
shift register. After getting the specified quantity of bit
problems that exist with the previous methodology which
intervals for the character length (5 to 8 bits, in general)
are reduced in this method. To overcome the problem of
eliminated, for the receiving approach, the contents of
routing and extra space requirement, UART IC is
the shift register is made to be available parallely. The
implemented on FPGA board. Regarding flexibility and
UART will set a flag, indicating new information to be
cost, it has the ability to update its functionality by using
available, and may also generate a processor interrupt to
partial reconfiguration of the portion in the design.
request that the host processor transfers the received
5. Proposed Work data. On every alternate of data line, the satisfactory
From the initial stage this design is divided into three UARTs "resynchronize" more than a half bit. In this
stages. First, the design of baud rate generator. Second, approach, when the transmitter is sending at a different
the receiver end module, and third is the transmitter end speed than the receiver, they reliably receive (This is the
module. Figure 1 shows the module of UART. normal case, on the grounds that apart from the
Initially, the baud rate generator helps in providing the communication signal, communicating units probably
clock (local clock), which is required to be higher than the do not have any shared timing process). The receiver
requirements of the transmitter and the receiver modules. system is shown in Figure 3.
The RXD pin used to produce alert signals by the receiver 7. Transmitter
module, which is being converted into parallel The Transmitter subsystem transmits the signal by placing
information. And similarly, the transmitter module sends all the data into the shift register and simultaneously the
receiver starts receiving the signal. The UART produces

Figure 1. Module of UART Figure 2. UART Frame Format

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signal along with the parity bit including start and stop bits. Acknowledgment
The transmitter subsystem is shown in figure 4. Expression of giving thanks are just a part of those feelings
8. Baud Rate Generator (BRG) Module which are too large for words but shall remain as
Baud rate generator is a module which is used in the initial memories of wonderful people with whom we have got
stage to specify the rate of transmission and reception of the pleasure of working during the completion of this work.
the signal. The transmitter transmits the signal and the We are grateful to Shri Shankaracharya Institute of
receiver receives the signal at the same rate on which the Professional Management and Technology, Raipur which
rate is defined by the baud rate generator. helped me to complete this work by giving encouraging
environment. We would like to express my deep and
Divisor (decimal) = (clock frequency) /
sincere gratitude to my supervisor, Assistant Professor,
(baud rate x clock sampling rate)
Upendra Soni. His wide knowledge and his logical way of
Conclusion
thinking have been of great value to me. His
In this paper, a verilog based UART design is proposed and understanding, encouraging, and personal guidance
implemented successfully. This design consists of three have provided a good basis for the present work.
modules, i.e. Baud rate generator, Transmitter, and
References
Receiver modules. All these three modules were
[1]. Ansari, H. K., & Farooqi, A. S. (2012). Design of high
implemented successfully using verilog or simulated by
speed UART for programming FPGA. International Journal
Xilinx ISE. This design helps in reducing the routing
of Engineering and Computer Science,1(1), 28-36.
problems, issues related to cost, and also improves
[2]. Fang, Y. Y., & Chen, X. J. (2011, May). Design and
flexibility.
simulation of UART serial communication module based

Figure 3. Receiver Subsystem

Figure 4. Transmitter Subsystem

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ABOUT THE AUTHORS

Dharmendra Singh is currently working as an Assistant Professor in the Department of Electronics and Telecommunication
Engineering at Shri Shankaracharya Institute of Professional Management and Technology (SSIPMT), Raipur affiliated by CSVTU,
Bhilai, Chhattisgarh, India. He received his M.Tech Degree in Digital Electronics from Chouksey Engineering College, affiliated by
CSVTU, Bhilai in 2015. He is having 8 years of teaching experience. His specializations are Digital Electronics, Signal Processing,
Image Processing, Computer Networking and Hardware.

Upendra Soni is presently working as an Assistant Professor in the Department of Electronics and Telecommunication Engineering
at Shri Shankaracharya Institute of Professional Management and Technology (SSIPMT), Raipur affiliated by CSVTU, Bhilai,
Chhattisgarh, India. He received his M.Tech Degree in VLSI Design from ITM University, Gwalior in 2013. He has received his
Bachelor of Engineering Degree from Disha Institute of Management and Technolgy, Raipur affiliated from CSVTU, Bhilai during
2006-2010. His area of interest is in the field of VLSI Design.

Karan Shobhani is currently pursuing B.E. in Electronics and Telecommunication Engineering at Shri Shankaracharya Institute of
Professional Management and Technology, Raipur affiliated by CSVTU, Bhilai, Chhattisgarh, India.

Yash Karkashe is currently pursuing B.E. in Electronics and Telecommunication Engineering at Shri Shankaracharya Institute of
Professional Management and Technology, Raipur affiliated by CSVTU, Bhilai, Chhattisgarh, India.

Shubham Limje is currently pursuing B.E. in Electronics and Telecommunication Engineering at Shri Shankaracharya Institute of
Professional Management and Technology, Raipur affiliated by CSVTU, Bhilai, Chhattisgarh, India.

Aayush Nayak is currently pursuing B.E. in Electronics and Telecommunication Engineering at Shri Shankaracharya Institute of
Professional Management and Technology, Raipur affiliated by CSVTU, Bhilai, Chhattisgarh, India.

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