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LCD Binary Adder Ckts

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LCD Binary Adder Ckts

Uploaded by

Sibin
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Experiment 2

BINARY ADDER CIRCUITS


Name: SIBIN THOMAS SISIL
Roll No.: 39

1 Objectives
1. To implement half adder on breadboard and mini FPGA and to verify
its truth table.
2. To implement full adder on breadboard and mini FPGA and to verify
its truth table.
3. To implement four bit adder with 7483 IC and mini FPGA

2 Observations
The observations of experiments done on discrete ICs and FPGA are detailed
below.

2.1 Half adder circuit


The truth table is shown in Fig. 1.

The K-maps obtained from the truth table are shown in Fig. 2.

Therefore the logic function for the sum bit and carry bit in half adder is
Sn = X n ⊕ Y n (1)
Cn = Xn · Y n (2)
The circuit is shown in Fig. 3.
Figure 1: Truth table of halfadder

Figure 2: K-maps of halfadder

Figure 3: Circuit of half adder


2.1.1 Half Adder with ICs
The wiring diagram is shown in Fig. 4.
The IC is wired and applied various bit patterns to the input pins and the
output is obtained the truth table in Fig. 1.

2.1.2 Half adder with Verilog and Mini FPGA


The gate level Verilog model for half adder is listed in Code 1.
1 // module h a l f adder
2 module hadder ( output w i r e sum , c a r r y , i n p u t w i r e x , y ) ;
3 xor n1 ( sum , x , y ) ;
4 and n2 ( c a r r y , x , y )
5 endmodule
Listing 1: Verilog module for half adder
The code is tested with a mini FPGA and verified the truth table in Fig. 5.

2.2 Full adder circuit


The truth table is shown in Fig. 5.

The K-maps are shown in Fig. 6.

Therefore the logic function for the sum bit and carry bit in one bit full
adder is

S n = X n ⊕ Y n ⊕ C n-1 (3)
C n = X n · Y n + Y n · C n-1 + X · C n-1 (4)

The circuit is shown in Fig. 7.

2.2.1 Full Adder with ICs


The wiring diagram is shown in Fig. 8.
The IC is wired and applied various bit patterns to the input pins and the
output is obtained the truth table in Fig. 5.
Figure 4: Wiring diagram of halfadder

Figure 5: Truth table of full adder


Figure 6: K-maps of full adder

Figure 7: Circuit of full adder

Figure 8: Wiring diagram of full adder


2.2.2 Full adder with Verilog and Mini FPGA
The gate level Verilog model for half adder is listed in Code 2.
1 // module f u l l adder
2 module f a d d e r ( output w i r e sum , cout , i n p u t w i r e x , y , c i n ) ;
3 w i r e intersum , a , b , c , d ;
4 xor n1 ( intersum , x , y ) ;
5 xor n2 ( sum , intersum , c i n ) ;
6 and n3 ( a , x , y ) ;
7 and n3 ( a , x , y ) ;
8 and n4 ( b , x , y ) ;
9 and n5 ( c , x , y ) ;
10 o r n6 ( cout , a , b , c ) ;
11 endmodule
Listing 2: Verilog module for full adder
The code is tested with a mini FPGA and verified the truth table in Fig. 5.

2.2.3 Four bit adder circuit


Four one bit full adders are connected in parallel to result in a four bit adder.
The block diagram is shown in Fig. 9.

2.2.4 Full Adder with ICs


The wiring diagram is shown in Fig. 10 The IC is wired and applied various bit
patterns to the input pins and verified the addition of two four bit numbers.

Figure 9: Four bit parallel adder using full adder


Figure 10: Wiring diagram of four bit adder

2.2.5 Full adder with Verilog and Mini FPGA


The gate level Verilog model for four bit adder is listed in Code 3.
1 // module f o u r b i t adder
2 ‘include fadder . v
3 module f o u r b i t a d d e r (
4 output [ 3 : 0 ] sum ,
5 output cout ,
6 input [ 3 : 0 ] x ,
7 input [ 3 : 0 ] y ,
8 input cin
9 );
10

11 w i r e c0 , c1 , c2 ;
12

13 fadder f a 0 ( sum [ 0 ] , c0 , x [ 0 ] , y [ 0 ] , c i n ) ;
14 fadder f a 1 ( sum [ 1 ] , c1 , x [ 1 ] , y [ 1 ] , c0 ) ;
15 fadder f a 2 ( sum [ 2 ] , c2 , x [ 2 ] , y [ 2 ] , c1 ) ;
16 fadder f a 3 ( sum [ 3 ] , cout , x [ 3 ] , y [ 3 ] , c2 ) ;
17

18 endmodule
Listing 3: Verilog code for four bit full adder
The code is tested with a mini FPGA and verified the addition of two four
bit numbers.

3 Results
1. Verified half adder with discrete ICs and Verilog and mini FPGA board.

2. Verified full adder with discrete ICs and Verilog and mini FPGA board.

3. Verified fourbit adder with discrete ICs and Verilog and mini FPGA
board.

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