Republic of the Philippines

Laguna State Polytechnic University

Province of Laguna
COLLEGE OF ENGINEERING

ECE 10
DIGITAL ELECTRONICS 1

RESEARCH NO. 3
MULTIPLEXERS & DEMULTIPLEXERS
COMPARATOR
READ ONLY MEMORY
PROGRAMMABLE LOGIC ARRAY
INTRODUCTION TO SEQUENTIAL LOGIC

Alcantara, Mark Randolf, L.

BS ECE - 2B

OCTOBER 28, 2024

Submitted to:

Engr. Robert J. Calupitan

 MULTIPLEXERS & DEMULTIPLEXERS

Exploring the field of digital electronic circuits and specially by areas of

learning logic circuits, learners or undergraduates always configure the essential role

of logic, binary signals, boolean algebra, and principles of communication which are

building blocks of what technology has been till the present. Each of the parts of the

mentioned logic circuits’ foundation have more sub-functions and operations to

control over. An instance of these are multiplexers and demultiplexers.

Multiplexers and Demultiplexers have one definition in common. These are

digital circuits that are involved in routing signals for digital electronics. Yet, the two

are opposite in operation. The both are also classified under switching theories.

Multiplexers (MUX)

A multiplexer is a type of combinational circuit that facilitates the selection of a

single input from multiple available input lines and directs it to a singular output line.

It operates analogously to a multi-position switch, ensuring that only one input is

routed to the output at any moment.

In mathematical terms, a multiplexer functions as a data selector that receives

multiple input signals and produces a single output. In a multiplexer, there are 2^n

input lines and one output line, where n represents the number of selection lines.

Multiplexers follow combinational logic type while working on many to one

operational principles.

One specific type of this type of digital logic switch is time division

Multiplexing, where the multiplexer is used at the transmitter end. Advantages of

having multiplexers is the saving of space and power due to reducing the number of

lines or devices needed to distribute signals.

An illustration of a multiplexer is provided below to visualize its operation.

 Figure 1.1. Block Diagram of Multiplexer
https://www.geeksforgeeks.org/difference-between-multiplexer-and-demultiplexer/

Figure 1.1 presents an example of a multiplexer that follows a 2^1:1 ratio of

routing input to output respectively. Single-pole multi-position switch is a simple

non-electronic circuit of a multiplexer. These are suitable for both analog and digital

applications. In analog applications, they are constructed using relays and transistor

switches, while in digital applications, they are composed of standard logic gates.

When employed in digital contexts, the device is referred to as a digital multiplexer.

By its behavior of 2^1:1, multiplexers have input that are even in numbers and

can be classified by four types mainly, 2-1 multiplexer that has 1 select line, 4-1

multiplexer that has 2 select lines, 8-1 multiplexer that has 3 select lines, and 16-1

multiplexer that has 4 select lines.

Multiplexer, by being known as a data selector and digital switch, is composed

of logic gates that are identified as Sum of Products (SOP) operation. The

composition of this kind of logic circuit is adding the AND functions which are

products of inputs with paths of NOT or inverters. The output will be joint by the sum

of these products that utilize the final OR logic gate. An instance of these is a 4-1

multiplexer with 2 select lines that includes a circuit schematic.

 Figure 1.2. 4-1 Multiplexer
https://www.elprocus.com/what-is-multiplexer-and-demultiplexer-types-and-differenc

In Figure 1.2, a 4-to-1 multiplexer is given by terms of combinational logic

circuit. It consists of four input bits, one output bit, and two control bits. The input bits

are designated as D0, D1, D2, and D3, with only one input bit being transmitted to

the output at a time. The output, denoted as 'q', is determined by the value of the

control input AB. The control bits AB dictate which input data bit is transmitted to the

output. The circuit diagram of the 4-to-1 multiplexer, constructed using AND gates, is

illustrated below. For instance, when the control bits AB are set to 00, the upper AND

gate is enabled, while the remaining AND gates are disabled, allowing the input D0

to be passed to the output 'q'.

When the control input is set to 11, all gates are disabled except for the

bottom AND gate. In this scenario, the input D3 is transmitted to the output, resulting

in q = D3. A notable example of a 4-to-1 multiplexer is the IC 74153, where the

output matches the input. Another example is the IC 45352, in which the output is

the complement of the input.

Multiplexers and demultiplexers often come together to complete a design of

networking and other electronic transmissions applications. Demultiplexer will be

discussed after realizing the runthrough of a multiplexer.

 For real-world technologies, multiplexers are commonly used in computer

memory. Multiplexers are utilized in computer memory systems to manage large

amounts of memory efficiently and to minimize the number of copper lines needed

for connecting the memory to other components of the computer. Another application

is telephone networking since multiple audio signals are integrated on a single line of

transmission with the help of a multiplexer.

Demultiplexers (DEMUX)

Demultiplexers on the other hand, is a combinational circuit that takes a single

input and channels it to one of several output lines. It performs the reverse operation

of a multiplexer. A demultiplexer functions as a data distributor that accepts a single

input and produces multiple outputs. In a demultiplexer, there is one input line and

2^n output lines, where n still represents the number of selection lines the same in

multiplexers.

In summary, Demultiplexer receives digital information from a single source

and converts it into several sources. While a multiplexer is based as a digital switch,

demultiplexers are on the side of being a digital circuit instead. It works on one to

many operational principles and for time division multiplexing, a demultiplexer is

used at the receiver end.

Knowing demultiplexers and multiplexers have opposite or reverse operation,

they still are both space-saving and power-efficient due to being used to reduce the

number of input ports needed in associated devices. Example of demultiplexer is

sustained in the figure below showing the ratio 1:2^n relationships. One factor to

consider in demultiplexers and multiplexers are the selection lines. Selection lines

are employed to identify which input or output will be active at a given moment.

These lines enable the routing of a specific line as needed.

 Figure 1.3. Block Diagram of Demultiplexer
https://www.geeksforgeeks.org/difference-between-multiplexer-and-demultiplexer/

Figure 1.3 portrays the block diagram of a demultiplexer and how it behaves

and runs. Due to having only 1 input, the demultiplexer works to distribute it to

multiple outputs showing 1:2^n ratio where output is also in base of 2 exponentially.

Such demultiplexers are commonly implemented using semiconductor components

such as CMOS devices or Heterojunction Bipolar Transistors (HBT).

Similar to multiplexers, demultiplexers have also its types such as 1-2

demultiplexer with 1 select line, 1-4 demultiplexer with 2 select lines, 1-8

demultiplexer with with 3 select lines, and finally 1-16 demultiplexer with 4 select

lines. But unlike multiplexers, when constructing digital logic circuits, the operation is

not in Sum of Products (SOP) anymore to add all the inputs. Because demultiplexers

have only a single input, the circuit is designed to have multiple AND logic gates to

produce the data distribution or required outputs.

Some real-world application of demultiplexers is the building of Arithmetic

Logic Unit or ALU. The output of the ALU is supplied as an input to the demultiplexer,

whose output is then linked to multiple registers. This allows the ALU output to be

stored in several registers. Demultiplexers in other applications can also be used to

reconstruct parallel data in serial to parallel converters.

 Figure 1.4. 1-8 Demultiplexer
https://www.elprocus.com/what-is-multiplexer-and-demultiplexer-types-and-differenc

A 1-to-8 Demultiplexer logic circuit schematic is given above in Figure 1.4.

The demultiplexer, also referred to as a data distributor, requires one input, three

selection lines, and eight output lines. It accepts a single input data line and directs it

to one of the output lines. The circuit diagram of a 1-to-8 demultiplexer utilizes eight

AND gates to perform this operation.

The input bit, referred to as data D/I, is transmitted to the output lines based

on the control input value of AB. When AB = 01, the second gate, F1, is activated,

while the other AND gates remain disabled, allowing the data bit to be transmitted to

the output, resulting in F1 = data. If D is low, F1 will also be low; if D is high, F1 will

be high. Therefore, the value of F1 depends on the value of D, with the other outputs

remaining in a low state.

The data conversion method employed in a multiplexer (MUX) is

parallel-to-serial, which is relatively straightforward as it involves multiple inputs. In

contrast, a demultiplexer (DEMUX) operates in the opposite manner, performing a

serial-to-parallel conversion. As a result, it can achieve multiple outputs. Alongside,

there are also advantages and disadvantages for multiplexers and demultiplexers.
Table 1.1. ADVANTAGES & DISADVANTAGES OF MULTIPLEXERS

MULTIPLEXERS

ADVANTAGES DISADVANTAGES

The usage of a number of wires can be Additional delays required within

decreased switching ports & I/O signals which
propagate throughout the MUX

Reduces the cost as well as the The ports which can be utilized at the
complexity of the circuit same time have limitations

Doesn’t require K-maps & simplification Switching ports can be handled by

adding the complexity of firmware

Dissipation of heat is less because of The controlling of multiplexer can be

the analog switching current which done by using additional I/O ports
ranges from 10mA to 20mA

Can be extended to switch audio

signals, video signals, etc.

Table 1.2. ADVANTAGES & DISADVANTAGES OF DEMULTIPLEXERS

DEMULTIPLEXERS

ADVANTAGES DISADVANTAGES

Used to divide the mutual signals back Bandwidth wastage might happen
into separate streams.

Used as a decoder within the security Because of the synchronization of the

systems of banking sectors. signals, delays might take place

Communication system efficiency can

be enhanced
 COMPARATOR

A comparator is a combinational circuit that compares two binary inputs to

assess their relative magnitude. It generates one or more output signals that indicate

whether one input is greater than, less than, or equal to the other. Binary or digital

comparators can be constructed using standard AND, NOR, and NOT gates to

compare the digital signals at its input terminals and generate an output based on

the conditions of those inputs. Comparators are known to be used in microcontrollers

(MCU) and central processing units (CPU) that the world knows until this time.

In addition to performing binary addition and subtraction, it is essential to

compare binary numbers to determine whether the value at input A is greater than,

less than, or equal to the value at input B, among other conditions. The digital

comparator achieves this by utilizing several logic gates that operate based on the

principles of Boolean algebra. This digital comparator has mainly two types

mentioned below.

Types of Digital Comparator

1. Identity Comparator

A digital comparator with only one output terminal for when A=B, either A=B=1

(HIGH) or A=B=0 (LOW).

2. Magnitude Comparator

a digital comparator which has three output terminals, one each for equality

(A = B), greater than (A > B) and less than (A < B).

The function of a digital comparator is to compare a set of variables or

unknown values, denoted as A (A1, A2, A3, … An, etc.), with a constant or another

set of variables, represented as B (B1, B2, B3, … Bn, etc.), and generate an output

condition or flag based on the outcome of the comparison. For example, a

magnitude comparator with two 1-bit inputs, A and B, would yield three distinct

output conditions based on their relative comparison. (A>B, A=B, A<B), meaning A is

greater than B, A is equal to B, or A is less than B.

This is beneficial when comparing two variables and generating an output

upon the fulfillment of any of the three conditions mentioned. For instance, it can be

used to trigger an output from a counter when a specified count value is reached.

Since digital comparator is constructed by combinational logic circuits, a basic

example of this is a 1-bit digital comparator circuit.

Figure 2.1. 1-Bit Digital Comparator Circuit

https://www.electronics-tutorials.ws/combination/comb_8.html

Figure 2.1 reveals a 1-bit digital comparator that composes inverter logic or

NOT, AND logic, and NOR logic which are combined in a sequential manner to

produce different outputs that match the function of a digital comparator. Naming the

outputs C=A’B which A is less than B, while output D=(A’B+AB’)’ concludes that input

A is equal to input B, and last output E=AB’ showing input A is greater than B. In

observation, a complement of either inputs of A or B will give a LOW logic output

while a non-complement of either inputs of A or B will give a HIGH logic output.

Based on these functions, the digital comparator can compare the individual inputs.

By this boolean expression and logic operations, a truth table can be created

for a digital comparator. According to the combinational logic circuit and following the

given inputs and outputs, the truth table will present as shown below.
Table 2. Digital Comparator Truth Table

INPUTS OUTPUTS

B A A>B A=B A<B

0 0 0 1 0

0 1 1 0 0

1 0 0 0 1

1 1 0 1 0

Table 2 shows the possible outputs in a specific inputs given. Two notable

characteristics of this simple comparator can be observed from the truth table above.

First, the circuit does not differentiate between the two inputs being "0" or "1." The

output A = B is generated when both inputs are equal, meaning that either A = B =

"0" or A = B = "1.". The output condition for A = B is similar to the function of a

commonly available logic gate, the Exclusive-NOR (X-NOR) gate, which performs

equivalence on each of the n-bits, resulting in Q = (A ⊕ B)’.

Digital comparators utilize Exclusive-NOR gates in their design to compare

corresponding pairs of bits. When comparing two binary or BCD values or variables,

we are assessing the "magnitude" of these values, contrasting a logic "0" with a logic

"1," which is the origin of the term "Magnitude Comparator."

Beyond comparing individual bits, it is possible to design comparators for

larger bit-widths by cascading multiple components, thereby creating an n-bit

comparator, analogous to the method used in the previous tutorial for constructing an

n-bit adder. Multi-bit comparators can be implemented to evaluate entire binary or

BCD words, producing an output that indicates whether one word is greater than,

equal to, or less than the other.

 Figure 2.2. 4-bit Magnitude Comparator
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A block diagram of a 4-bit magnitude comparator is provided in figure 2.2 as

an example of a larger bit of magnitude comparator. In this case, two 4-bit words

known as "nibbles" are compared to generate the corresponding output, with one

word connected to input A and the other, to be compared, connected to input B.

By the comparison of large binary or BCD numbers, as demonstrated in the

example above, the comparator initiates the process by comparing the most

significant bit (MSB) to optimize efficiency. If equality is established (A = B), the

comparison proceeds to the next bit in descending order until the least significant bit

(LSB) is reached. If equality is preserved across all bits, the two numbers are

determined to be equal.

Applications of digital comparators that are commonly used in industries are

data sorting and searching. Comparators are essential in algorithms for sorting and

searching, where values need to be compared to each other to arrange or find data.

Another instance is control systems that make use of digital comparators to

compare sensor readings with set thresholds and trigger actions accordingly. Finally,

digital comparators can be used in digital clock and timer synchronization due to

being employed to compare a given signal’s frequency with a reference signal in

frequency counters and analyzers. Signal integrity and error detection can bring

comparators to play by comparing received signals against expected values.

 READ ONLY MEMORY

Modern computers have modular parts that work as a puzzle in order for a

machine to operate. From any technology companies that offer components may mix

the building blocks of a computer. This includes the central processing unit which is

the heart of the computer, the motherboard that connects the individual parts of the

PC, the RAM or Random Access Memory, that manages multitasking activities in a

system, the power supply unit that delivers and regulates the required power and

electricity for the computer, and finally, the storage that is based in ROM or Read

Only Memory. Read Only Memory is one of the essential factors of any

contemporary electronic technology since it is the one responsible for storing

permanent data such as startups, applications, and much more in a chip.

Memory is a fundamental component of computer systems, responsible for

storing data for both immediate access and long-term retention. Computer memory

is broadly classified into two types based on its operational characteristics: volatile

and non-volatile memory. A comprehensive understanding of these categories is

essential before delving into the specifics of ROM (Read-Only Memory).

Non-volatile memory is defined as a type of memory capable of retaining

stored data even when the power supply is disconnected. This type of memory is

generally more cost-effective and has a higher storage capacity compared to volatile

memory. Common examples of non-volatile memory include ROM and flash memory.

In contrast, volatile memory is characterized by its temporary nature, where data is

retained only while the system is powered. When the power is interrupted, all stored

data in volatile memory is lost. RAM (Random Access Memory) serves as a primary

example of volatile memory.

 Figure 3.1. Read Only Memory
https://www.thoughtco.com/definition-of-rom-958317

Read-Only Memory (ROM) is a form of non-volatile storage that plays a

crucial role in maintaining essential data necessary for system functionality. As

implied by its designation, ROM permits only the retrieval of pre-stored programs

and data, making modifications impossible after initial programming. It constitutes a

key component of a computer system's primary memory architecture. ROM's

structure incorporates programmable electronic fuses, allowing it to be configured

with specific data, which is encoded in binary format. Due to its non-volatile nature,

ROM is often referred to as permanent memory, as it preserves data even without

power.

Figure 3.2. Block Diagram of ROM

https://www.geeksforgeeks.org/read-only-memory-rom/

Figure 3.2 discerns the block diagram of a Read-Only Memory. The structure

comprises k input lines and n output lines, where the k input lines are utilized to

designate the address from which the ROM content is accessed. Given that each of
the k input lines can independently assume a binary value of 0 or 1, a total of 2^k

unique addresses can be referenced. Each of these addresses corresponds to n bits

of stored information, which are subsequently output from the ROM.

While a read only memory is embedded on a chip or integrated circuit, the

elements that complete the ROM can be distinguished. Thus, the two basic internal

components of a read-only memory are the decoder and the OR gates. A circuit

schematic of the internal structure of ROM is recorded below.

Figure 3.3. Circuit Schematic 64x4 ROM

https://www.geeksforgeeks.org/read-only-memory-rom/

The two major electronic devices can be found in Figure 3.3 with specific

constructions to perform a read-only memory peripheral. The decoder is a circuit

designed to translate encoded data, such as binary-coded decimal (BCD), into a

more interpretable format, such as a decimal representation. The resulting output

corresponds to the binary form of the input provided. In the context of ROM, the

decoder’s outputs align with the outputs of each OR gate. For example, in a 64 x 4

ROM configuration, there are 64 memory words, each comprising 4 bits, yielding four

output lines. The presence of six input lines allows for the specification of 64 unique

addresses or minterms, thereby enabling the selection of one out of the 64 stored
words based on the input address. Each input combination uniquely identifies and

retrieves a specific word from the memory.

A small, durable battery powers the ROM within a computer, which is primarily

composed of two key components: OR logic gates and a decoder. The decoder in

ROM receives binary input and generates a decimal output, which subsequently

serves as the input for the OR gates. ROM chips are structured in a grid

configuration, consisting of rows and columns that can be selectively activated or

deactivated. When activated, a value of 1 is represented, with the rows and columns

connected via a diode; when deactivated, the value is 0, with no connection

established between the lines. Each intersection in this grid corresponds to an

individual storage element within the memory chip. The diodes permit current flow in

only one direction, with a specific forward break-over threshold, typically around 0.6

V for silicon-based components, determining the current necessary for the diode to

conduct. ROM chips may transmit a charge exceeding the forward break-over

voltage to a designated column and row, with the cell in question being grounded. In

the presence of a diode at the intersection, the charge is converted to a binary state,

with the cell being activated (or "on") and assigned a value of 1.

Covering the information about read only memory, this can conclude that a

ROM is utilized during the startup process of computers that makes the stored data

available due to non-volatile memory classification. Often instances of read only

memory during startup of computers is the boot firmware, basic input/output system

or also known as “BIOS”. This software consists of code that instructs the boot-up

processes for the computer with the help of ROM.

Read-only memory also has different types according to its functions and

utilization. ROM has evolved since it is an old semiconductor device.

Types of Read-Only Memory

1. Masked Read-Only Memory (MROM)

MROM, the first generation of ROM, is defined by a grid structure of word

lines and bit lines interconnected through transistor switches. Data in this type

of ROM is physically encoded within the circuitry and can only be

programmed during the manufacturing process. This form of ROM is also

considered to be relatively inexpensive.

2. Programmable Read-Only Memory (PROM)

PROM is a type of digital memory in which each bit is permanently encoded

through the use of fuses or anti-fuses. Once programmed, the data within

PROM cannot be altered or erased. This type of memory is typically employed

in low-level applications, including firmware and microcode.

3. Erasable Programmable Read-Only Memory (EPROM)

EPROM, also known as EROM, is a type of PROM that can be

reprogrammed. The data stored in EPROM can be erased and reprogrammed

using high voltages and exposure to ultraviolet light for about 20 minutes.

However, the number of times it can be reprogrammed is limited. Prior to the

advent of EEPROM and flash memory, EPROM was commonly used in

microcontrollers.

4. Electrically Erasable Programmable Read-Only Memory (EEPROM)

EEPROM supports multiple erasure and reprogramming cycles, though it

restricts the modification to a single memory location at a time. In contrast,

flash memory represents an enhanced iteration of EEPROM, facilitating the

concurrent modification of multiple memory locations. The duration of erasing

and programming of the EEPROM is about 4ms to 10ms.

Applications of Read-Only Memory

ROM plays a critical role in facilitating communication between various

hardware components by providing the necessary instructions. As highlighted earlier,

it is indispensable for the storage and execution of the BIOS. Moreover, ROM serves

other functions, including basic data management, the storage of software for

fundamental utility processes, and enabling read and write operations with peripheral

devices. There are a ton more real-life applications to technology using read-only

memory.

a. Firmware Storage in Electronics

ROM is widely employed for storing firmware, which consists of permanent

software integrated into hardware devices. This includes applications in

devices such as printers, cameras, and household appliances, where the

integrity and immutability of the software are essential for proper functionality.

Figure 3.4.1. Phone Motherboard with ROM

https://www.istockphoto.com/photos/cell-phone-components

b. Game Consoles

Many older video game consoles utilize ROM cartridges for storing game

data. These cartridges offer a dependable, unalterable medium for game

software, ensuring that the game can be played without the risk of data

corruption.
 Figure 3.4.2. Nintendo Entertainment System
https://www.billboard.com/culture/product-recommendations/retro-gaming

c. Embedded Systems

In embedded systems, ROM serves to store essential programs that regulate

the functioning of various devices, such as medical equipment, automotive

control systems, and industrial machinery. The data within these systems is

preserved in a stable form to ensure continuous and dependable operation.

Figure 3.4.3. Electronic Medical Equipment

https://marianinc.com/medical-electronics-devices/

d. Bootstrapping Devices

ROM is also employed to store the initial bootstrapping code necessary for

loading an operating system or other essential software. This is typically

observed in devices such as routers and networking equipment.

 Figure 3.4.4. Internet Router
https://www.asus.com/us/networking-iot-servers/wifi-routers/asus-gaming-routers/

e. Cryptographic Systems

ROM is utilized to store encryption keys in security devices, where

maintaining the integrity of the data is crucial and must be preserved without

alteration.

Advantages & Disadvantages of Read-Only Memory

The evolution of ROM is significantly effective to the systems of electronic

designs and technologies. With this, identifying the advantages and disadvantages

of ROM is practical most of all for considering its functions and operations.

Table 3. Advantages & Disadvantages of Read-Only Memory

ADVANTAGES DISADVANTAGES

Cheaper than RAM and it is non-volatile It cannot be modified due to read-only

memory. memory.

Doesn’t need refreshing time because it It is slower as compared to RAM.

is static.

Contents of the ROM can always be

known and verified.
 PROGRAMMABLE LOGIC ARRAY

A Programmable Logic Array or PLA is a programmable device employed in

the field of digital electronics for the realization of combinational logic circuits. It is

composed of a network of programmable AND gates and OR gates, facilitating the

design and implementation of user-defined logic functions. PLA is a type of

programmable logic device designed for constructing reconfigurable digital circuits

within its architectural framework. It integrates both memory elements and logic

operations, enabling users to program the device to execute specific logical

functions. As highlighted in the literature, PLAs are manufactured without any

predefined function and are configured for their intended operations during the

programming phase prior to deployment.

This type of digital logic circuit processes multiple input variables and

generates output signals based on the logic specified within its programmed

configuration. Unlike fixed logic circuits, PLAs offer significant flexibility, as they

enable users to define and program the interconnections between input variables,

AND gates, and OR gates to implement specific logic operations. Yet, when

comparing it to Programmable Array Logic (PAL) or Field-Programmable Gate Arrays

(FPGA), the programmable logic array may lack efficiency in terms of speed and

cost. While in contexts of logic circuits, PLA tends to be versatile since it has a

programmable AND gate array and programmable OR gate array rather than PAL

that has programmable AND gate array but a fixed OR gate array and ROM that has

a fixed AND gate array and only OR gate array are programmable. The

Programmable Logic Array shares conceptual similarities with a Read-Only Memory;

however, it does not fully decode input variables or generate all possible minterms,

as seen in ROM implementations.

 Although the term "programmable" is associated with its name, configuring a

PLA does not involve traditional programming practices, such as using languages

like C or C++. For more in depth understanding, the block diagram of a PLA is

provided for visualization.

Figure 4.1. Block Diagram of PLA

https://www.tutorialspoint.com/digital-electronics/programmable-logic-array.htm

In figure 4.1, there are several logic gate components that are present to

create a programmable logic array. The first block includes the input buffer which is

employed to prevent the loading effect on the source driving the input signals in a

PLA. Following the process after the input buffer, the AND matrix or array will

function in PLA to generate the product terms. Then, the OR array or matrix is

utilized to generate the desired output by performing the logical OR operation on the

product terms to produce the sum terms. Next is similar to the first input buffer where

the invert or non-invert matrix is a buffer used in PLAs to set the output to active-high

or active-low. Finally, the output buffer is used at the output side. It is mainly provided

to increase the driving capability of the programmable logic array. Here in PLA, all

the minterms are not realized but only required minterms are implemented.

In the field of digital electronics, the PLAs are extensively used for designing

combinational logic circuits. For instance, building a full-adder circuit can be

accomplished using a programmable logic array by designing and developing each

buffer gate, AND gate, and OR gate to generate the exact desired outputs. The

following is an example and procedure of designing a full-adder circuit using PLA.

Table 4.1. Full-adder Truth Table

INPUTS OUTPUTS

A B Cin S Cout

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

In table 4, the full-adder truth table comprises three inputs and two outputs.

With three inputs, there are a total of eight product terms, as outlined in the following

truth table for the full adder. That being output S is the Sum while output Cout is the

output carry of the full-adder. While examining the truth table, forming the minterms

together can give us the output sum S=∑m(1,2,4,7) and the output carry

Cout=∑m(3,5,6,7). In further simplification, the karnaugh map can be implemented.

Figure 4.2. K-Map for Sum (S) and Carry Out (Cout)
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Given the karnaugh maps of Sum (S) and Carry Out (Cout) in figure 4.2, the

boolean expression can be determined by the placement of output “1” in the K-Map.
 According to the karnaugh map of sum (S), the total number of individual

boolean expressions are 4 which are products of the inputs A, B, and Cin. Then it will

be joined by a sum operation (OR). The boolean expression for Sum (S) is

S=A’BCin’ + A’B’Cin + AB’Cin’ + ABCin. Same process for the boolean expression of

the Carry Out (Cout) having only 3 individual product expressions. Carry out (Cout)

boolean expression is therefore, Cout=AB + BCin + ACin. From these two Boolean

expressions, we can see that there are seven product terms and two sum terms.

Thus, formulating the programmable logic array program table is now possible based

on the boolean expressions.

Table 4.2. PLA Program Table

Sr.No Product INPUTS OUTPUTS

Terms
A B Cin S Cout

1 A’BCin’ 0 1 0 1 -

2 A’B’Cin 0 0 1 1 -

3 AB’Cin’ 1 0 0 1 -

4 ABCin 1 1 1 1 -

5 AB 1 1 - - 1

6 BCin - 1 1 - 1

7 ACin 1 - 1 - 1

T T

The table 4.2 consists of the PLA program table that proves the

implementation for a full-adder circuit. In the PLA programming table, "1" signifies

the presence of a connection, whereas "-" indicates the absence of a product term in

the output. The symbol "T" represents a true value, denoting an active-high output.

This is upon the completion of PLA as a full-adder circuit.

 The final procedure is to design and develop the combinational logic circuit for

programmable logic array based on the program table being a full-adder circuit.

Figure 4.3. Combinational Logic Circuit Schematic for PLA

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Figure 4.3 gives the overview of the construction of the combinational logic

circuit required for making a programmable logic array specifically for full-adder

operation and functions.

In conclusion, a Programmable Logic Array or PLA is a digital logic device

designed to implement complex digital functions, eliminating the need for discrete

components like AND gates, OR gates, and similar elements. This chapter has

outlined the foundational principles and various applications of PLAs.

Applications of Programmable Logic Array

1. Programmable Logic Arrays (PLAs) are employed in the field of digital signal

processing to implement a range of logical functions, including filtering,

convolution, Fourier transformation, and others.

2. In control systems, Programmable Logic Arrays (PLAs) are utilized to

implement control logic functions for various components, such as feedback

mechanisms, PID controllers, state machines, and others.

 Figure 4.4.1. Proportional-Integral-Derivative Controller
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3. Programmable Logic Arrays are employed to execute various arithmetic

operations, including addition, subtraction, multiplication, and division.

4. Programmable Logic Arrays are also applied in data compression and

encryption technologies. In digital communication systems and networking

equipment, PLAs are utilized to implement algorithms for protocol handling,

packet processing, error detection and correction, among other functions.

5. Programmable Logic Arrays are also utilized in various measuring

instruments, including digital oscilloscopes, protocol analyzers, logic

analyzers, and others.

Figure 4.4.2. Digital Oscilloscope

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 INTRODUCTION TO SEQUENTIAL LOGIC

Sequential logic in digital electronics refers to a type of circuit whose output

depends not only on the current inputs but also on the prior sequence of inputs,

indicating that it possesses memory. In contrast to combinational logic, where the

output is determined solely by the present input values, sequential logic circuits

retain information about previous states, which affects their current output.

These circuits are defined by the presence of storage elements such as

flip-flops, latches, or registers that store the system's state. Sequential logic is

commonly employed in applications where it is necessary to remember previous

events or perform operations that require a specific sequence, including counters,

shift registers, memory units, and finite state machines.

One factor about sequential circuits is that it is a type of combinational logic

circuit composed of input variables (X), logic gates (computation circuit), and output

variables (Z). The block diagram of the sequential circuit should be in this form.

Figure 5.1. Block Diagram of Sequential Circuit

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Figure 5.1 deploys the block diagram of a combinational circuit that generates

an output solely based on the input variables, whereas a sequential circuit produces

an output that depends on both the current input and the previous output variables.

This indicates that sequential circuits incorporate memory elements capable of

storing binary information. This stored binary information determines the current

state of the sequential circuit. A latch, for instance, can store one bit of information.

Another example of a block diagram of sequential logic will be shown below.

 Figure 5.2. Block Diagram of Sequential Logic with Memory
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As shown in the figure 5.2, there are two types of input to the combinational

logic. The first is the external inputs which are not controlled by the circuit while the

second is the internal inputs which are a function of a previous output state. Lastly,

Secondary inputs are state variables produced by the storage elements, whereas

secondary outputs are excitations for the storage elements.

Flip Flops

A flip-flop is a fundamental digital memory circuit that stores a single bit of

information. It serves as the basic building block for most sequential circuits and is

also referred to as a bistable multivibrator, binary memory, or one-bit memory.

Flip-flops function as memory elements in sequential circuits. In such circuits, output

can be derived from the combinational circuit, the flip-flop, or a combination of both.

The state of flip-flops changes during the active phase of clock pulses and remains

unchanged when the clock pulse is inactive. Specifically, clocked flip-flops act as

memory elements in synchronous sequential circuits, while unclocked flip-flops

(latches) function as memory elements in asynchronous sequential circuits.

Types of Flip Flops

1. S-R Flip Flop

This stands for Set-Reset Flip Flop. It has two inputs: Set (S) and Reset (R),

and two outputs: Q and Q’ (not Q). When S is turned on, the output Q

becomes 1. When R is turned on, Q becomes 0. If both S and R are 0, the

flip-flop keeps its last state. However, having both S and R as 1 at the same

time is usually avoided because it can lead to unpredictable behavior.

Figure 5.2.1. S-R Flip Flop Equivalent Combinational Logic

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2. T Flip Flop

The T in T flip-flop stands for "Toggle." This type of flip-flop has a single input,

T, and two outputs, Q and Q'. When T is 0, the state remains unchanged.

However, when T is 1, the flip-flop toggles its state, if Q was 1, it switches to

0, and if Q is 0, it switches to 1. This behavior is particularly useful for

implementing counters or frequency division in digital circuits.

Figure 5.2.2. T Flip Flop Equivalent Combinational Logic

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3. J-K Flip Flop

This flip-flop can be considered an enhanced version of the S-R flip-flop. It

has two inputs, J and K, along with two outputs, Q and Q'. When J is 1 and K

is 0, the output becomes 1. Conversely, when J is 0 and K is 1, the output is

set to 0. If both J and K are 0, the output retains its previous state. A

distinguishing characteristic occurs when both J and K are 1, causing the

flip-flop to toggle its state, switching 1 to 0 or 0 to 1.

Figure 5.2.3. J-K Flip Flop Equivalent Combinational Logic

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4. D Flip Flop

The D in D flip-flop stands for "Data" or "Delay." This flip-flop has a single

input, D, and two outputs, Q and Q'. It is straightforward to use, as the value

present on the D input (0 or 1) is transferred to the Q output when the flip-flop

is triggered. It is commonly employed for temporary data storage or for

synchronizing signals within digital systems.

Figure 5.2.4. D Flip Flop Equivalent Combinational Logic

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Latches

A latch is an electronic device that updates its output instantaneously in

response to the applied input. It is used to store a binary value, either 1 or 0, at any

given time. The latch has two inputs, labeled SET and RESET, and two outputs that

are complementary to each other.

Types of Latches

1. S-R Latch

S-R latches, or Set-Reset latches, represent the most basic type of latch and

are constructed using two inputs: S (Set) and R (Reset). The S input sets the

output to 1, while the R input resets the output to 0. If both S and R inputs are

simultaneously set to 1, the latch enters an "undefined" state. These states

are also referred to as preset and clear states. The S-R latch serves as the

fundamental building block for all other types of flip-flops.

Figure 5.2.5. S-R Latch Equivalent Combinational Logic

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2. D Latch

D latches, also referred to as transparent latches, are implemented with two

inputs: D and a clock signal. The output of the latch follows the input at the D

terminal while the clock signal is high. Once the clock signal transitions to low,

the latch stores and retains the output until the next rising edge of the clock.

Figure 5.2.6. D Latch Equivalent Combinational Logic

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3. J-K Latch

JK latch has two inputs J and K. The output gets toggled when the J and K

inputs are high. JK latch is just like SR latch, but it eliminates the undefined

state of SR latch.

Figure 5.2.7. J-K Latch Equivalent Combinational Logic

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 4. T Latch

When the JK inputs of a JK latch are connected together, the result is a T

latch. In a T latch, the outputs toggle when the input is high.

Figure 5.2.8. T Latch Equivalent Combinational Logic

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Registers & Register Design

Registers, which consist of groups of flip-flops, are used to enhance storage

capacity. By utilizing n flip-flops, a register can store an n-bit word. Thus, Register

design in sequential logic involves the creation and configuration of registers, which

are composed of flip-flops used for storing and managing data in digital systems.

Registers are essential components in sequential circuits, as they store binary

information and are commonly employed to retain intermediate results, control

signals, or data in operations such as computation, data transfer, and

synchronization.

The register design process aims to ensure that the register efficiently stores

and manages data in alignment with the specific requirements of the sequential logic

circuit, while also taking into account factors such as speed, control, and

synchronization. In register design, there are key aspects required to consider to

successfully arrange a sequential logic system. The following is included in register

design.
1. Selection of Flip Flops

The choice of flip-flops (D, T, JK, etc.) in the register depends on the desired

functionality, such as whether the register must store data on a particular

clock edge or perform toggling.

2. Clocking Mechanism

Registers typically operate synchronously with a clock signal, with clocked

registers updating their stored data at defined intervals, usually on the rising

or falling edge of the clock pulse.

3. Control Inputs

Registers may include control inputs such as enable, load, clear, or reset

signals to regulate when data is stored, modified, or cleared. The design

process must consider how these control signals interact with the flip-flops

within the register.

4. Data Width

The width of a register, defined by the number of flip-flops, is determined by

the number of bits it is intended to store. For instance, a register designed to

store an n-bit value would consist of n flip-flops.

5. Parallel & Serial Registers

Registers can be designed for either parallel or serial data storage. Parallel

registers store multiple bits simultaneously, whereas serial registers transfer

bits one at a time.

6. Timing & Synchronization

Since sequential circuits rely on the state of flip-flops, careful attention must

be given to the timing and synchronization of the clock signal to ensure

correct data storage and retrieval.

Types of Registers

Registers are used to perform various types of operations, with the CPU

utilizing these registers to carry out tasks. The input data to the system is stored in

the registers, and the results produced by the system are also stored within the

registers. There are several types of registers to be executed with distinct behaviors.

1. Memory Address Register

The Memory Address Register (MAR) is a specialized register that holds the

memory address of data and instructions. Its primary function is to retrieve

instructions and data from memory during the execution phase. The MAR

stores the address of the memory location from which the CPU reads data or

where it writes data.

2. Accumulator Register

The accumulator register is commonly used by the CPU to store the system's

results. After processing, the CPU stores all generated results in the

accumulator register.

3. Memory Data Register

The Memory Data Register (MDR) is a component of the computer's control

unit. It holds the data that is either to be stored in the computer's memory or

has been fetched from memory. The MDR functions as a buffer, temporarily

storing data that the processor is ready to use. It contains a copy of the data

from memory, which is first held in the MDR before being passed to the

decoder for further processing.

4. Shift Register

A digital memory circuit that stores and shifts data through a series of internal

relays or flip-flops.
Counters & Counter Design

A counter is a device that stores and sometimes displays the number of times

a specific event or process has occurred, typically in relation to a clock signal. In

digital electronics, counters are used for counting purposes, tracking specific events

occurring within a circuit. For instance, in an up counter, the count increases with

each rising edge of the clock.

Hence, A counter is a sequential circuit constructed using flip-flops, designed

to count the number of clock signals or pulses. A mod n counter counts from 0 to

n-1. Counters can be classified as synchronous or asynchronous. In a synchronous

counter, all flip-flops share a common clock signal. In contrast, an asynchronous

counter applies the clock input only to the first flip-flop, while the clock pulses for the

intermediate or subsequent flip-flops are derived from the output of the preceding

flip-flop.

For Counter Designing, there are also key factors to consider for successful

implementation of counters in sequential logic. One of these is the type of counter

needed. There are two classifications of counters being the asynchronous and

synchronous counters which have different operations. Counting Sequence is also a

crucial part for designing counters since this depends on the increment and

decrement of values of the clock. And of course, the modulus which indicates the

number of distinct states it cycles through before returning to its initial state. For

instance, a mod-10 counter counts from 0 to 9 and then resets to 0.

When designing a counter, key considerations include the selection of

flip-flops, the type of counter like up/down, binary, and the modulus or the number of

states the counter will have. These factors are essential in determining the counter's

functionality and performance.

 Figure 5.4.1 Clock Sequence
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Table 5.4.1. Transition Table Logic

Present State Next State

0 1

1 3

3 4

4 5

5 7

7 0

In figure 5.4.1 shows a diagram of a sequence that is needed to be designed

in a sequential circuit. Table 5.4.1 on the other hand is a tabular figure of the

sequence above, since the language of sequential logic is in binary, the next process

in order to construct a counter is to set the values of the sequences which are

decimal into binary code.

Table 5.4.2. Binary Coded Transition Table

Present State Next State

Q3 Q2 Q1 Q3(t+1) Q2(t+1) Q1(t+1)

0 0 0 0 0 1

0 0 1 0 1 1
 0 1 1 1 0 0

1 0 0 1 0 1

1 0 1 1 1 1

1 1 1 0 0 0

After stating table 5.4.2, the binary coded transition table, using a type of flip

flop is essential. For this instance, T Flip Flop will be utilized as its condition is: If

value of Q changes either from 0 to 1 or from 1 to 0 then input for T flip-flop is 1 else

input value is 0. Using T Flip Flop Excitation Table.

Table 5.4.3. T Flip Flop Excitation Table

Qt Qt+1 T

0 0 0

0 1 1

1 0 1

1 1 0

The next process upon completing T flip flop shown in table 5.4.3,

Constructing the input table for all T flip-flops using the excitation table of the T

flip-flop. Given that the T flip-flop operates in a toggle mode, the output Q3

represents the most significant bit, while Q1 represents the least significant bit.

Table 5.5.4. Input Table of Flip Flops

T3 T2 T1

0 0 1

0 1 0

1 1 1

0 0 1
 0 1 0

1 1 1

Table 5.5.4 presents the input table of flip flops for the sequence given.

Provided the plots of T3, T2, and T1, finding the value of T3, T2, T1 in terms of Q3,

Q2, Q1 using K-Map is possible.

Figure 5.4.2. K-Map of T3, T2, & T1

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Once the karnaugh map of T3, T2 and T1 is computed, the values of

themselves are solved by examining the outputs of logic 1 inside the K-Map.

Therefore, the values required for the sequence are T3=Q2, T2=Q1, & T1=Q2+Q1’.

Finally, the values given from the solutions can be formulated to design a

combinational logic circuit that can be equivalent to a sequential circuit with the

specified sequence and clock. This is the complete process of designing counters by

a given sequence.
 Figure 5.4.3. Logic Circuit Diagram Equivalent
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Arithmetic Logic Unit Function

An Arithmetic Logic Unit or ALU is a digital component employed to carry out

arithmetic and logical operations within sequential circuits, commonly as a part of the

Central Processing Unit or CPU. The ALU is tasked with performing various

operations, including addition, subtraction, multiplication, division, bitwise logical

operations such as AND, OR, XOR, NOT, and comparison tasks. It also handles the

logical operations, enabling complex computations and decision-making within digital

systems.

Defying the ALU in some context, it is known for being the “heart” of a

processor or CPU due to the support and function it gives to give the processor its

purpose. In certain processors, the Arithmetic Logic Unit is split into two distinct

units: an Arithmetic Unit (AU) and a Logic Unit (LU). Additionally, some processors

may feature multiple Arithmetic Units. ALU has direct input and output connections to

the processor controller, main memory (RAM & ROM), and i/o devices. Data flows

between these components through an electronic pathway known as a bus.

 Figure 5.5.1. Schematic Symbol of ALU
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Figure 5.5.1 previews the typical schematic symbol of an arithmetic logic unit.

It is composed of 5 parts. The inputs to the ALU is the variable A & B which are also

referred to as operands while variable R is the output of the ALU. For variable F, it

represents the code or instruction from the Control Unit and lastly, variable D depicts

the Output status; it indicates cases such as carry in, carry out, overflow, division by

zero, and much more.

Typically, the Arithmetic Logic Unit comprises storage locations for input

operands, operands being processed such as those being added, the accumulated

result which is stored in an accumulator, and shifted results. The flow of bits and the

operations applied to them within the ALU's subunits are managed by gated circuits.

The ALU frequently interacts with registers (e.g., the accumulator) to receive

input data, perform computations, and store the resulting data. Registers temporarily

hold data as the ALU processes it. The operation of the ALU is managed by control

signals that specify which operation, either arithmetic or logical, it should perform,

based on the instructions provided by the processor.

As part of a sequential circuit, the ALU relies on a clock signal to synchronize

its operations and manage the flow of data through registers and flip-flops. Its output

can depend on prior states, which are stored in the system’s registers. The ALU also

generates flag bits, such as carry, zero, sign, or overflow flags. These flags can be

used for branching or further decision-making within the processor.

ALU Flags

Exporting multiple status codes from the ALU is essential for several

purposes, including error detection and facilitating decision-making within the

system.

1. Comparisons

Comparisons between two values are generally carried out by subtracting one

from the other. The relationship between the values can then be determined

by analyzing the resulting difference. Some conditions are stated like this: If

the first is larger than the second, the result will be positive; If the second is

larger than the first, the result will be negative; If the two are equal, the result

will be zero.

2. Zero Flag

In order to assess the equality of two values, the ALU must verify whether the

result is zero. This can be accomplished by passing each bit of the result

through a NOR gate. Notably, utilizing a single multi-port NOR gate offers a

hardware advantage over employing an array of equivalent 2-port NOR gates,

as it reduces the overall hardware complexity.

3. Overflow Flag

It is important to detect when the result of an addition or multiplication

exceeds the maximum allowable result size. Similarly, it is crucial to identify

when the result of a subtraction or division is smaller than the minimum

possible value, indicating an underflow. This can be addressed either by using

two distinct flags for these conditions or by employing a single flag that is

interpreted differently based on the specific input operation.

4. Carry/Borrow Flag

This flag signals when an operation produces a result that exceeds the range

the accumulator can represent carry/overflow or falls below the representable

range borrow/underflow. It can be utilized by software to perform

arbitrary-width arithmetic, such as in the implementation of a "bignum" library.

5. Sign Flag

A status flag that indicates the sign of the result of an arithmetic operation. It

reflects whether the result is positive or negative by examining the most

significant bit or MSB of the result. If the result is negative, the MSB will be set

to 1, causing the sign flag to be set. Conversely, if the result is positive, the

MSB will be 0, and the sign flag will be cleared. This flag plays a crucial role in

decision-making processes within a processor, particularly in branching

operations.

6. Latch ALU Flag

Certain instruction sets require the CPU designer to store the ALU flags in a

dedicated "status register" and ensure that these flags can be preserved

during an interrupt routine. These sets rely on the status of the flags from

previous ALU operations. In contrast, other instruction sets do not reference

prior ALU flags; instead, they use the results of the ALU calculations within

the same instruction in which the calculations are performed. This distinction

dictates how the CPU handles and stores flag values, with some sets

necessitating more careful management of the flags to ensure correct

functionality during interrupts. Therefore, understanding and managing ALU

flags is vital for the design of efficient and accurate computational systems.
Control Signals

The functionality of the Arithmetic Logic Unit is regulated by control signals

that define the specific operation to be carried out. Typically, the ALU necessitates at

least three control lines, each corresponding to a bit, which collectively allow the

execution of up to eight distinct operations. ALU also uses appropriate gates to

calculate results based on the control lines while having two 4-bits inputs.

Table 6. ALU corresponding Operations

Code Operation

000 AND

001 OR

010 X-OR

011 NOT/INVERT

100 ADD

101 SUBTRACT

110 SHIFT LEFT

111 SHIFT RIGHT

Sequential Circuit Design Procedure

The design of sequential circuits follows a systematic approach to guarantee

functionality and proper integration within a digital system. The initial phase requires

a clear definition of the problem, specifying the desired circuit behavior, including the

relationship between inputs and outputs, as well as timing and sequence

requirements. This step is followed by the development of a state diagram, which

visually depicts the circuit's states and transitions based on input conditions, serving

as a guide for the sequential operation of the circuit over time. The state diagram is
then converted into a state table that comprehensively lists the current states, inputs,

next states, and outputs, acting as a foundational blueprint for the circuit's design.

Subsequently, binary codes are assigned to the states in a process known as

state assignment, facilitating their mapping to flip-flops or memory components. The

selection of flip-flops—such as D, T, JK, or SR—plays a critical role in how state

transitions are managed. An excitation table is then constructed for the chosen

flip-flops, outlining the required inputs to transition between states as defined in the

state table.

The next step involves deriving and simplifying Boolean expressions for the

inputs of the flip-flops and any outputs to reduce circuit complexity. These simplified

expressions are utilized to design the logic circuit by integrating the appropriate logic

gates and flip-flops to achieve the physical implementation. Verification and testing

are conducted to ensure that the circuit performs according to the initial

specifications, with adjustments made as needed based on simulation or practical

test outcomes. Upon successful verification, the circuit is prepared for hardware

implementation or further optimized for specific applications. This structured design

approach ensures the sequential circuit meets its functional requirements, aligns with

design objectives, and integrates effectively into larger digital systems.

State Diagram

Figure 5.5.1 Clock Sequence (State Diagram Example)

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State Table

Table 5.4.1. Transition Table Logic

Present State Next State

0 1

1 3

3 4

4 5

5 7

7 0

In figure 5.4.1 shows a diagram of a sequence that is needed to be designed

in a sequential circuit. Table 5.4.1 on the other hand is a tabular figure of the

sequence above, since the language of sequential logic is in binary, the next process

in order to construct a counter is to set the values of the sequences which are

decimal into binary code.

Table 5.4.2. State Transition Table

Present State Next State

Q3 Q2 Q1 Q3(t+1) Q2(t+1) Q1(t+1)

0 0 0 0 0 1

0 0 1 0 1 1

0 1 1 1 0 0

1 0 0 1 0 1

1 0 1 1 1 1

1 1 1 0 0 0

After stating table 5.4.2, the binary coded transition table, using a type of flip

flop is essential. For this instance, T Flip Flop will be utilized as its condition is: If
value of Q changes either from 0 to 1 or from 1 to 0 then input for T flip-flop is 1 else

input value is 0. Using T Flip Flop Excitation Table.

Excitation Table

Table 5.4.3. T Flip Flop Excitation Table

Qt Qt+1 T

0 0 0

0 1 1

1 0 1

1 1 0

The next process upon completing T flip flop shown in table 5.4.3,

Constructing the input table for all T flip-flops using the excitation table of the T

flip-flop. Given that the T flip-flop operates in a toggle mode, the output Q3

represents the most significant bit, while Q1 represents the least significant bit.

Table 5.5.4. Input Table of Flip Flops (State Table)

T3 T2 T1

0 0 1

0 1 0

1 1 1

0 0 1

0 1 0

1 1 1

Table 5.5.4 presents the input table of flip flops for the sequence given.

Provided the plots of T3, T2, and T1, finding the value of T3, T2, T1 in terms of Q3,

Q2, Q1 using K-Map is possible.

 Figure 5.5.2. K-Map of T3, T2, & T1
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Once the karnaugh map of T3, T2 and T1 is computed, the values of

themselves are solved by examining the outputs of logic 1 inside the K-Map.

Therefore, the values required for the sequence are T3=Q2, T2=Q1, & T1=Q2+Q1’.

Finally, the values given from the solutions can be formulated to design a

combinational logic circuit that can be equivalent to a sequential circuit with the

specified sequence and clock. This is the complete process of designing counters by

a given sequence.

Before constructing the sequential logic circuit design, a recap is essential

mostly for the major factors to consider in the procedure.

1. The state diagram is constructed using all the states of the sequential circuit

in question. It builds up the relationship between various states and also

shows how inputs affect the states.

2. The state table is the same as the excitation table of a flip-flop, i.e. what

inputs need to be applied to get the required output. In other words this table

gives the inputs required to produce the specific outputs.

3. The excitation table is crucial for developing excitation equations, which are

then used to design the logic that drives the flip-flop inputs in the sequential

circuit. This ensures the circuit operates correctly according to the desired

state transitions and timing requirements.

Figure 5.5.3. Other Flip Flop Excitation Tables & State Diagrams
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 Finally, the counter design can be drawn into a logic circuit by obeying the

procedures of sequential circuit design.

Figure 5.5.4. Logic Circuit Diagram Equivalent

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Synchronous & Asynchronous Circuits Analysis and Design

When talking about digital electronics, an asynchronous circuit lies in the

operations that are not coordinated by a global clock signal. The circuit is based

rather on the changes of input signals which specifies the timing of its operations.

Synchronous circuit on the other hand is performed where the operation relies on a

central clock signal, having to have its controlled and coordinated manner. The clock

signal guarantees simultaneous and regular intervals even when the circuit's state is

changed, they are known as "clock cycles".

Synchronous Sequential Circuits

A Synchronous Sequential Circuit is a type of circuit in which all state

variables representing the internal state of the circuit change simultaneously in

response to an input clock signal, allowing the next state to be reached. This

synchronization with a common clock signal ensures that all internal state transitions
occur at the same time, enhancing reliability and reducing the likelihood of issues

such as race conditions.

Figure 5.6.1. 2-Bit Synchronous UP Counter

https://www.geeksforgeeks.org/difference-between-synchronous-and-asynchronous

Excitation Table for Synchronous Circuit

Generally, flip flops are a kind of synchronous circuit. Meaning, any type of flip

flop can be used for an excitation function in a synchronous sequential circuit. As an

example, the J-K Flip Flop excitation table will be used. As for J-K flip flop

excitations, If J=1 and K=0, set the flip-flop to 1, while if J=0 and K=1, reset the

flip-flop to 0, when J=1 and K=1, the flip-flop toggles and if J=0 and K=0, there's no

change .

Table 7. J-K Excitation Table

Present Next J(in) K(in)

0 0 0 0

0 1 1 x

1 0 x 1

1 1 0 0

Asynchronous Sequential Circuits

In an Asynchronous Sequential Circuit, state variables do not synchronize

with a universal clock signal and may not transition simultaneously to reach the next
stable internal state. Any change in input can lead to alterations in the internal state,

potentially causing issues such as race conditions and other related problems. This

kind of circuit is also known as self-timed or ripple-clock circuits.

Figure 5.6.2. 2-Bit Asynchronous UP Counter

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The asynchronous sequential circuit in terms of logic circuits may consist and

be illustrated such as the figure below.

Figure 5.6.3. Asynchronous Sequential Circuit with Feedback Loop Broken

https://web.stanford.edu/class/archive/ee/ee108a/ee108a.1082/reader/ch22to25.pdf

Depending on the asynchronous sequential circuit in figure 5.6.3 with

feedback loop broken, a flow table can be implemented according to the operations

and values given in the circuit.

Table 8. Asynchronous Sequential Circuit Flow Table

NEXT
STATE
00 01 11 10

0 0 1 1 0

1 1 1 0 0
 REFERENCES

Anon. (2024). High accuracy pid temperature controller – PID-967. Libratherm

Instruments.
https://libratherm.com/product/high-accuracy-pid-temperature-controller-pid-9
67/
Anon. (2024). Read only memory (ROM). GeeksforGeeks.
https://www.geeksforgeeks.org/read-only-memory-rom/?fbclid=IwZXh0bgNhZ
W0CMTEAAR0mgnfipLQNXwDOptejW_YESWPvSF2HqwDx6vQEqweBe5hH
B4sk0Qul6bM_aem_gbMnDGyHpKtpmgAq98tJJA
Jain, Sandeep. (2024). Difference between multiplexer and demultiplexer.
GeeksforGeeks.
https://www.geeksforgeeks.org/difference-between-multiplexer-and-demultiple
xer/
Jaiswal, S. (2017). Registers in digital electronics - javatpoint. www.javatpoint.com.
https://www.javatpoint.com/registers-in-digital-electronics
Agarwal, T. (2021). Multiplexer and demultiplexer : Types, differences & their
applications. ElProCus.
https://www.elprocus.com/what-is-multiplexer-and-demultiplexer-types-and-diff
erences/
Bolton, D. (2017). Wondering what ROM is or how it works? here’s The answer.
ThoughtCo. https://www.thoughtco.com/definition-of-rom-958317
Brush, K. (2019). Read-only memory (ROM). WhatIs.
https://www.techtarget.com/whatis/definition/read-only-memory-ROM?fbclid=I
wZXh0bgNhZW0CMTEAAR13-Ozql-4lbmXdXDbo6XV0vPXPdk7poMMTbu3h
eQGqiRChCMtudEYdrI0_aem_ufBKBHOWcCJSWaEbrG9XQQ
Hanna, K. T. (2021). What is an arithmetic-logic unit (ALU) and how does it work?.
WhatIs. https://www.techtarget.com/whatis/definition/arithmetic-logic-unit-ALU
Hassan, M. (2015). Sequential and combinational alu. Computer Architecture &
Organization.
https://pd.daffodilvarsity.edu.bd/bn_IN/course/material/1745/pdf_content
Lowne, A. (2024). Choosing an oscilloscope. Nuts and Volts Magazine.
https://www.nutsvolts.com/magazine/article/October2016_Choosing-Oscillosc
opes
McFarland, G. (2017). Microprocessor design/alu flags. Wikibooks, open books for
an open world.
https://en.wikibooks.org/wiki/Microprocessor_Design/ALU_Flags
Mohtashim, M. (2022). Programmable logic array (PLA). Tutorialspoint.
https://www.tutorialspoint.com/digital-electronics/programmable-logic-array.ht
m
Obias, R. (2024). 7 best retro gaming consoles for old-school video games.
Billboard.
https://www.billboard.com/culture/product-recommendations/retro-gaming-con
soles-where-to-buy-online-1235635744/
Pickett, K. (2024). Medical Electronics Devices. Marian, Inc.
https://marianinc.com/medical-electronics-devices/
Raveendran, B. (2024). Difference between multiplexer and demultiplexer. BYJUS.
https://byjus.com/gate/difference-between-multiplexer-and-demultiplexer/#:~:t
ext=Multiplexer%20refers%20to%20a%20type,directs%20it%20through%20m
ultiple%20outputs.&text=A%20Multiplexer%20performs%20conversion%20fro
m%20parallel%20to%20serial.
Standford, U. (2012). Asynchronous Sequential Circuits. Chapter 22.
https://web.stanford.edu/class/archive/ee/ee108a/ee108a.1082/reader/ch22to
25.pdf
Storr, W. (2024). Digital comparator and magnitude comparator tutorial. Basic
Electronics Tutorials.
https://www.electronics-tutorials.ws/combination/comb_8.html
Tung, T. H., Hsu, T., Hsieh, W., & Liao, M. T. (2020). RT-AX82U brings you all the
benefits of WIFI 6 (802.11ax), and works perfectly with all your existing WIFI
devices!. ASUS USA.
https://www.asus.com/us/networking-iot-servers/wifi-routers/asus-gaming-rout
ers/rt-ax82u/
Zhakupov, V. (2018). Cell Phone Components Pictures, images and stock photos.
iStock. https://www.istockphoto.com/photos/cell-phone-components