Rajgad Dnyanpeeth Technical Campus Polytechnic, Dhangawadi

Tal. Bhor, Dist. Pune – 412206 (M.S) India

A MICRO PROJECT REPORT

On
“Build a 4 bit parity generator and parity checker circuit ’’

Is Submitted by -
Miss. Gaikwad Pranjal Nilesh
Miss. Jadhav Shweta Pradip
Mr. Kochale Himesh Santosh
Mr. Shrike Aayush Ganapat
Under the guidance of

Prof. Malusare K.B

Subject: - Digital Techniques

In partial fulfilment of

Diploma in S.Y Computer Engineering

(Academic Year 2024-2025)
Maharashtra State Board of Technical Education, Mumbai
 Certificate

This is to certify that following students

Miss. Gaikwad Pranjal Nilesh

Miss. Jadhav Shweta Pradip
Mr. Kochale Himesh Santosh
Mr. Shirke Aayush Ganapat

Has successfully submitted their micro project report on “Build a 4 bit parity
generator and parity checker circuit’’during the academic year 2024-2025 in
the partial fulfilment towards the completion of micro project in S.Y. Computer
Engineering under MSBTE MUMBAI

Project Guide Head of Department

Prof. Malusare K.B Prof. Khutwad S. S

 ACKNOWLEDGEMENT

I am personally indebted to a number of people who gave me their useful insights to

aid in my overall progress for this project. A complete acknowledgement would therefore be
encyclopedic. First of all, I would like to give my deepest gratitude to my parents for
permitting me to take up this course.

My heartfelt sense of gratitude goes to our respected Principal Prof. Khopade D. K.

for all his efforts and administration in educating us in his premiere institution. I take this
opportunity to also thank our Head of the Department, Prof. Khutwad S.S. for her
encouragement throughout the seminar. I would like to express my sincere thanks and
gratitude to my guide Prof. Malusare K.B for her commendable support and
encouragement for the completion of Project with perfection. I also convey my sincere thanks
to Prof. Khutwad S.S for her invaluable suggestions and for his technical support rendered
during the course of my project.

I would like to thank all faculty members and staff of the Department of Computer
Engineering for their generous help in various ways for the guidance of this project.

STUDENT NAME ENROLLMENT NO SIGN

1.Gaikwad Pranjal Nilesh 23213160127

2.Jadhav Shweta Pradip 23213160128

3.Kochale Himesh Santosh 23213160130

4.Shirke Aayush Ganapat 23213160120

 ABSTRACT

This microproject focuses on the design and implementation of a Parity Generator and Parity
Checker, crucial components in error detection mechanisms. The parity method, widely used in
digital communication systems, ensures the accuracy of transmitted data by adding an extra bit,
known as the parity bit, to a given data stream. The Parity Generator creates this parity bit based
on the data’s binary values, while the Parity Checker verifies it on the receiver’s end to detect
single-bit errors during transmission.

This project implements both even and odd parity schemes, demonstrating how parity helps
maintain data integrity. The parity generator forms an n-bit code with an appended parity bit,
and the parity checker ensures the correctness of the received code by checking the generated
parity against the transmitted data. The project involves hardware simulation using logic gates,
showcasing the effectiveness of parity in error detection in real-time communication systems.

The design of the 4-bit parity generator and checker was implemented using fundamental logic
gates, demonstrating the efficiency and effectiveness of the parity method in real-time digital
communication. The project includes simulations and hardware descriptions to illustrate the
functionality of the system. Applications of parity error detection span a wide range of digital
systems, from computer memory and storage devices to network data transmission protocols.

This microproject underscores the importance of parity as an elementary but powerful error-
detection technique in modern computing and communication systems. Although limited in its
error-detection capabilities, the simplicity of the 4-bit parity generator and checker makes it a
valuable learning tool for understanding the basics of error detection in digital systems.
 INTRODUCTION

Welcome to our microproject of building a 4 bit parity generator and parity checker circuit,
where we embark on a journey to unravel the operations and implementation of 4 bit parity
generator and checker. In this micro project, we aim to guide you to test data converters and
PLDs in digital electronic system.

In digital communication systems, ensuring data integrity during transmission is crucial due to
the possibility of errors introduced by noise or signal interference. One of the simplest and most
widely used techniques for error detection is the use of parity. Parity is a method where an
additional bit, called the parity bit, is added to a set of binary data to make the total number of 1s
either even or odd. This extra bit helps in identifying any single-bit errors that may occur during
the transmission process.

A Parity Generator is responsible for generating the parity bit based on the data to be
transmitted. Depending on whether even parity or odd parity is being used, the generator ensures
that the total number of 1s in the data stream (including the parity bit) is even or odd,
respectively. On the receiving end, a Parity Checker evaluates the received data, including the
parity bit, to determine whether the data has been corrupted. If the parity condition (even or odd)
is not satisfied, it indicates that an error has occurred during transmission.

This project aims to design and simulate both a parity generator and a parity checker, utilizing
logic gates to illustrate their functioning. By implementing this error detection mechanism, the
project highlights how parity can effectively detect single-bit errors, making it an essential tool
in ensuring the reliability of data communication systems. While parity detection is limited to
identifying single-bit errors and cannot correct them, it remains a fundamental and efficient
error-checking method in modern digital systems.
 APPLICATION OF 4 BIT PARITY GENERATOR AND CHECKER
CIRCUIT

In digital systems, like digital communication and storage systems, the parity generator and
checker are essential components that provide a robust method for error detection and correction
in transmitted and retrieved data streams. Thus, parity generator/checker helps to ensure data
integrity, reliability, and security of digital data.

The following examples illustrate the applications of parity generators and checkers in various
digital electronic applications −

 In digital communication systems, parity generators and checkers are used to ensure
integrity and accuracy of the transmitted and received data. Parity generators and
checkers help to detect errors in the data that can be caused due to noise and
interference during transmission over communication channels.

 Parity generators and checkers are used in storage systems like RAM and ROM to
detect errors in the data stored and retrieved.

 In digital networking, parity generators and checkers are used to improve reliability of
data transmission and verify the correctness of the transmitted data.

 Parity generators and checkers are used in industrial automation and control systems to
ensure accurate and reliable operation of industrial systems.

 Parity generators and checkers are also used in medical equipment used to diagnose and
monitor patient’s health and avoid any kind errors in medical reports and diagnosis data.
ADVANTAGES AND DISADVANTAGES OF PARITY GENERATOR AND
CHECKER

 Advantages :-

o Simplicity: Parity checks are easy to implement and don't require much
computational power.

o Low cost: Parity checks are inexpensive because they only require adding a small
bit to each data unit.

o Accuracy: Parity checks can be accurate.

o Improved security: Parity checks can improve security.

 Disadvantages :-

o May not catch errors: Parity checks may not detect errors if two data bits are
corrupted.

o Can't locate or correct errors: Once an error is detected, parity checks can't locate
or correct it.

o Can only detect odd number of errors: Parity checks can only detect an odd
number of bit errors
 What is a Parity Bit?
In digital signal processing, an additional bit either 0 or 1 is added to the original binary or
digital code to detect and correct any kind of errors in the data that can occur during
transmission. This additional bit is called a parity bit.
The addition of a parity bit to the original digital code makes the total number of 1s in the code
either even or odd. Thus, on the basis of number 1s in the data, the parity can be classified into
two types namely, even parity and odd parity.

If we add a 0 or a 1 to the original binary code and this makes the total number of 1s in the code
an even number, then it is called an even parity.

On the other hand, if we add a parity bit i.e., 0 or 1 to the original binary code and this makes the
total number of 1s in the code an odd number, then it is called an odd parity.

The parity bit is one of the simplest forms of error-detection technique used in digital
electronics.

How Does the Parity Bit Work?

Let us now consider an example to understand how the parity bit works.

Suppose we have a decimal number say 5 and its BCD code is 0101. This code has total number
of 1s are even, as it has two 1s.

In the case of even parity, we add a parity bit 0 to the original code to make the number of 1s an
even number in the code.

Therefore, after adding even parity, we get 01010. Here, a 0 (parity bit) is added to the end of the
original code.

In case, when we need to perform odd parity, then we add a 1 to end of the original code, we get
01011. Now, the total number of 1s in the code, including parity bit, is odd i.e., three 1s. This
ensures that it is odd parity scheme.
The following table shows the odd and even parity bits for decimal digits from 0 to 9 –
 What is a Parity Generator?
A combinational logic circuit that can generate the parity bit according to the original digital
code is known as a parity bit generator or parity generator.

The parity generator is used at the transmitter end and generate and add a parity bit the original
code before transmission.

First, a parity generator reads the input data and calculates the parity bit accordingly. Once the
parity bit is generated, it is added to the original data code. This gives an output code which is
the original code with a newly generated parity bit.

Types of Parity Generators

Depending on the parity system used, there are two main types of parity generators −

 Even Parity Generator

 Odd Parity Generator

Even Parity Generator
An even parity generator is a type of parity generator in which the parity bit, either a 0 or a 1 is
added to the original data so that the final digital code contains an even number of 1s, including
the parity bit.

Therefore, we can state that total number of 1s in the output of an even parity generator
including the parity bit is even.

In the case of an even parity generator −

 If a digital code contains an odd number of 1s, then the even parity generator will
generate a 1 as parity bit to maintain the even parity.

 If a digital code already contains an even number of 1s, then the even parity generator
will generate a 0 as the parity bit to maintain the even parity.

For example, consider a digital code 0110. This code already contains the even number of 1s.
Hence, if it is input to an even parity generator, the output of the parity generator will be 01100.
Where, the LSB 0 is a parity bit added by the even parity generator.

Similarly, consider another digital code 0111. In this case, the total number of 1s in the code is
three (odd). If we input this code to an even parity generator, the generator’s output will be
01111, containing even number of 1s. Where, the LSB 1 is the parity bit.
Let us now design a 4-bit even parity generator. The following is the truth table of the 4-bit even
parity generator −

The Boolean expression of the 4-bit even parity generator can be obtained
by simplifying its truth table, which is given below.

P=A⊕B⊕C⊕DP=A⊕B⊕C⊕D
The logic circuit diagram of a 4-bit even parity generator is shown in the
following figure.

In this circuit, three XOR gates are connected together to add four data
bits of the input code. The sum bit produced at the output will be the
parity bit.

This is all about the even parity generator and its functioning.
Odd Parity Generator
A type of parity generator that adds a parity bit to a binary code so that the total number of 1s in
the output code is an odd number, it is called an odd parity generator.

The output of an odd parity generator is a digital code that contains an odd number of 1s,
including the parity bit.

In the case of an odd parity generator,

 If the original data contains an even number of 1s, then the odd parity generator adds a 1
as parity bit to the original code to maintain the odd parity.

 If the original data already contains an odd number of 1s, then the odd parity generator
adds a 0 as parity bit to the original code to maintain the odd parity.

Let us understand the function of the odd parity generator with the help of examples.

Consider a 4-bit digital code that is 0110. This code has even number of 1s (two). Therefore, if
we input this code to an odd parity generator, the generator will add a 1 and produces a code
01101 as output. This resulting code has odd number of 1s, including the parity bit, and ensuring
the odd parity system.

Similarly, consider another 4-bit code that is 0111. This code already contains odd number of 1s
i.e., three 1s. Therefore, the odd parity generator will add a 0 as parity bit to it and gives an
output code as 01110 to ensure the odd parity system.
 The following is the truth table of a 4-bit odd parity generator –

The Boolean expression of the 4-bit odd parity generator is,

P=A⊕B⊕C⊕D¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
The following figure depicts the logic circuit diagram of the 4-bit odd parity generator.

In this circuit, three XOR gates are connected together to add the four bits of the input data and
the sum bit is then complemented to obtain the odd parity bit.

This is all about the even parity generator and odd parity generator. Both of these types of parity
generators are used in digital systems to implement different types of parity systems depending
on the needs of the applications.

Parity generators are extensively used in digital communication and storage systems to check
errors that can occur during transmission of data.
What is a Parity Checker?
A combinational circuit that checks and verifies the correctness of the transmitted data by
analyzing the parity bit is called a parity checker. The main function of a parity checker is to
detect errors that can occur during data transmission.

Parity checkers are used at the receiver end of the communication channel. It receives the
transmitted data from the communication channel. This data includes the original message code
and the parity bit.

After that, the parity checker counts the number of 1s in the data code and compares this number
with the expected code to determine whether there is any error or not. If there is any error in the
received data, the parity checker takes an appropriate action like request to retransmit the data.

The parity checker is an essential component in the digital communication systems to ensure the
correctness and integrity of data. It also provides a simple and effective method for error
detection.

Types of Parity Checkers

Depending on the parity system used, there are two main types of parity checkers −

 Even Parity Checker

 Odd Parity Checker
Even Parity Checker
The type of parity checker that verifies whether the received data is correct as per the even parity
system is called an even parity checker.

The even parity checker counts and verifies that the received data contains an even number of
1s, including the parity bit.

Thus, in the case of an even parity checker,

 If the number of 1s in the received data is even, then it is considered that the data is error
free.

 If the number of 1s in the received data is odd, then the parity checker shows that the
data contains some error.

How Does an Even Parity Checker Work?

Let us understand the even parity checking with the help of an example.

Consider a 4-bit digital code 00110 (having 0 as parity bit at LSB position), this code is received
by the even parity checker. The parity checker will count the number of 1s in the code which is
even (two). Thus, the parity checker shows that it is an error free code, where LSB 0 is the parity
bit.

Similarly, consider another 4-bit message code 01011 with a parity bit at the LSB place. This
code contains odd number of 1s (three 1s). Hence, the even parity checker will show that the
code has some error.
Let us now implement a 4-bit even parity checker whose truth table is shown below –
Here, the bits ABCD represents the original digital code and P is the parity bit.

In this truth table, if CP = 1, there will be an error in the received code. If C P = 0, there is no error
in the received code.

The Boolean expression of the 4-bit even parity checker is,

CP=A⊕B⊕C⊕D⊕PCP=A⊕B⊕C⊕D⊕P
The logic circuit diagram of the 4-bit even parity checker is shown in the following figure.
Odd Parity Checker

An odd parity checker is a combinational logic circuit that checks and verifies whether the
received data is correct as per the odd parity system.

An odd parity checker counts and confirms that the received data contains odd number of 1s
including the parity bit.

In the case of an odd parity checker,

 If the number of 1s in the received code is odd, there is no error in the code.
 If the number of 1s in the received code is even, this represents an error in the code that
might be occurred during transmission.

For example, consider a 4-bit data code 01101 (LSB 1 is the parity bit). In this code, the number
of 1s are odd (three). Thus, the odd parity checker will show that the code is error free.

Similarly, consider another 4-bit data code 01100 (LSB 0 is the parity bit). This code contains
the even number of 1s i.e., only two 1s are there. In this case, the odd parity checker will show
that the code has an error.
Let us now implement a 4-bit odd parity checker whose truth table is shown below.
In this truth table, the bits ABCD represents the original binary code and P is the parity bit.

From this truth table, we can observe that if C P = 1, the code contains an even number of 1s and
hence, there is an error occurred in the code during transmission.
If CP = 0, the code contains odd number of 1s which represents that the code is error free.

The Boolean expression of the 4-bit odd parity checker is given here,

⊕D⊕P¯
CP=A⊕B⊕C⊕D⊕P¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯CP=A⊕B⊕C
The logic circuit diagram of this 4-bit odd parity checker is depicted in the following figure.
 CONCLUSION
In this microproject, we successfully designed, implemented, and tested a 4-bit Parity Generator
and Parity Checker, which demonstrated the effectiveness of parity as a simple yet powerful
error detection mechanism in digital systems. The project involved constructing logic circuits
capable of generating a parity bit and subsequently verifying the integrity of data transmitted
over a communication channel.

The primary objective of this project was to highlight how parity can be utilized to detect single-
bit errors in a data stream. By applying either even parity or odd parity, we ensured that any
errors occurring during transmission could be identified at the receiver’s end. The parity
generator produced an additional bit based on the input data, and the checker compared the
received data, including the parity bit, to detect any discrepancies caused by errors.

Our design centered around a 4-bit data word, which is a common data size in basic error
detection implementations. Through this design, we successfully demonstrated that the parity
method can detect errors with minimal hardware overhead. The simplicity of the logic gates used
in both the generator and checker circuits further highlights the efficiency of this method,
making it particularly useful for systems where hardware resources are limited and the detection
of single-bit errors is sufficient.

While the parity mechanism is effective in detecting single-bit errors, one of its limitations is its
inability to detect multiple-bit errors or correct any errors. Parity is primarily used for systems
where error detection is critical, but error correction is not required or can be handled by other
means. For instance, in modern digital communication systems, more advanced techniques like
Hamming code or Cyclic Redundancy Check (CRC) are often employed for error correction.

This project has provided valuable insights into how basic error detection works and its
importance in ensuring reliable data communication. By focusing on the design of a 4-bit parity
generator and checker, we gained hands-on experience in working with combinational logic
circuits, which form the basis of many digital systems. Furthermore, the practical
implementation and testing of this system reinforced our understanding of the fundamental
principles of data integrity and error detection.

In conclusion, the parity-based error detection method, though simple, remains a key component
in many digital communication protocols. Its implementation in this project has demonstrated its
utility for real-time error detection with minimal computational complexity. The project could be
further expanded by exploring more complex error detection and correction techniques or by
applying parity concepts to larger data sizes to understand the scalability and limitations of this
approach in more advanced communication systems.
 REFERENCES

Certainly! Here are some reference links that you can explore for your micro project on Building
a 4 bit parity generator and checker circuit.These links cover theoretical explanations, design
steps, and practical simulations using different tools like logic circuits, Verilog, or
VHDL.General:-

Concepts on Parity Generators and Checkers:

 Parity Bit in Error Detection – GeeksforGeeks https://www.geeksforgeeks.org/error-
detection-codes-parity-bit-method/
 Parity Generator and Checker – All About Circuit
https://www.allaboutcircuits.com/industry-articles/implementing-binary-parity-
generator-and-checker-greenpak/
 Error Detection using Parity – TutorialsPoint https://www.tutorialspoint.com/digital-
electronics/parity-bit-generator-and-checker.htm
Designing a 4-bit Parity Generator and Checker:
 4-bit Parity Generator and Checker using Logic Gates – ElectronicsHub
https://www.electronicshub.org/parity-generator-and-parity-check/
 How to Design a Parity Generator and Checker – ElectronicsPost
https://www.electrical4u.com/parity-generator/
 Design of Parity Generator and Checker Circuit – VLSIFacts
https://www.vlsifacts.com/state-machine-diagram-parity-generator/

Verilog/VHDL Implementation:
 4-bit Even Parity Generator and Checker using Verilog – Hardware Model
 VHDL Code for Parity Generator – VHDL-Whiz
 4-bit Parity Generator in Verilog – ChipVerify

Simulation Tools and Examples:

 Parity Generator and Checker Simulation using Logisim – CircuitVerse
 Parity Generator in Proteus – Proteus Simulation of Parity Circuit

Research Papers and Thesis:

 Parity Generator and Checker – IEEE Research Papers – IEEE Xplore
 Implementation of Parity Generators – ResearchGate
 Error Detection Codes: A Review of Parity Checkers – Springer

LinkVideos and Tutorials:

 Parity Generator and Checker – Digital Logic Design – YouTube
 Even Parity Generator using Logic Gates – YouTube