EXPERIMENT No.
11
AIM: To Analyse and Implement Synchronous BCD Decade counter using J-K flip flop:
a. Mod – Up Counter
b. Mod – Down Counter
APPARATUS: Digital trainer kits, logic gate & flip flop IC’s, connecting wires.
THEORY: Synchronous binary counters can be able to count either in increasing or decreasing
order. In a count-up mode, the counter value sequentially increased and in a count down mode
the counter value sequentially decreased.
a. Mod-Up Counter: As the input clock pulses are applied to all the Flip-flops in a
synchronous counter, some means must be used to control when an FF is to toggle and when it
is to remain unaffected by a clock pulse. This is accomplished by using the J and K inputs for
a 4-bit, MOD-16 synchronous counter.
Table 7.1: Truth Table of Mod-16 counter
For a 4-bit (MOD-16) synchronous counter circuit, to count properly on a given NGT (negative
transition) of the clock, only those FFs that are supposed to toggle on that NGT should have J
= K = 1. Each FF should have its J and K inputs connected so that they are HIGH only when
the outputs of all lower-order FFs are in the HIGH state.
Fig 7.1: Circuit diagram of Mod-16 up counter
b. Mod-Down Counter: As the input clock pulses are applied to all the Flip-flops in a
synchronous counter, some means must be used to control when an FF is to toggle and when it
is to remain unaffected by a clock pulse. This is accomplished by using the J and K inputs for
MOD-8 synchronous counter.
Fig 7.2: Circuit diagram of Mod-8 down counter
Table 7.2: Truth Table of Mod-8 counter
Count C B A
7 1 1 1
6 1 1 0
5 1 0 1
4 1 0 0
3 0 1 1
2 0 1 0
1 0 0 1
0 0 0 0
PROCEDURE:
1. Take the IC’s mentioned in apparatus required.
2. Place them properly on their respective places.
3. Make the connections as per the circuit diagram.
4. The circuit can be verified using various values of inputs and then testing the values
of output as per truth table.
PRECAUTIONS:
1. Circuit should be properly connected.
2. Do not short circuit in the trainer kit during operation.
3. Wires should be held by their heads while being removed else they may get damage.
RESULT:
We have analyzed and implemented the mod up and mod down Decade counter using JK
Flip Flop.
EXPERIMENT No. 10
AIM: To Analyze and Implement SISO, SIPO, PISO and PIPO Shift Registers using JK flip
flop and logic gates.
APPARATUS: Digital trainer kits, logic gate & flip flop IC’s, connecting wires.
THEORY:
SISO Register: The shift register, which allows serial input (one bit after the other through
a single data line) and produces a serial output is known as Serial-In Serial-Out shift register.
Since there is only one output, the data leaves the shift register one bit at a time in a serial
pattern, thus the name Serial-In Serial-Out Shift Register. The main use of a SISO is to act
as a delay element.
Fig 6.1: Circuit Diagram of SISO Register
Fig 6.2: Data Shift in SISO Register
SIPO Register: The shift register, which allows serial input (one bit after the other through
a single data line) and produces a parallel output is known as Serial-In Parallel-Out shift
register. The logic circuit given below shows a serial-in-parallel-out shift register. The circuit
consists of four D flip-flops which are connected. The clear (CLR) signal is connected in
addition to the clock signal to all the 4 flip flops in order to RESET them. The output of the
first flip flop is connected to the input of the next flip flop and so on. All these flip-flops are
synchronous with each other since the same clock signal is applied to each flip flop.
They are used in communication lines where demultiplexing of a data line into several
parallel lines is required because the main use of the SIPO register is to convert serial data
into parallel data.
Fig 6.3: Circuit Diagram of SIPO Register
PISO Register: The shift register, which allows parallel input (data is given separately to
each flip flop and in a simultaneous manner) and produces a serial output is known as
Parallel-In Serial-Out shift register. A Parallel in Serial out (PISO) shift register us used to
convert parallel data to serial data.
Fig 6.4: Circuit Diagram of PISO Register
PIPO Register: The shift register, which allows parallel input (data is given separately to
each flip flop and in a simultaneous manner) and also produces a parallel output is known as
Parallel-In Parallel-Out shift register. A Parallel in Parallel out (PIPO) shift register is used
as a temporary storage device and like SISO Shift register it acts as a delay element.
Fig 6.5: Circuit Diagram of PIPO Register
PROCEDURE:
1. Take the IC’s mentioned in apparatus required.
2. Place them properly on their respective places.
3. Make the connections as per the circuit diagram.
4. The circuit can be verified using various values of inputs and then testing the
valuesof output as per truth table.
PRECAUTIONS:
1. Circuit should be properly connected.
2. Do not short circuit in the trainer kit during operation.
3. Wires should be held by their heads while being removed else they may get damage.
RESULTS:
We have analyzed and implemented the SISO, PIPO, SIPO and PISO registers using the
JK flip flop
EXPERIMENT No. 12
AIM: To Analyze and Implement a simple Three-bit ripple counter.
APPARATUS: Digital trainer kits, logic gate & flip flop IC’s, connecting wires.
THEORY: Ripple counter is a cascaded arrangement of flip-flops where the output of one flip-flop
drives the clock input of the following flip-flop. A 3-bit Ripple counter using a JK flip-flop is as follows:
Fig 12.1: Circuit diagram of 3-bit Ripple counter
In the circuit shown in the above figure, Q0(LSB) will toggle for every clock pulse because JK flip-flop
works in toggle mode when both J and K are applied 1, 1, or high input. The followingcounter will toggle
when the previous one changes from 1 to 0.
Table 12.1: Truth Table of 3-bit Ripple Counter
PROCEDURE:
1. Take the IC’s mentioned in apparatus required.
2. Place them properly on their respective places.
3. Make the connections as per the circuit diagram.
4. The circuit can be verified using various values of inputs and then testing the valuesof output
as per truth table.
PRECAUTIONS:
1. Circuit should be properly connected.
2. Do not short circuit in the trainer kit during operation.
3. Wires should be held by their heads while being removed else they may get damage.
RESULT:
We have studied, analyzed and implemented a simple Three-bit ripple counter.
EXPERIMENT No. 13
AIM: To Analyze and Implement BCD to Seven Segment Display driver circuit using IC7447.
APPARATUS: Logic Trainer kit, IC 7447/4511, 7 segment display (Common cathode), Connecting
leads.
THEORY: A BCD to 7-segment decoder/driver is used as a 4-bit BCD input and provide theoutputs
that will pass current through the appropriate segment to display the decimal digit. Fordisplay numerical
digit, a 7-segment configuration is used to form the decimal character 0 to 9 and sometimes the hex
character A through F. One common arrangement uses light emitting diode (LED’S) for each segment,
by controlling the current through each LED. Some segmentwill pass light through and other will dark
so that the desired character pattern will be generated.
Fig 13.1: Circuit diagram of BCD to seven segment display
Table 13.1: Truth Table of BCD to seven segment display
Pin Description:
Fig 13.2: Pin description of seven segment display IC
PROCEDURE:
1. Make the connection as shown in the figure.
2. Switch on the power supply,
3. Verify the Truth Table for BCD to seven segment display
4. If the LED glow, output is at logic”1” otherwise at logic “0”.
PRECAUTIONS:
1. Circuit should be properly connected.
2. Do not short circuit in the trainer kit during operation.
3. Wires should be held by their heads while being removed else they may get damage.
RESULT:
We have studied, analyzed and implemented BCD to Seven Segment Display driver circuit using IC
7447.
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