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IEC-05 Assignment2

iec 5 assign 2

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69 views2 pages

IEC-05 Assignment2

iec 5 assign 2

Uploaded by

Ishaan jain
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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IEC – 05: Semiconductor devices and VLSI

Assignment 2 Deadline: 11 October, 5pm Marks: 20

1. Consider an ideal MOS capacitor fabricated on a P-type silicon with a doping of


NA = 5 × 1016cm–3 with an oxide thickness of 2 nm and an N+ poly-gate.
(a) What is the flat-band voltage, Vfb, of this capacitor?
(b) If the gate is changed to P+ poly, what would the flat-band voltage? (2)

2. Consider the C–V curve of an MOS capacitor in below figure (the solid line). The capacitor
area is 6,400 μm2. Cox = 45 pF and C1 = 5.6 pF.

If, due to the oxide fixed charge, the C–V curve is shifted from the solid line to the dashed line with ΔV
= 0.05 V, what is the charge polarity and the area density (C/cm2) of the oxide fixed charge? (2)

3. The oxide thickness (Tox) and the doping concentration (Na or Nd) of the silicon substrate can be
determined using the high-frequency C–V data shown in figure below for an MOS structure.
(a) Identify the regions of accumulation, depletion, and inversion in the substrate corresponding to this C–V
curve. What is the doping type of the semiconductor? (2)
(b) If the maximum capacitance of the structure C0 (which is equal to Cox × Area) is 82 pF and the gate area
is 4.75 × 10–3 cm2, what is the value of Tox? (1)
(c) Determine the concentration in the silicon substrate. Assume a uniform doping concentration. (2)

4. Ids – Vds curve of an ideal MOSFET is shown in figure below. Note that Idsat = 10-3A and Vdsat = 2 V for
the given characteristic. (You may or may not need the following information: L = 0.5 μm, W = 2.5 μm,
Tox = 10 nm. )

(a) Given a Vt of 0.5 V, what is the gate voltage Vgs one must apply to obtain the I–V curve? (2)
(b) What is the inversion-layer charge per unit area at the drain end of the channel when the MOSFET is
biased at point (1) on the curve? (1)
(c) Suppose the gate voltage is changed such that Vgs – Vt = 3 V. For the new condition, determine Ids at Vds
= 4 V. (2)
(d) If Vd = Vs = Vb = 0 V, sketch the general shape of the gate capacitance Cgg vs. Vg to be expected from the
MOSFET, when measured at 1 MHz. Do not calculate any capacitance but do label the Vg = Vt point in
the C–V curve. (2)

5. Derive an expression for the potential along the channel of a MOSFET, Vc(x), in the linear strong-
inversion region of operation. [Note x=0 is source and x=L is the drain end of the channel]
HINT: Use the expression for current at a point (x) in the channel as the starting point. (4)

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