Design different types of Flip Flop

S-R flip flop

The S-R (also called R-S) Flip Flop is considered as one of the most basic sequential logic
circuits. The Flip Flop is a one-bit memory bi-stable device. It has two inputs, one is called
“SET” which will set the device (output = 1) and is labelled S and another is known as “RESET”
which will reset the device (output = 0) labelled as R. The SR stands for SET/RESET.
Block diagram of S-R flip flop

Truth table of S-R flip flop

S R Q Q’ Action
0 1
0 0 No Change
1 0
0 1 0 1 Reset
1 0 1 0 Set
1 1 0/1 0/1 Forbidden State

Logic circuit design of S-R flip flop

When R=0, S=0

When R=0, S=1 When R=1, S=0

When R=1, S=1

Discussion
i. When R is 0, S is 0 and previous Q is 0 then Q is 0 and Q’ is 1.
ii. When R is 0, S is 0 and previous Q is 1 then Q is 1 and Q’ is 0.
iii. When R is 0, S is 1 and previous Q is 0/1 then Q is 1 and Q’ is 0.
iv. When R is 1, S is 0 and previous Q is 0/1 then Q is 0 and Q’ is 1.
v. When R is 1, S is 1 and previous Q is 0 then Q is 0 and Q’ is 1.
vi. When R is 1, S is 1 and previous Q is 1 then Q is 1 and Q’ is 0.

J-K flip flop

The JK Flip Flop is the most widely used flip flop. It is considered to be a universal flip-flop
circuit. The sequential operation of the JK Flip Flop is the same as for the RS flip-flop with the
same SET and RESET input. The difference is that the JK Flip Flop does not the invalid input
states of the RS Latch (when S and R are both 1). The JK Flip Flop name has been kept on the
inventor’s name of the circuit known as Jack Kilby.
Block diagram of J-K flip flop

Truth table of J-K flip flop

J K Q Q’ Action
0 1
0 0 No Change
1 0
0 1 0 1 Reset
1 0 1 0 Set
1 1 1 1 Toggle State
Logic circuit design of S-R flip flop
When J=0, K=0

When J=0, K=1 When J=1, K=0

When J=1, K=1

Discussion
i. When J is 0, K is 0 and previous Q is 0 then Q is 0 and Q’ is 1.
ii. When J is 0, K is 0 and previous Q is 1 then Q is 1 and Q’ is 0.
iii. When J is 0, K is 1 and previous Q is 0/1 then Q is 0 and Q’ is 1.
iv. When J is 1, K is 0 and previous Q is 0/1 then Q is 1 and Q’ is 0.
v. When J is 1, K is 1 and previous Q is 0/1 then Q is 0 and Q’ is 1.
vi. When J is 1, K is 1 and previous Q is 1/0 then Q is 1 and Q’ is 0.

D flip flop

D Flip-flops are used as a part of memory storage elements and data processors as well.
Whenever the clock signal is LOW, the input is never going to affect the output state. The
clock has to be high for the inputs to get active. Thus, D flip-flop is a controlled Bi-stable
latch where the clock signal is the control signal. Again, this gets divided into positive edge
triggered D flip flop and negative edge triggered D flip-flop.
Block diagram of D flip flop

Truth table of D flip flop

CLK D Q Q’ Action
0 1
0 0 No Change
1 0
1 0 0 1 Reset
1 1 1 0 Set

Logic circuit design of D flip flop

When CLK=0, D=0

When CLK=1, D=0 When CLK=1, D=1

Discussion
i. When CLK is 0, D is 0 and previous Q is 0 then Q is 0 and Q’ is 1.
ii. When CLK is 0, D is 0 and previous Q is 1 then Q is 1 and Q’ is 0.
iii. When CLK is 1, D is 0 and previous Q is 0/1 then Q is 0 and Q’ is 1.
iv. When CLK is 1, D is 1 and previous Q is 0/1 then Q is 1 and Q’ is 0.

T flip flop

The name T flip-flop is termed from the nature of toggling operation. The major applications
of T flip-flop are counters and control circuits. T flip flop is modified form of JK flip-flop making
it to operate in toggling region. Whenever the clock signal is LOW, the input is never going to
affect the output state. The clock has to be high for the inputs to get active. Thus, T flip-flop
is a controlled Bi-stable latch where the clock signal is the control signal.
Block diagram of T flip flop

Truth table of T flip flop

CLK T Q Q’ Action
0 1
0 0 No Change
1 0
0 1 Reset
1 1
1 0 Set

Logic circuit design of T flip flop

When CLK=0, T=0

When CLK=1, T=1

Discussion
i. When CLK is 0, T is 0 and previous Q is 0 then Q is 0 and Q’ is 1.
ii. When CLK is 0, T is 0 and previous Q is 1 then Q is 1 and Q’ is 0.
iii. When CLK is 1, T is 1 and previous Q is 0/1 then Q is 0 and Q’ is 1.
iv. When CLK is 1, T is 1 and previous Q is 0/1 then Q is 1 and Q’ is 0.