Clock Domain

Crossing
Part 7 – Timing Constraints

Amr Adel Mohammady

/amradelm

/amradelm
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Introduction
• In the previous parts we went through all the CDC solutions and schemes.
• In this part we will discuss the timing constraints associated with these schemes.
• We mentioned that CDC paths are asynchronous and therefore can’t be analyzed with static timing analysis. ‘
• That’s why, in the past, the most common approach was applying false paths on CDC paths. We will see how that may lead to major issues.
• It turns out we still need some timing constraints to enforce some assumptions we made when designing the CDC circuit

CDC Synchronizers CDC Handshake Protocol CDC FIFO

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1 (Trial) Solution :
st

Apply False Path

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What is a False Path?
• False paths are timing paths that can’t possibly occur due to the logic of the circuit
• Consider the example below:
o Both muxes have the same select signal. This means we have 2 possible timing paths. The one going through both red logics (200 + 300 = 500𝑝𝑠) and
the one going through both blue logics (100 + 500 = 600𝑝𝑠)
o The paths going through a red logic then a blue logic (200 + 500 = 700𝑝𝑠) or blue logic then red logic (100 + 300 = 400𝑝𝑠) is impossible to happen.
o Unless we instruct the tool to ignore these false paths, they will be considered for timing analysis leading to the large 𝑇𝑐𝑜𝑚𝑏 of the red to blue path which
will violate setup.

𝑝𝑜𝑠𝑠𝑖𝑏𝑙𝑒 𝑝𝑎𝑡ℎ𝑠

200𝑝𝑠 300𝑝𝑠
0 0

1 1
100𝑝𝑠 500𝑝𝑠

sel
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What Would Happen With A False Path Constraint?
• Applying false path will make the tool ignore the timing of the paths and therefore may create unnecessary delay that breaks our CDC circuit.
o The tool might:
▪ Place the launch and capture FF far apart.
▪ Create unnecessarily long routes.
▪ Add unnecessary buffers in the routes.
▪ Use slow cells/FFs to save power.
o We will see how this may break our CDC circuits. We will consider 2 examples
▪ CDC Mux
▪ CDC Gray Coding

Possible Schematic of a very relaxed Path

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CDC Mux Scheme And False Path
1 Let's review the CDC MUX scheme1: 2 • The data reaches the MUX quickly since no FF 3 • After some time, the enable arrives at the MUX
• The data goes directly to the Rx domain MUX exist in the way. and opens the gate for the data.
• The enable goes to the Rx domain through FF • The enable is still going through the FF syncs • Since the enable is synchronized, it's
synchronizers guaranteed with STA that the gate will open
without violating setup or hold time and
therefore the data won't cause metastability

D D D

EN

EN
EN

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[1] : You can watch an animation of this here : https://lnkd.in/en-iuNPx Free Palestine /amradelm 7
CDC Mux Scheme And False Path
1 Now let’s consider the faulty behavior with a 2 • The data takes a long time to reach the MUX 3 • After some time, the data arrives at the MUX
false path constraint applied1 due to the logic delay. after the enable.
• The data goes to the Rx domain MUX • The enable reaches the MUX and opens the • The data is a domain 1 signal arriving at
• The enable goes to the Rx domain through FF gate domain 2 FF. Metastability happens
synchronizers

D Metastability!

D D

EN EN

EN

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CDC Gray Coding And False Path
1 Now let’s see the faulty behavior with CDC Gray coding 2 • We then send gray code 101 (decimal 6)
• Initially the Rx sees gray code 110 (decimal 4) • Due to the long delay on the LSB line, the logic “1” from decimal 5 didn’t
• After that we send gray code 111 (decimal 5) reach the Rx yet.
• Now the Rx sees two bit changing and may jump to wrong count

1 1 1 1

5 4 6 4
1 1 0 1

1
1 0 1 0

Multiple bits are changing at the same time.

The Gray code is violated

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 2 nd(Trial) Solution :
Don’t Apply False Path

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What Could Happen Without a False Path Constraints?
• By default, the tool will assume the 2 CDC clocks are synchronous and will run STA on any path between them.
• This will lead to one of 2 issues:
o If the clock skew between the 2 clocks is small, the path will be very tight and won’t meet timing. The synthesis and PnR tools will spend a lot of effort trying
to fix the path1.
o If the clock skew between the 2 clocks is large, the path will be relaxed and may meet timing with a large setup margin.
▪ The tool might add delay (for example, to save power)
▪ We get the same issue of applying a false path constraint

𝑇𝑐𝑞 𝑇𝑐𝑞
𝑇𝑐𝑜𝑚𝑏 𝑇𝑐𝑜𝑚𝑏
𝑇𝑙𝑎𝑢𝑛𝑐ℎ_𝑒𝑑𝑔𝑒 𝑇𝑙𝑎𝑢𝑛𝑐ℎ_𝑒𝑑𝑔𝑒

𝑇𝑠𝑒𝑡𝑢𝑝 𝑇𝑠𝑒𝑡𝑢𝑝

𝑇𝑐𝑎𝑝𝑡𝑢𝑟𝑒_𝑒𝑑𝑔𝑒 𝑇𝑐𝑎𝑝𝑡𝑢𝑟𝑒_𝑒𝑑𝑔𝑒

Small Skew Case Large Skew Case

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[1] : The tools ignore less critical paths and focus on the critical ones. This will lead to real paths being masked by Free Palestine /amradelm 11
fake CDC violations
3 rd (Correct) Solution :
Skew Constraint

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What is A Skew Constraint

• Skew checks constraint the arrival difference between 2 signals or more.

• In the example below we have a data bus of 4 bits. The bits should arrive close to each other with a difference no more than 3ns. This means the difference
between the latest bit to arrive and the earliest bit to arrive shouldn’t exceed 3ns.
• To fix skew violations we need to speed up slow signals and/or slow down fast ones.

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CDC Gray Coding And Skew Constraint

Buffers are added by the tool on the other

paths to balance with the LSB route delay.

Without A Skew Constraint With A Skew Constraint

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The Issue With This Approach
• The main issue with this approach is that it needs lots of manual efforts
• If we have multiple CDC paths, we need to identify each group of signals and add skew constraints for them
• We will try another easier approach

Group 1 Group 2 Group 3

Group 4 Group 5 Group 6

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4 th (Best) Solution :
Max Delay Constraint

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Max and Min Delays

• Sometimes we want to control the arrival time of a signal.

• In the example below, it’s required that signal A arrives at the memory block no eariler than 10ns and no later than 30ns after the clock edge.
• To constraint signal A to follow this requirement we need to apply a min delay constraint of 10ns and a max delay of 30ns1.

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More details : https://docs.amd.com/r/2021.2-English/ug903-vivado-using-constraints/Min/Max-Delays

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[1] : Don’t apply the constraint from the Q pin of the FF but from the CK pin. Otherwise, the setup and hold timing paths of
the FF will be broken
Max Delay Constraint

• The best approach is to add a max delay constraint with an amount small enough that the CDC paths are not broken
• What makes this approach easy is that it can applied to all CDC paths with one line1 so it doesn’t need manual work:
• pt_shell> set_max_delay 4.0 -from CLK1 -to CLK2
• What remains now is what value to use for the max delay constraint.
≤ 𝟒 𝒏𝒔
o In some cases, we need to apply the Tx clock period
o In other cases, we need to apply the Rx clock period
o In other cases, we need to apply multiple clock periods.
≤ 𝟒 𝒏𝒔
o We will use the worst case (smallest) instead of applying a specific max delay
value for each
• The value used for max delay might be too tight for some CDC paths. In that case, ≤ 𝟒 𝒏𝒔
we can resort to skew constraint

[1] : In some tools, the max delay constraint overwrites the setup constraints, but in others, it won’t.
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Depending on your tool, you might need to first apply a false path on the setup constraint then apply the max
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delay constraint : Timing constraints for clock-domain crossings. #sta #cdc (github.com)
References
1) https://gist.github.com/brabect1/7695ead3d79be47576890bbcd61fe426
2) Y. Mirsky, O. Tsarfaty, D. Stein, & O. Winner, “Timing Analysis of Unconstrained Clock Domain Crossings – the Need and the Method,”
3) O. Dasa, Y. Mirsky “A New Approach to Easily Resolve the Hidden Timing Dangers of False Path Constraints on Clock Domain Crossings”

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Thank You!

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