ENC O U N T E R L I B R A RY

DATASHEET
CHA R A C T E R I Z E R

Power and process variation concerns are growing for digital IC

designers, who need advanced modeling formats to support their
cutting-edge low-power digital design flows. Cadence® Encounter®
Library Characterizer provides an automated, high-throughput model
abstraction and verification solution. This fast and highly accurate
digital characterization technology supports the latest timing, noise,
power, and statistical variation modeling formats.

ENCOUNTER LIBRARY
Setup
CHARACTERIZER Cell
Spectre/
SPICE
Netlist Models
Major IP providers and digital design teams
rely on Encounter Library Characterizer for
its simplified setup and accurate model
generation for standard cells, I/O cells, and
memories. Built on the solid foundation of
Encounter
Cadence SignalStorm® technology—the • process Library
first characterization solution available • voltage Characterizer
for the effective current source model • temperature
(ECSM)—Encounter Library Characterizer • input slew
Spectre Simulator
has a long history of providing accurate • output load
model generation. IP providers will benefit
from its fast and accurate characterization
and parallel simulation capabilities, and .lib VHDL
will be ready to meet current and future
customer demand for advanced timing, ECSM CCS
noise, power, and statistical variation
library models. HTML Timing Timing Verilog

One challenge designers face when Noise Noise

implementing a power savings strategy
or moving to a smaller process node is Power Power
the need for numerous, more advanced
sets of standard-cell libraries. For ASIC Stat.
and CoT designers, this can be a real
barrier to realizing their ultimate vision. Figure 1: Encounter Library Characterizer delivers a unified system for fast, accurate, and advanced model generation
To implement a particular design strategy – Supports manual vectors ADVANCED AUTOMATIC LOGIC
and meet their power requirements, RECOGNITION
• Enables state-dependent power
designers need custom standard-cell
characterization The propagation delay between some
libraries at specialized process, voltage,
input ports and output ports depends on
and temperature (PVT) points. The cost • Includes a library validation suite
the status of other input ports. Two types
and turnaround time needed to obtain for output library verification, SPICE
of logic are state dependent: complex
these libraries can limit the aggressiveness correlation, and comparison
gates (AOI and OAI) and exclusive logic
of the power-saving strategy employed.
• Delivers exceptional ease-of-use such as XOR and XNOR. During the logic
Using Encounter Library Characterizer,
recognition stage, Encounter Library
designers are free to generate any PVT – Supports simultaneous process
Characterizer automatically detects state-
corner in-house, giving them greater corners
dependent logic and generates vectors to
flexibility while minimizing the cost
– Supports multiple circuit simulators comprehensively exercise the logic.
of obtaining custom libraries from IP
providers (Figure 1). – Provides advanced automatic logic ADAPTIVE LIBRARY
recognition for complex gates RE-CHARACTERIZATION
BENEFITS – Offers incremental and detailed Designers needing an extra corner,
• Unified characterization system delivers runtime status reporting as well as library vendors updating IP
faster, simultaneous model generation libraries, will benefit from the ability to
• Generates HTML data sheets
– Automatically creates abstracted use existing .lib files to save runtime
• Supports adaptive library during the characterization process. The
models for standard cell and
re-characterization library re-characterization feature utilizes
I/O cell characterization and
re-characterization – Saves runtime for re-generated information in the timing library—such
libraries for new PVTs, etc. as function, arcs, I/P slew, and O/P load
– Supports IP characterization range—to reduce the dependence on
– Uses advanced logic recognition gate recognition by performing automatic
– Now supports memory
when function statement not present sensitization for simulation vectors.
re-characterization
For incomplete cells, adaptive logic
• Offers high-throughput parallel job FEATURES recognition technology automatically
execution and management
Encounter Library Characterizer provides uses logic recognition to determine the
– Supports parallel simulation job a comprehensive characterization solution function while preserving the arcs in the
control designed to meet the standard-cell original seed library. This enables fast,
modeling needs of today’s advanced incremental characterization for different
– Supports simultaneous corners and
digital design flows. It is designed to supply voltages and temperatures, process
models
support advanced low-power, 28nm, changes, format changes, or underlying
– Improves performance up to 13x over multi-corner design methodologies and subcircuit changes.
previous releases can characterize for:
SUPPORT FOR LOW-POWER CELLS
• Supports advanced modeling formats • State-dependent pin-to-pin delay
Encounter Library Characterizer supports
– ECSM (effective current source • Input timing constraints (setup/hold/ advanced low-power library model
modeling) for delay, noise, power, pulse width) generation and complex state retention
and statistical power gating (SRPG) cells. For SRPG cells,
• Power consumption (internal/leakage)
– CCS (composite current source timing constraints between sleep, save, and
• Input/output pin capacitance restore pins are automatically recognized
modeling) for delay, noise, and power
• Input pin threshold voltage and generated. It characterizes for:
– Liberty NLDM (non-linear delay
modeling) • Output pin transition time • Combinational cells with or without a
pull-up/pull-down device
– Liberty NLPM (non-linear power • ECSM and CCS driver/receiver models
modeling) • Sequential cells with or without a
pull-up/pull-down device
• Provides automatic and optimized
vector generation • Sequential cells with balloon structure
with or without a pull-up/pull-down
device

www.cadence.com ENCOUNTER LIBRARY CHARACTERIZER 2

• Power shutoff cells • Supports multi-piece pin-cap modeling co-mingle. The SI extensions are based
for greater accuracy on short, high- on the cdB format, which is production-
• Level shifters
fanout nets proven in more than 1,000 tapeouts.
ACCURATE NLDM When used in conjunction with power
• Works with Encounter Digital
and timing extensions, ECSM noise
CHARACTERIZATION Implementation System, Encounter
extensions will accurately measure the
The industry-standard Liberty (or .lib) format Timing System, and third-party tools
cumulative impact of IR drop and noise on
utilizes non-linear delay models (NLDMs) delay and provide a comprehensive view
to estimate delay as a function of gate
ECSM POWER MODEL
of timing as well as power signoff.
input slew and the network loading on the CHARACTERIZATION
output. Encounter Library Characterizer Encounter Library Characterizer generates ECSM noise model characterization:
accurately generates these models to ECSM for power inside the .lib format • Generates Si2-approved ECSM noise
support synthesis and static timing analysis library and enables dynamic or static extensions
(STA), and provides a baseline for more gate-level power-consumption analysis
advanced modeling formats. by characterizing the actual current • Characterizes for noise delay and glitch
drawn from the power grid at any given models
ECSM DELAY MODEL time for individual cells. The extension – Accurately models the driving stage
CHARACTERIZATION allows storage of current waveforms at of each gate noise on delay
Modeling the voltage impact on delay can power-grid pins for different combinations
of slew and load. – Models the effective holding resis-
be particularly problematic for low-power
tance of the output stage of the cell
applications. The effective current source ECSM power model characterization: for glitch analysis
model (ECSM) for timing is an advanced
cell driver model that represents the effect • Generates Si2-approved ECSM power • Uses advanced voltage-in/voltage-out
of non-linear switching waveforms on extensions (ViVo) models that capture the effective
cell-based interconnect delay calculation. • Characterizes dynamic current cell I-V characteristics
It has consistently demonstrated superior signatures of power and ground pins, – Each current model is represented
delay calculation accuracy by modeling represented in ECSMs as current by a ViVo waveform on an input or
a cell’s output drive as a current source waveforms output pin of a cell
rather than a voltage source. Current
sources are more effective at tracking – Supports either 2D or 3D lookup – 2D lookup table is used to store
non-linear transistor switching behavior, tables values of I (Vi, Vo)
and they permit highly accurate modeling – Generates piecewise linear (PWL) • Also considers internal pins
of the complex interconnect common representations of current waveforms
in today’s largest low-power designs. It • Is supported by Encounter Timing
is also the only approved standard from • Can incrementally add ECSM power System and Encounter Digital
the Silicon Integration Initiative’s Open extensions to existing .lib Implementation System
Modeling Coalition (www.si2.org). • Is supported by Encounter Power
System and Encounter Timing System
CCS TIMING MODEL
ECSM delay model characterization:
CHARACTERIZATION
• Used for thousands of tapeouts since ECSM NOISE MODEL The composite current source (CCS)
2001 CHARACTERIZATION model is a new, current-based model
• Delivers accuracy to within 2% of SPICE The risk of signal integrity (SI)-related similar to ECSM that models current
with non-linear IR drop derating failures in silicon increases greatly at 90nm vs. time and multi-piece capacitances
and below. Using advanced voltage-in/ to enable more accurate static timing
– .lib (NLDM) can be off by as much analysis. Encounter Library Characterizer
voltage-out relationships, Encounter
as 20% provides efficient CCS characterization,
Library Characterizer can generate ECSM
• Is an Si2-approved standard noise extensions to .lib that enable SI which picks current waveform points
analysis technologies (such as Encounter intelligently to maximize accuracy while
• Offers voltage-based characterization minimizing library size.
Timing System) to model the cumulative
for greater accuracy and ease of
effects of noise introduced by coupling
adoption
capacitances in complex scenarios where
multi-Vt and multi-voltage devices

www.cadence.com ENCOUNTER LIBRARY CHARACTERIZER 3

CCS NOISE MODEL
CHARACTERIZATION
The CCS noise model provides cell-
level noise models to enable support
for some noise analysis solutions.
Characterization includes:

• Current-based driver model

• Receiver model

CCS POWER MODEL

CHARACTERIZATION
The CCS power model provides additional
information for dynamic and static power
analysis similar to that provided by ECSM
power analysis. Characterization includes:

• DC current

• Output voltage

• Noise propagation

• Miller capacitance
Figure 2: Encounter Library Characterizer offers advanced validation tools
SILICON-ON-INSULATOR SUPPORT
Partially depleted silicon-on-insulator
(SoI) process technology requires special
the ecsmChecker can perform gross requirements. Memories and IP blocks
handling during library characterization
checks on library data to ensure they meet are an increasingly large part of today’s
so that the floating body history effect
specifications. highly integrated SoC designs and must
can be properly modeled during timing
also be considered when creating new
analysis. Encounter Library Characterizer The LibDiff utility provides valuable
voltage domains or reducing design
can automatically generate the minimum/ information on the changes from the
margins. Often memories and custom
maximum SoI libraries for each process original seed library. It also checks for
macro timing views are only available in
voltage temperature (PVT) library corner. syntax and semantic problems with the
a selected set of voltages from a given
This enables the history effect to be input libraries (Figure 2). This information
provider, which may not be optimal
modeled during static timing analysis is all presented in an easy-to-read
for your specific application. Memory
when used in conjunction with the graphical interface that shows:
generators can also be quite conservative,
simultaneous minimum/maximum mode.
• Minimum, maximum, and average error which can lead to overdesign. Encounter
(absolute or relative) for timing and Library Characterizer’s ability to generate
LIBRARY VALIDATION SUITE
power, including waveforms new voltages and more accurate timing
Once libraries are generated for the views from existing memory or custom
first time, or when new PVTs are • CCS and ECSM waveforms
macro netlists improves chip performance
re-characterized from an existing set, • Line-by-line library text comparison and helps you meet your power
it is important to ensure integrity and consumption targets. The memory and
accuracy. Any problems need to be The suite also includes validation utilities
IP characterization solution performs fast
corrected before they cause hard-to- which can check the accuracy of the
and accurate re-characterization for:
correct issues in the design flow. generated libraries compared to static
Encounter Library Characterizer provides timing analysis and SPICE. • Smaller custom macros and memories
an advanced set of validation tools to leveraging Cadence Spectre® Circuit
help library developers quickly validate the IP AND MEMORY Simulator or Virtuoso® Accelerated
library output and identify problems early. RE-CHARACTERIZATION Parallel Simulator
Standard cells are not the only views • Large memories leveraging Virtuoso
The ecsmChecker utility checks for syntax
that need to be re-characterized in UltraSim Full-Chip Simulator (FastSPICE)
and semantics issues that would normally
order to meet power and accuracy
be flagged by library parsers. In addition,

www.cadence.com ENCOUNTER LIBRARY CHARACTERIZER 4

Encounter Library Characterizer’s memory
characterization can generate most Total leakage PDF
standard formats including the advanced 1.20E-04
current source modeling and power
1.00E-04
modeling formats. Encounter
8.00E-05 Spice Monte Carlo

ADVANCED SIMULATION AND 6.00E-05

PDF
ANALYSIS
4.00E-05
To ensure the flexibility that is critical in 2.00E-05
today’s digital design processes, Encounter
0.00E+00
Library Characterizer supports the Spectre 0 10000 20000 30000 40000 50000 60000
Circuit Simulator as well as HSpice and -2.00E-05
Eldo. It also generates statistical timing Leakage (nW)

and leakage power formats used for

Figure 3: Encounter Library Characterizer GXL uses statistical ECSMs for leakage power characterization to avoid
modeling variation in advanced designs.
overdesign

STATISTICAL PROCESS VARIATION

MODELING consumption, improves chip performance likelihood of occurring in real silicon.
by as much as 20%, and allows designers Since cell leakage has an exponential
Process variation—which at 90nm and
to explore the potential tradeoff between response to process variation—meaning
above had a manageable impact on
parametric yield and clock speed. that a small change in process variation
delay—has a much more dramatic effect as
causes a major shift in transistor
process geometries shrink. For example, a Advanced features include:
leakage—the probability distribution
0.01μm variation at the 1μm process node
• Si2-approved statistical ECSM gener- becomes skewed such that the extreme
is only 1% of the nominal. However, the
ation for greater accuracy worst-case scenario has a very small
same 0.01μm variation at 65nm is greater
chance of occurring (Figure 3). This leads to
than 15% of the nominal. • Sensitivity-based analysis (delay per
aggressive overdesign, overcompensation
parameter change)
In traditional static timing analysis for IR drop, and potentially unnecessary
(STA), this variability is accounted • Nominal + delay due to changes in architectural changes.
for by introducing more aggressive parameters
The solution is to model the leakage
gross guardbands and new analysis
• Within-the-die, die-to-die, and random power as a statistical probability to avoid
corners to model different process and
variation modeling support designing to the worst-case limit. This
environmental variation combinations
enables designers to target a smaller,
over multiple analysis runs. The corner- • Support for Encounter Timing System,
more reasonable leakage number, which
based approach can be overly pessimistic Encounter Digital Implementation
can be as much as 40% smaller than
since it can report timing scenarios that System, and third-party tools
that from traditional worst-case leakage
have an extremely small likelihood of
power analysis. Encounter Library
occurring. STATISTICAL LEAKAGE POWER
Characterizer GXL is foundry-certified for
MODELING
In contrast, statistical static timing leakage power characterization using the
analysis (SSTA) signoff uses advanced At smaller process geometries, leakage statistical ECSM format:
statistical ECSMs to determine the power begins to dominate the power
consumed by CMOS devices. Accurately • State-dependent exponential leakage
probability of timing failure over the full
modeling device leakage is critical power variation with respect to process
range of process variation. SSTA can also
to achieving an efficient low-power parameters
account for the variability of the process
parameters in a single run. This reduces solution. Existing leakage power analysis • Die-to-die, within-the-die (spatially
both pessimism and guardbanding, techniques use a pessimistic worst-case correlated), and random variation
which in turn decreases area and power leakage scenario that has a very small

www.cadence.com ENCOUNTER LIBRARY CHARACTERIZER 5

PACKAGING CADENCE SERVICES AND
Encounter Library Characterizer is SUPPORT
available in XL and GXL base licenses. • Cadence application engineers can
answer your technical questions by
PLATFORMS telephone, email, or Internet—they can
also provide technical assistance and
• Linux (32-bit, 64-bit)
custom training
• Solaris (64-bit)
• Cadence certified instructors teach
• AIX (64-bit) more than 70 courses and bring
their real-world experience into the
• Sol86 (64-bit)
classroom

STANDARD INTERFACE • More than 25 Internet Learning

SUPPORT Series (iLS) online courses allow you
the flexibility of training at your own
• Inputs: SPICE subckt, SPICE models,
computer via the Internet
.lib, setup_file (for slew, load, operating
condition information), and statistical • Cadence Online Support gives you
config file (for parameter variation) 24x7 online access to a knowledge
base of the latest solutions, technical
• Outputs: .lib + ECSM timing, noise,
documentation, software downloads,
power, and statistical formats, and CCS
and more
• Simulators: Cadence Spectre, Synopsys
HSpice, Mentor Eldo

For more information

contact Cadence sales at:
+1.408.943.1234
or log on to:
www.cadence.com/
contact_us

© 2011 Cadence Design Systems, Inc. All rights reserved. Cadence, the Cadence logo, Encounter, SignalStorm, Spectre, and Virtuoso are registered
trademarks of Cadence Design Systems, Inc. All others are properties of their respective holders.
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