Verilog Implementation of Master-Slave Communication

Using the I2C Protocol

Internship Report

Submitted by

DEVINENI ANUSREE (218W1A04E6)

In partial fulfillment of the requirements

for the award of the degree of

Bachelor of Technology
in
Electronics and Communication Engineering

Department of Electronics and Communications Engineering

Velagapudi Ramakrishna Siddhartha Engineering College
Kanur, Vijayawada - 520007

November, 2024
 Department of Electronics and Communications Engineering
Velagapudi Ramakrishna Siddhartha Engineering College
Kanuru, Vijayawada - 520007

CERTIFICATE

This is to certify that the Internship report entitled ‘Verilog Implementation of

Master-Slave Communication Using the I2C Protocol’ was prepared and presented
by DEVINENI ANUSREE (218W1A04E6) of B. Tech, 7th semester, in Electronics
and Communication Engineering, in partial fulfillment of the requirements for the
award of the Degree of Bachelor of Technology in Electronics and Communication
Engineering at Velagapudi Ramakrishna Siddhartha Engineering College, affiliated
with Jawaharlal Nehru Technological University, Kakinada, during the academic year
2024-2025.

FACULTY GUIDE HEAD OF DEPARTMENT

(Dr. D. Venkata Rao)

(G.VENKATA

SUBBAIAH) DATE:

DATE:

ii
 Department of Electronics and Communications Engineering
Velagapudi Ramakrishna Siddhartha Engineering College
Kanuru, Vijayawada - 520007

DECLARATION

I, DEVINENI ANUSREE (218W1A04E6) of B. Tech 4th year in Electronics

andCommunication Engineering at Velagapudi Ramakrishna Siddhartha Engineering
Col- lege, Kanuru, Vijayawada, here by declare that this internship has been carried
out at ‘SkillDzire’ for a period of 8 weeks and the report has been submitted in partial
fulfil-ment for the requirement of B. Tech curriculum.

Place:

Date: D.ANUSREE
(218W1A04E6)

iii
Table of Contents

Certificate ii

Declaration iii

Table of Contents iv

List of Figures vi

Abstract vii

About The Company viii

1 Introduction 1
1.1 Background ..................................................................................................... 1
1.2 Overview of the I2C Protocol ......................................................................... 1
1.2.1 Protocol Basics ................................................................................... 1
1.2.2 Master-Slave Architecture .................................................................. 2

2 Proposed Approach 4
2.1 Introduction ..................................................................................................... 4
2.2 Methodology ................................................................................................... 4
2.2.1 State Machine Design......................................................................... 4
2.2.2 Clock Synchronization ....................................................................... 5
2.2.3 Data Transfer Management ................................................................ 6
2.2.4 Bidirectional SDA Management ........................................................ 7
2.2.5 Error Handling and Debugging .......................................................... 7
2.2.6 Simulation and Testing....................................................................... 7

3 Results and Discussion 8

3.1 Introduction ..................................................................................................... 8

iv
 3.2 Evaluation and Discussion .............................................................................. 8

4 Conclusion 10

v
List of Figures

1.1 SDA and SCL diagram .................................................................................... 2

1.2 Masterand Slave diagram ................................................................................ 3

2.1 Clock Synchronization .................................................................................... 6

2.2 Data transfer Management .............................................................................. 6

3.1 Resultant waveform......................................................................................... 9

vi
 Abstract

This project explores the design and implementation of an I2C master controller using
Verilog, a Hardware Description Language (HDL) ideal for synthesizing communication
protocols at the hardware level. The I2C protocol is widely used in embedded systems
for its simplicity and efficiency, allowing multiple slave devices to communicate with
a master over just two lines (SDA and SCL). This project focuses on creating a robust,
state-machine-driven Verilog design that manages the full I2C transaction cycle, includ-
ing start and stop conditions, slave addressing, data transfer, clock synchronization, and
acknowledgment signaling. Simulation results validate the I2C master’s effectiveness
in handling both read and write operations with accurate timing, and bidirectional data
control. The outcomes highlight Verilog’s strength in realizing complex protocol behav-
iors on hardware, making this design suitable for various embedded applications, such
as microcontrollers and SoC designs, where efficient and reliable serial communication
is essential.

vii
 About The Company

Skill Dzire is a forward-thinking organization specializing in skill development, work-

force training, and career enhancement services aimed at bridging the gap between aca-
demic knowledge and industry requirements. Focused on empowering students, recent
graduates, and young professionals, the company provides a diverse range of training
programs tailored to enhance employability skills in high-demand fields such as infor-
mation technology, digital marketing, software development, and data science.
The company’s mission is to make skill-based learning accessible, relevant, and impact-
ful, preparing individuals for successful careers in competitive job markets. Skill Dzire
emphasizes a hands-on approach to training, often combining theoretical lessons with
practical applications. Through collaborations with industry experts, the company of-
fers real-world insights, helping learners gain experience in areas that mirror actual work
environments. This approach not only helps individuals gain confidence but also equips
them with the problem-solving skills essential for professional success.
Skill Dzire also partners with corporate clients to provide customized training solu-
tions, addressing specific organizational needs and helping businesses upskill their ex-
isting workforce. Their corporate training programs range from technology and soft-
ware skills to soft skills development, ensuring a comprehensive approach to employee
growth. Skill Dzire’s offerings are designed to increase productivity, adaptability, and
performance within teams, fostering a more innovative and efficient workplace.
Through a blend of in-person and online training options, Skill Dzire ensures flexibil-
ity for both individual learners and corporate clients. The company’s curriculum is
constantly updated to reflect the latest trends and advancements in various industries,
making its programs relevant to the ever-evolving job market. By prioritizing skill en-
hancement and fostering a culture of lifelong learning, Skill Dzire plays a vital role in
shaping a skilled and competent workforce equipped to meet the challenges of modern
industries.

viii
Chapter 1

Introduction

1.1 Background
The I2C protocol, developed by Philips, is widely used in embedded systems to enable
communication between various integrated circuits, such as microcontrollers, sensors,
and memory devices, using only two bidirectional lines—SDA (data line) and SCL
(clock line). Due to its simplicity, it has become essential for applications requiring
low-speed, short-distance communication. However, implementing the I2C protocol re-
quires precise timing control, acknowledgment handling, and reliable state transitions
to maintain data integrity and synchronization.

1.2 Overview of the I2C Protocol

The Inter-Integrated Circuit (I2C) protocol is a simple and widely used communica-
tion protocol in embedded systems, enabling low-speed, short-distance communication
between integrated circuits (ICs) on the same board. Developed by Philips in the early
1980s, I2C is known for its efficiency and flexibility, as it supports multi-device commu-
nication with minimal wiring. I2C’s unique architecture allows it to operate in a variety
of applications, from connecting microcontrollers to sensors in consumer electronics to
handling data transfers in automotive and industrial systems.

1.2.1 Protocol Basics

The I2C protocol relies on only two bidirectional lines—Serial Data Line (SDA) and
Serial Clock Line (SCL)—to manage communication between devices. This simplicity

1
 Chapter 1 – Introduction

in wiring reduces the overall cost and complexity, making it ideal for applications where
multiple devices need to communicate efficiently over a shared bus.

• SDA (Serial Data Line): This line carries the actual data being transmitted be-
tween devices. It is bidirectional, meaning it can switch between reading and
writing as necessary to enable data flow in both directions.

• SCL (Serial Clock Line): The clock line is generated by the master device to
synchronize the data transfer. Since the communication is synchronous, each data
bit is transmitted with a corresponding clock pulse, ensuring timing consistency
across the network.

The combination of these two lines allows I2C to operate efficiently in multi-device
configurations. To prevent conflicts on the shared bus, both lines are typically connected
to a pull-up resistor, setting the lines to a high state when idle. When devices transmit
data, they actively pull the line low, creating a sequence of high and low voltages that
represent binary data.

Figure 1.1: SDA and SCL diagram

1.2.2 Master-Slave Architecture

I2C follows a master-slave communication model, where one device acts as the master
and controls the timing and flow of data across the bus, while other devices act as slaves.
This architecture ensures organized data transfer and minimizes conflicts on the shared
bus.

• Master Device: The master is responsible for initiating and controlling data trans-
fer. It generates the clock signals on the SCL line, defines the direction of data
flow (read or write), and initiates communication with slaves by issuing a start
condition. The master also terminates communication with a stop condition, sig-
naling the end of a transaction.

2
 Chapter 1 – Introduction

• Slave Devices: Each slave device has a unique 7-bit address, which allows it to
respond only to communications that match its address. Once addressed by the
master, a slave will either transmit data back to the master (in read operations) or
receive data from the master (in write operations). The slave follows the master’s
timing signals, ensuring synchronous communication on the bus.

This master-slave arrangement supports up to 128 unique addresses (with 7-bit address-
ing), enabling multiple devices to coexist on the same I2C bus. In cases where additional
devices are needed, I2C supports 10-bit addressing, extending the address range for more
complex systems.

Figure 1.2: Master and Slave diagram

3
Chapter 2

Proposed Approach

2.1 Introduction
The proposed architecture for the I2C protocol implementation using Verilog consists of
several key components that work together to facilitate communication between a master
device and multiple slave devices. The architecture is designed to handle various states
of the I2C communication cycle, ensuring efficient data transfer and synchronization.
Below is a detailed overview of the proposed architecture.

2.2 Methodology
The I2C master module is implemented using Verilog HDL to create a reliable commu-
nication interface for controlling and exchanging data with multiple slave devices. This
design allows the master device to initiate and manage data transactions over the I2C
bus by implementing the start, stop, address, acknowledgment, and data phases of the
protocol. Each of these phases is controlled by a state machine that synchronizes with
the clock to ensure correct timing and orderly data transfer.

2.2.1 State Machine Design

The I2C protocol is inherently state-based, requiring careful control over the timing of
events such as start and stop conditions, address transmission, acknowledgment (ACK),
data read/write, and stop signaling. The master module leverages a Finite State Machine
(FSM) to manage these phases:

• IDLE: The module starts in the IDLE state, where it waits for the start signal. In

4
 Chapter 2 – Proposed Approach

this state, SDA and SCL lines are both high, indicating that the bus is idle and
ready for communication.

• START: When the start signal is asserted, the FSM transitions to the START state,
pulling the SDA line low while keeping the SCL line high to signify the start of a
data transfer.

• ADDRESS: In this state, the master sends a 7-bit address of the target slave device
along with a read/write (R/W) bit. Each bit is clocked out on the rising edge of
SCL. The state machine monitors a counter that decrements for each transmitted
bit until all 8 bits are sent.

• ACK: After sending the address, the master releases SDA to allow the slave to
respond. If the slave pulls SDA low, it signals acknowledgment (ACK), indicating
it is ready to communicate. The master checks SDA on the SCL clock edge to
determine if the acknowledgment is received.

• DATA: The data state is entered after a successful acknowledgment. Depending

on the R/W bit, the master either sends data (write operation) or reads data from
the slave (read operation). A counter tracks the number of bits sent or received.

• STOP: The STOP state concludes the communication sequence. Here, the SDA
line is pulled high while SCL is high, signaling the end of data transfer. After this,
the state machine returns to IDLE.

2.2.2 Clock Synchronization

To comply with the I2C protocol, the master module must generate and control the clock
signal (SCL). The module achieves this using a clock divider, which creates an appro-
priate I2C clock frequency based on the system clock. Here’s how it works:

• Clock Divider: An internal scl_counter divides the main system clock down to
match the desired I2C bus speed.

• SCL Signal Generation: When scl_counter reaches a predetermined value, the

SCL signal toggles, generating the clock pulse required for synchronized data
transfer.

• Data Synchronization: Data is only transmitted or read on specific edges of the

SCL signal, ensuring that both master and slave devices stay in sync during data
transfer.

5
 Chapter 2 – Proposed Approach

Figure 2.1: Clock Synchronization

2.2.3 Data Transfer Management

The data transfer in I2C involves both transmitting and receiving data based on the R/W
bit, and the methodology differs slightly depending on whether data is written to or read
from the slave device.

• Address and R/W Transmission: The 7-bit slave address is combined with the
R/W bit into an 8-bit register (addr_rw). This register shifts out one bit per SCL
clock pulse during the ADDRESS state.

• Write Operation: When the R/W bit is 0, indicating a write operation, data from
data_in is shifted out bit by bit on SDA. The FSM controls data-count to track the
number of bits transmitted.

• Read Operation: When the R/W bit is 1, the master receives data on SDA. The
received data bits are sequentially stored in the read-data register, accumulating
to form the complete 8-bit byte.

Figure 2.2: Data transfer Management

6
 Chapter 2 – Proposed Approach

2.2.4 Bidirectional SDA Management

The SDA line in I2C is bidirectional, meaning it is used for both data transmission and
acknowledgment signaling. This module handles the bidirectional nature of SDA with
the following approach:

• SDA as Output: During the ADDRESS, DATA (write), and STOP states, the
module actively drives SDA, setting it high or low based on the data being sent.

• SDA as Input: During the ACK and DATA (read) states, the master releases
SDA, allowing the slave to control it. This is achieved by enabling or disabling
SDA_OUT, effectively switching SDA between input and output modes.

The Verilog code implements this functionality through a conditional assignment, where
SDA is high-impedance (1’bz) when not being driven, allowing other devices to control
it when necessary.

2.2.5 Error Handling and Debugging

To enhance robustness, the I2C master module includes basic error handling. If an ex-
pected acknowledgment is not received, the state machine can revert to the IDLE state
or attempt retransmission. Additionally, debugging registers like state, counter1, and
data_count are used to monitor the state and bit progress, simplifying verification and
debugging during simulation.

2.2.6 Simulation and Testing

The module was simulated using various test cases to validate its functionality:

• Basic Read/Write Transactions: The module’s ability to perform simple read and
write operations was tested by simulating the response of a slave device.

• Address Acknowledgment: The module was tested with various slave addresses
to confirm that it correctly waits for and responds to acknowledgments.

• Error Handling: Scenarios where the slave fails to acknowledge or does not re-
spond within expected clock cycles were simulated to test error-handling behavior.

7
Chapter 3

Results and Discussion

3.1 Introduction
The simulation waveform demonstrates the I2C master module’s performance across
key phases of the I2C protocol, including start, address transmission, acknowledgment,
data transfer, and stop conditions. By examining signals such as ‘SCL‘ (clock), ‘SDA‘
(data line), ‘data_in‘, ‘address‘, and control flags like ‘done‘ and ‘rst‘, we validate the
module’s correct operation. The transitions observed in the waveform confirm that the
module effectively manages communication initiation, slave acknowledgment, and data
synchronization with the clock. This analysis supports that the I2C master module suc-
cessfully adheres to protocol specifications, ensuring reliable communication with slave
devices on the I2C bus.

3.2 Evaluation and Discussion

In the evaluation of the simulation waveform, the I2C master module demonstrates ac-
curate adherence to the I2C protocol phases, which include the start condition, address
transmission, acknowledgment (ACK), data transfer, and stop condition. The ‘SCL‘
clock signal exhibits a consistent toggling pattern, which is essential for timing synchro-
nization between the master and slave devices. The start condition is correctly generated
with the ‘SDA‘ line transitioning from high to low while ‘SCL‘ is high, signaling the
start of communication.
During the address phase, the 7-bit ‘address‘ is transmitted bit by bit on ‘SDA‘, matching
the expected binary value and identifying the target slave device. The transition to the
ACK phase is observed as the module releases the ‘SDA‘ line, allowing the slave to pull

8
 Chapter 3 – Results and Discussion

it low, which it does successfully to acknowledge the address. This response validates
proper slave communication.
In the data transfer phase, the module shifts out data from ‘data_in‘ in synchronization
with ‘SCL‘, confirming correct transmission. The stop condition, shown as a transition
of ‘SDA‘ from low to high while ‘SCL‘ is high, marks the end of the communication
cycle, releasing the bus. The ‘done‘ signal indicates successful completion of the oper-
ation, ensuring reliable I2C communication.
This evaluation confirms that the module functions as expected, handling each protocol
phase accurately and supporting stable data exchanges with I2C-compatible devices.

Figure 3.1: Resultant waveform

9
Chapter 4

Conclusion

In conclusion, this project successfully implements an I2C master module in Verilog,

achieving reliable communication with slave devices in compliance with the I2C proto-
col. Through rigorous testing and waveform analysis, each phase of the I2C protocol—
start, address transmission, acknowledgment, data transfer, and stop—is accurately ex-
ecuted by the module, ensuring stable and synchronized data exchanges. The simula-
tion results confirm that the module generates the clock (‘SCL‘), manages the data line
(‘SDA‘), and adheres to protocol timing requirements, including proper generation of
start and stop conditions and handling of slave acknowledgments. The design achieves
reliable data transfer by shifting data in and out precisely, which is crucial for applica-
tions requiring efficient serial communication. Overall, this I2C master module demon-
strates robust performance and protocol compliance, making it a viable component for
integration in systems that require standardized, efficient communication with multiple
I2C-compatible devices.

10