Advanced Syste

em Architecture

Lecturre 33-44
Words and Bytes

• 232 by
bytes
es : by
byte
e add
addresses
esses from
o 0 to
o 232-1

• 230 words : byte addressess 0, 4, 8, ... 232-4

 Big-Endian and Little-E
Endian Memory
• Word address is the same for big
g- or little-endian

• Little-endian: byte numbers start at the little (least significant) end

• Big-endian: byte numbers start att the big (most significant) end

Big-Endian Little-Endian
Byte Wordd Byte
Address Addres
ss Address

C D E F C F E D C
8 9 A B 8 B A 9 8
4 5 6 7 4 7 6 5 4
0 1 2 3 0 3 2 1 0
MSB LSB MSB LSB
 Big Endian Address
sing
• With Big Endian addressing, the
t byte binary address
x . . . x00
is in the most significant position (big end) of a 32 bit
word (IBM, Motorolla, Sun, HP P).

M SB
S LSB
S
0 1 2 3
4 5 6 7
Little Endian Addre
essing
• With Little Endian addressing, th he byte binary address
x . . . x00
is in the least significant position
n (little end) of a 32 bit word (DEC,
Intel).
)

M SB LSB
3 2 1 0
7 6 5 4

• Programmers/protocols shou uld be careful when transferring

binary data between Big Endiaan and Little Endian machines
Big- and Little-Endiian Example
• Suppose, $t0 initially containss 0x23456789. After the following
program is run on a big-endian system,
s what value does $s0 contain?
I a little-endian
In littl di system?
t ?
sw $$t0,, 0($0)
($ )
lb $s0, 1($0)

• Big-endian: 0x00000045
• Little-endian: 0x00000067

Big-Endian
g Little-Endian
Wordd
Byte Address 0 1 2 3 Address 3 2 1 0 Byte Address
Data Value 23 45 67 89 0 23 45 67 89 Data Value
MSB LSB MSB LSB
Operands: Constants/Immediates
• lw and sw illustrate the use of co onstants or immediates
• Called immediates because theyy are immediately available
from the instruction
• Immediates dondon’tt require a regisster or memory access.
• Add immediate (addi) instruction n adds an immediate to a
variable ((held in a register).
g )
• An immediate is a 16-bit two’s co omplement number.

High-level code M
MIPS assembly code
# $s0 = a
a, $s1 = b
a = a + 4; ad
ddi $s0, $s0, 4
b = a – 12; ad
ddi $s1, $s0, -12
Constants in MIPS instructions

• addi $29, $29, 4 ‘i’ is for

f ‘immediate’
• slti $8, $18, 10
andi $29, $29, 6
ori $29, $29, 4
How about larger constants?
c

To load a 32 bit constant into a reegister, we use two instructions

one instruction fills this one instruction fills this

1010101010101010 1111000011110000
Loading larger consttants
• "load upper immediate" instructio on
l i $t0,
lui $t0 1010101010101010
• then get the lower order bits right, i.e.,
orii $t0,
$t0 $t0,
$t0 11110000111100000

1010101010101010 0000000000000000
0000000000000000 1111000011110000
1010101010101010 1111000011110000
Instruction Formats

R -T y p e
op rs rt rd sham t fu n c t
6 b its 5 b its 5 b its 5 b its 5 b its 6 b its

I- T y p e
op rs rt im m
6 b its 5 b its 5 b its 1 6 b its

J -T y p e
op addr
6 b its 2 6 b i ts
R-Type
• Register-type
Register type
• 3 register operands:
– rs,
rs rtrt: source
so rce registers
– rd: destination register
• Oth fields:
Other fi ld
– op: the operation code or opccode (0 for R-type instructions)
– funct:
f t the th function
f ti
together, the opcodee and function tell the computer
what
h t operation
ti to
t bbee performed
f d
– shamt: the shift amount for shift s instructions, otherwise it’s 0
R -T
T yp
y e
op rs rt rd sham t funct
6 b its 5 b its 5 b its 5 b its 5 b its 6 b its
 R-Type Examples

Assembly Code F ie ld V a lu e s
op rs rt rd sham t fu n ct

0 17 18 16 0 32
add $s0
$s0, $s1,
$s1 $s2
0 11 13 8 0 34
sub $t0, $t3, $t5 6 b its 5 b its 5 b its 5 b its 5 b its 6 b its

Order of registers in the assembly code:

c
add rd, rs, rt
• Instructions are 32 bits long
• registers have numbers 0 .. 31,
e.g., $t0=8,
$ $t1=9,
$ $$s0=16, $$s1=17 etc.
e
 R-Type Examples

Assembly Code
F ie
i ld V a llu e s
op rs rt rd sham t fu n ct
add $s0,
$s0 $s1,
$s1 $s2 0 17 18 16 0 32

sub $t0, $t3, $t5 0 11 13 8 0 34

6 b its 5 b its 5 b its 5 b its 5 b its 6 b its

Order of registers in the assemb

bly code:
add rd,, rs,, rt
• Instructions are 32 bits long
• registers have numbers 0 .. 31,
e.g., $t0=8, $t1=9, $s0=16, $ss1=17 etc.
R-Type Examples

A s s e m b ly C o d e F ie ld V a lu e s
op rs rt rd sham t fu n ct

add $s0, $s1, $s2 0 17 18 16 0 32

sub $t0, $t3, $t5 0 11 13 8 0 34

6 b its 5 b its 5 b its 5 b its 5 b its 6 b its

M achine
hi C ode
de
op rs rt rd s ham t funct

000000 10001 10010 10000 0 0000 100000 (0 02328020)

(0x02328020)

000000 01011 01101 01000 0 0000 100010 (0x016D 4022)

6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

Order of registers in the assembbly code:

add rd, rs, rt
I-Type
Immediate-type
p
• 3 operands:
– rs, rt: register operands
– imm: 16-bit two’s comple p ement immediate
• Other fields:
– op:
p the opcode
p
– Simplicity favors regularity: all instructions have opcode
– Operation
p is completely
p y dettermined byy the opcode
p

I- T y p e
op rs rt im m
6 b its 5 b its 5 b its 1 6 b its
I-Type Examples

Assembly Code Field Values

op rs rt imm

addi $s0, $s1, 5 8 17 16 5

addi $
$t0,
, $s3,
$ , -12 8 19 8 -12

lw $t2, 32($0) 35 0 10 32

sw $s1, 4($t1) 43 9 17 4
6 bits 5 bits
b 5 bits 16 bits

Differing order of registers in the assembly and machine codes:

addi
ddi rt,
t rs, imm
i
lw rt, imm(rs)
sw rt, imm(rs)
 I-Type Examples
A
Assembly
bl CCode
d Fi ld V
Field Values
l
op rs rt imm

addi $s0, $s1, 5 8 17 16 5

addi $t0, $s3, -12 8 19

9 8 -12

lw $t2
$t2, 32($0) 35 0 10 32

sw $s1, 4($t1) 43 9 17 4
6 bit
bits 5 bits 5 bit
bits 16 bit
bits
Machine Code
Differing order of registers in op r
rs rt im m

the assembly and machine 001000 10001

1 10000 0000 0000 0000 0101 (0x22300005)

codes: 001000 10011

1 01000 1111 1111 1111 0100 (0x2268FFF4)

100011 00000
0 01010 0000 0000 0010 0000 (0x8C0A0020)
addi rt, rs, imm
101011 01001
0 10001 0000 0000 0000 0100 (0xAD310004)

lw rt,
rt imm(rs) 6 bits 5 bits 5 bits 16 bits

2’s comp
plement of (-12)=1111 1111 1111 0100
sw rt, imm(rs)
Machine Language: J--Type

Jump-type

• 26-bit address operand (addr)

• Used for jump instructions (j)

J -T y p e
op addr
6 b its 2 6 b its
Power of Stored Program

• 32-bit instructions and data storred in memory

• To run a new program:
– No rewiring required
– Simply store new program in memory
• Processor hardware executes th he program:
p g
– fetches (reads) the instructio
ons from memory in sequence
– pperforms the specified
p opera
p ation
• Program counter (PC) keeps tracck of the current instruction
• In MIPS, programs typically startt at memory address 0x00400000
Stored Program
A s s e m b ly C o d e M a c h in e C o d e
lw $t2, 32($0) 0x8C0A0020
add $s0, $s1, $s2 0x02328020
addi $t0, $s3, -12 0x2268FFF4
sub $t0, $t3, $t5 0x016D4022

S to re d P ro g r a m
A d d re s s I s tr
In t u c tio
ti n s

0040000C 0 1 6 D 4 0 2 2
00400008 2 2 6 8 F F F 4
00400004 0 2 3 2 8 0 2 0
00400000 8 C 0 A 0 0 2 0 PC

M a in M e m o r y
Interpreting Machine La
anguage Code
• Start with opcode
• Opcode tells how to parse the remaining bits
• If opcode is all 0’s
– R R-type
type instruction
– Function bits tell what instructtion it is
• Otherwise
– opcode tells what instruction it is

Machine Code Field Values Assembly Code

op rs rt imm op rs rt imm
(0 2237FFF1) 001000 10001 10111 1111 1111 1111 0001
(0x2237FFF1) 8 17 23 -15 addi $s7, $s1, -15
2 2 3 7 F F F 1

op
p rs rt rd shamt funct op
p rs rt rd shamt funct

(0x02F34022) 000000 10111 10011 01000 00000 100010 0 23 19 8 0 34 sub $t0, $s7, $s3
0 2 F 3 4 0 2 2
Logical Instructions
• and, or, xor, nor
– and:d useful
f l ffor masking
ki b bits
bit
• Masking all but the leeast significant byte of a value:
0 F234012F AND
0xF234012F D 00x000000FF
000000FF = 00x0000002F
0000002F
– or: useful for combining bit fields
• Combine
C bi 00xF2340000
F2340000 with
ith 00x000012BC:
000012BC
0xF2340000 OR 0x000012BC
0 = 0xF23412BC
– nor: usefulf l for
f inverting
i ti bit
bits:
• A NOR $0 = NOT A
• andi,
di ori,
i xorii
– 16-bit immediate is zero-extended (not sign-extended)
– norii not needed
d d
Logical Instruction Exa
amples

S
Source Registers
R i t
$s1 1111 1111 1111 1111 0000 0000 0000 0000

$s2 0100 0110 1010 0001 1111 0000 1011 0111

Assembly Code Result

and $s3, $s1, $s2 $s3
or $s4, $s1, $s2 $s4
xor $s5, $s1, $s2 $s5
nor $s6, $s1, $s2 $s6
Logical Instruction Exa
amples

Source Registers
$s1 1111 11
111 1111 1111 0000 0000 0000 0000

$s2 0100 01
110 1010 0001 1111 0000 1011 0111

Assembly Code Result

and $s3, $s1, $s2 $s3 0100 01
110 1010 0001 0000 0000 0000 0000
or $s4, $s1, $s2 $s4 1111 11
111 1111 1111 1111 0000 1011 0111
xor $s5, $s1, $s2 $s5 1011 10
001 0101 1110 1111 0000 1011 0111
nor $s6, $s1, $s2 $s6 0000 00
000 0000 0000 0000 1111 0100 1000
Logical Instruction Exa
amples

Source Values
$s1 0000 0000
0 0000 0000 0000 0000 1111 1111

imm 0000 0000

0 0000 0000 1111 1010 0011 0100
z
zero
zero-extended
extended
Assembly Code Result
andi $s2, $s1, 0xFA34 $s2
ori $s3, $s1, 0xFA34 $s3
xori $s4, $s1, 0xFA34 $s4
Logical Instruction Examples
E

S
Source Values
V l
$s1 0000
0 0000 0000 0000 0000 0000 1111 1111

imm 0000
0 0000 0000 0000 1111 1010 0011 0100
zero-extended
Assembly Code Result
andi $
$s2,
, $ , 0xFA34 $s2 0000
$s1, 0 0000 0000 0000 0000 0000 0011 0100
ori $s3, $s1, 0xFA34 $s3 0000
0 0000 0000 0000 1111 1010 1111 1111
xori $s4 $s1, 0xFA34 $s4 0000
$s4, $s1 0 0000 0000 0000 1111 1010 1100 1011
Shift Instructions

• sll: shift left logical

– Example: sll $t0, $t1, 5 # $t0 <= $t1 << 5
• srl: shift right logical
– Example: srl $t0, $t1, 5 # $t0 <= $t1 >> 5
• sra: shift right arithmetic
– Example: sra $t0 $t0, $t1
$t1, 5 # $t0 <=
< $t1 >>> 5
Variable shift instructions:
• sllv: shift left logical variablee
– Example: sllv $t0, $t1, $t2 # $t0 <= $t1 << $t2
• srlv: shift right logical variab ble
– Example: srlv $t0, $t1, $t2 # $t0 <= $t1 >> $t2
• srav: shift right arithmetic vvariable
– Example: srav $t0, $t1,, $t2 # $t0 <= $t1 >>> $t2
Shift Instructions

Assembly Code Field Values

V
op
p rs rt rd shamt funct

sll $t0, $s1, 2 0 0 7

17 8 2 0

srl $
$s2,
, $
$s1,
, 2 0 0 17
7 18 2 2

sra $s3, $s1, 2 0 0 17

7 19 2 3
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

Machine Code
op rs rt rd shamtt f
funct

000000 00000 10001 01000 00010 000000 (0x00114080)

000000 00000 10001 10010 00010 000010 (0x00119082)

000000 00000 10001 10011 00010 000011 (0x00119883)

6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
Shift Instructions
Shift Instructions
Shift Instructions
Generating Constants

• 16-bit constants using addi:

High-level code MIPS assembly code
// int is a 32-bit signed word # $s0 = a
int a = 0x4f3c; addi $s0, $0, 0x4f3c

• 32-bit constants using load uppper immediate (lui) and ori:

(lui loads the 16-bit immediatte into the upper half of the register
andd sets the
h lower
l half
h lf to 0.)
0)

High-level code MIPS assemblyy code

# $s0 = a
int a = 0xFEDC8765; u $s0, 00xFEDC
lui C
ori $s0, $s0, 0x8765
Multiplication, Divisio
on

• Special registers: lo, hi

• 32 × 32 multiplication, 64 bit
b result
– mult $s0, $s1
– Result in {hi, lo}

• 32-bit division, 32-bit quotie

ent, 32-bit remainder
– div $s0, $s1
– Quotient in lo
– Remainder in hi

• Moves from lo/hi special registers

– mflo $s2
– mfhi $s3
Branching

• Allows a program to executte instructions out of sequence.

• Types of branches:
– Conditional branches
• branch if equal (beq)
• branch if not equal (bn
ne)
– Unconditional branches
• jump (j)
• jump register (jr)
• jump and link (jal)
Conditional Branchin
ng (beq)
# MIPS assembly
addi $s0, $0, 4 # $s0 = 0 + 4 = 4
addi $s1, $0, 1 # $s1 = 0 + 1 = 1
sll $s1, $s1, 2 # $s1 = 1 << 2 = 4
{0000 0000 0000 0001  0000 00000 0000 0100}
beq $s0, $s1, target # branch is taken n
addi $s1, $s1, 1 # not executed
sub $s1, $s1, $s0 # not executed

target: # label
add $s1, $s1, $s0 # $s1 = 4 + 4 = 8
Branch Not Taken (bn
ne)
# MIPS assembly
addi $s0,
$s0 $0,
$0 4 # $s0 = 0 + 4 = 4
addi $s1, $0, 1 # $s1 = 0 + 1 = 1
sll $s1 $s1,
$s1, $s1 2 # $s1 = 1 << 2 = 4
bne $s0, $s1, target # branch not taken
addi
ddi $s1,
$ 1 $s1,
$ 1 1 # $s1
$ 1=4+1=5
sub $s1, $s1, $s0 # $s1 = 5 – 4 = 1

target:
add
dd $s1,
$ 1 $s1,
$ 1 $$s00 # $s1
$ 1=1+4=5
Unconditional Branchin
ng / Jumping (j)
# MIPS assembly
addi $s0,
$s0 $0,
$0 4 # $s0 = 4
addi $s1, $0, 1 # $s1 = 1
j target # jump p to target
sra $s1, $s1, 2 # not executed
e
addi
ddi $ 1 $s1,
$s1, $ 1 1 # nott executed
e t d
sub $s1, $s1, $s0 # not executed
e

target:
add
dd $ 1 $s1,
$s1, $ 1 $$s00 # $s1
$ 1=1+4=5
Unconditional Branching (jr)
(

# MIPS assembly

0x00002000 addi $s0, $0, 0x2010

0x00002004 jr $s0

0x00002008 addi $s1, $0, 1

0x0000200C sra $s1, $s1, 2

0x00002010 lw $s3, 44($s1)

Conditional Statem
ment

• if statements
t t t

• if/else
if/ l statements

• while loops

• for loops
If Statement

High level code

High-level M
MIPS assembly code

if (i == j) # $s0 = ff, $s1 = g

g, $s2 = h
f = g + h; # $s3 = i, $s4 = j

f = f – i; bne $s3, $s4, L1

b
add $s0
$s0, $s1
$s1, $s2

L sub $s0
L1: $s0, $s0
$s0, $s3
If / Else Statement

High level code

High-level M
MIPS assembly code
# $s0 = f, $s1 = g, $s2 = h
if (i == j) # $s3 = i,i $s4 = j
f = g + h; bne $s3, $s4, L1
else add $s0,
$s0 $s1,
$s1 $s2
f = f – i; j done
L sub $s0,
L1: $s0 $s0,
$s0 $s3
d
done:
 While Loops

High-level code MIPS S assembly code

// determines the power # $ss0 = pow, $s1 = x
// of x such that 2x = 128
int pow = 1; addi $s0, $0, 1
int x = 0; add $s1, $0, $0
addi $t0, $0, 128
while (pow != 128) { whille: beq $s0, $t0, done
pow = pow * 2; sll $s0, $s0, 1
x = x + 1; addi $s1, $s1, 1
} j while
done: