EDC Mid 07082021 083018pm
EDC Mid 07082021 083018pm
Instructions:
1. The PAPER consists of TWO portions: OBJECTIVE portion carries 5 marks and
SUBJECTIVE portion carries 15 marks.
2. Duration for OBJECTIVE portion is 20 MINUTES.
3. OBJECTIVE portion must be solved on the SHEET provided at the end of OBJECTIVE
portion.
4. Attempt all objectives.
5. Give the suitable answer by filling the appropriate choice box completely with the pencil. Pen is
not allowed.
6. Properly fill the choice box. Pen filled, half filled, alphabetical answer, unnecessary tick
marks/signs and more than one filled box will be considered as an invalid answer.
7. Cheating of any type will disqualify the candidate.
8. The work must be neat & clean. Over-writing, cutting will be considered as mistake.
9. Do not detach the sheets. (Paper will be cancelled, if the sheets are detached).
10. Exchange / Borrow of Calculator and Stationary is not allowed.
11. Mobile Phones should be switched off during the examination.
This paper has a total of one section on four sheets including this title page
OBJECTIVE PAPER
SECTION ‘A’ (CLO 1 : Knowledge)
Select the suitable answer from the given choices. (5 Marks)
2
12. In BJTs, emitter follower configuration is also known as _______ configuration.
a) Common base b) Common collector
c) Common emitter d) None of the above
13. In cascaded systems, the overall _______ gain is determined by the product of gains
of the individual stages.
a) Power b) Current c) Voltage d) None of the above
14. The _______ circuit provides a very high current gain.
a) Darlington b) Current mirror c) Feedback pair d) None of the above
15. Current mirror circuits provide constant _______ in integrated circuits.
a) Voltage b) Current c) Power d) None of the above
16. FETs are less sensitive to _______ variations and are more easily integrated on ICs.
a) Frequency b) Power c) Temperature d) None of the above
17. The region to the left of the pinch off point is called the _______ region.
a) Saturated b) Cutoff c) Active d) Ohmic
18. VMOS devices have _______ switching times.
a) Stable b) Faster c) Constant d) Slower
19. _______ biasing is/are possible in JFET biasing circuits.
a) Fixed b) Self c) Voltage divider d) All of the above
20. Source follower amplifier circuit is also known as _______ amplifier circuit.
a) Common drain b) Common gate
c) Common source d) None of the above
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Student’s Name: __________________ Reg. #.: __________________
ANSWER SHEET
Select the suitable answer by filling the appropriate choice box completely with the
pencil. Pen is not allowed.
S. No. a b c d
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
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BAHRIA UNIVERSITY (KARACHI CAMPUS)
Midterm Examination – Fall Semester – 2020
Instructions:
1. The PAPER consists of TWO portions: OBJECTIVE portion carries 5 marks and
SUBJECTIVE portion carries 15 marks.
2. Duration for SUBJECTIVE portion is 70 MINUTES.
3. SUBJECTIVE portion must be solved on the MAIN copy.
4. Attempt all subjective questions.
5. Don’t write anything on the paper. Use answer sheet for the answers.
6. Don’t copy any question on the answer sheet. Just write down the question numbers and give the
answers.
7. Every question should be started from a new page.
8. Questions should be solved in the same sequence in which they are given in the paper.
9. Marks will be deducted in case of the violation of instructions 7 and 8.
10. Mention all the necessary steps which are required in solving a numerical.
11. Mention all the appropriate units which are required during the different calculations of numerical.
12. Write your answers in ink. For drawings pencils may be used.
13. Cheating of any type will disqualify the candidate.
14. The work must be neat & clean. Over-writing, cutting will be considered as mistake.
15. Do not detach the sheets. (Paper will be cancelled, if the sheets are detached).
16. Exchange / Borrow of Calculator and Stationary is not allowed.
17. Mobile Phones should be switched off during the examination.
This paper has a total of one section on three sheets including this title page
SUBJECTIVE PAPER
SECTION ‘B’ (CLO 2 : Analysis)
Analyze the following to provide the required solution. (15 Marks)
Q1) Determine VL, VR, IZ and PZ for the given Zener diode network. Also draw the
corresponding network diagram for the given scenario.
Q2) For the given figure, determine the following for the emitter bias network:
a) IB
b) IC
c) VCE
d) VC
e) VE
f) VB
g) VBC
h) ICsat
2
Q3) For the given network, determine VCEQ and IE.