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MODULE 4- PART-1 INPUT OUTPUT

ORGANIZATION

Introduction

• A general purpose computer should have the ability to exchange information with a wide range
of devices in varying environments.
• Computers can communicate with other computers over the Internet and access information
around the globe.
• They are an integral part of home appliances, manufacturing equipment, transportation systems,
banking and point-of-sale terminals.
Accessing I/O Devices

Figure: A single-bus structure

The I/O devices are connected by using a single bus which enables data transaction between each device
as shown in figure.

• Bus consists of 3 sets of lines used to carry address, data and control signals.

• Each I/O device is assigned a unique set of address. When the processor places a particular
address on the address lines, the device that recognizes this address responds to the commands
issued on the control lines.
• The processor requests either a read or a write operation which is transferred over the data lines.
When I/O devices and the memory share the same address space, the arrangement is called
memory-mapped I/O. There are two ways to deal with I/O devices as shown above figure.

Memory mapped I/O

The Memory and I/O devices are sharing information by a common address-space. Any data-transfer
instruction (like Move, Load) can be used to exchange information. For example,
Move DATAIN, R0;

• This instruction reads data from DATAIN (address of input-buffer associated with Keyboard) &
stores them into processor-register R0.

Move R0, DATAOUT

• This instruction sends the contents of register R0 to location DATAOUT, which may be the
output data buffer of a display unit or a printer.

I/O mapped I/O

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In I/O mapped I/O, the memory and I/0 address-spaces are different. Special instructions are used for
data transfer such as IN and OUT.

• The I/O devices use special I/O address space or memory address space.
• The I/O devices examine the low-order bits of the address bus to determine whether they should
respond.
• Advantage of separate I/O space: I/O devices deal with fewer address-lines.

The hardware required to connect an I/O device to the bus as shown in the figure.

• The address decoder enables the device to recognize its address when this address appears on the
address lines.
• The data register holds the data being transferred to or from the processor.
• The status register contains information relevant to the operation of the I/O device.
• Both the data and status registers are connected to the data bus and assigned unique addresses.
The address decoder, the data and status registers, and the control circuitry required to coordinate
I/O transfers constitute the device’s interface circuit.

Figure: I/O interface for an input device

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Interrupts
• There are many situations where other tasks can be performed while waiting for an I/O device to
become ready. A hardware signal called an Interrupt will alert the processor when an I/O device
becomes ready. It can do so by sending a hardware signal called an interrupt to the processor.

an

• For example, consider, COMPUTE and PRINT routines. The routine executed in response to
interrupt request is called interrupt-service routine.
• Transfer of control through the use of interrupts happens. The processor must inform the device
that its request has been recognized by sending interrupt-acknowledge signal.

• One must therefore know the difference between Interrupt Vs Subroutine. Interrupt latency is
concerned with saving information in registers will increase the delay between the time an
interrupt request is received and the start of execution of the interrupt-service routine.
• Processor is executing the instruction located at address i when an interrupt occurs.
• Routine executed in response to an interrupt request is called the interrupt-service routine.
• When an interrupt occurs, control must be transferred to the interrupt service routine.
• But before transferring control, the current contents of the PC (i+1), must be saved in a known
location.
• This will enable the return-from-interrupt instruction to resume execution at i+1.
• Return address, or the contents of the PC are usually stored on the processor stack.

Interrupt latency: Delay between the time an interrupt request is received and the start of execution of
the interrupt service routine.
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Interrupt Hardware:-
• An I/O device requests an interrupt by activating a bus-line called interrupt-request (IR).
• A single interrupt request line may be used to serve n devices as depicted. All devices are
connected to the line via switches to ground. To request an interrupt, a device closes its
associated switch. Thus, if all interrupt-request signals INTR1 to INTRn are inactive, that is, if
all switches are open, the voltage on the interrupt-request line will be equal to Vdd.
• This is the inactive state of the line. Since the closing of one or more switches will cause the line
voltage to drop to 0, causing the interrupt request signal , INTR received by the processor to go
to 1.
• The value of INTR is the logical OR of the requests from individual devices, that is,
INTR = INTR1 + ………+INTRn
It is customary to use the complemented form, INTR, to name the interrupt-request signal on the
common line, because this signal is active when in the low-voltage state.

Figure: An equivalent circuit for an open-drain bus used to implement a common interrupt-request line

• The figure shows that special gates known as open-collector (for bipolar circuits) or open-drain
(for MOS circuits) are used to drive the INTR line. The output of an open-collector or an open-
drain gate is equivalent to a switch to ground that is open when the gate’s input is in the 0 state
and closed when it is in the 1 state. Resistor R is called a pull-up resistor because it pulls the line
voltage up to the high-voltage state when the switches are open.

Enabling and Disabling Interrupts

• The facilities provided in a computer must give the programmer complete control over the events
that take place during program execution. The arrival of an interrupt request from an external
device causes the processor to suspend the execution of one program and start the execution of
another.
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• Because interrupts can arrive at any time, they may alter the sequence of events from the
envisaged by the programmer. Hence, the interruption of program execution must be carefully
controlled.
• Let us consider in detail the specific case of a single interrupt request from one device. When a
device activates the interrupt-request signal, it keeps this signal activated until it learns that the
processor has accepted its request.
• This means that the interrupt-request signal will be active during execution of the interrupt-
service routine, perhaps until an instruction is reached that accesses the device .
• This activated signal, if not deactivated, may lead to successive interruptions, causing the system
to enter into an infinite loop.
To prevent the system from entering into an infinite-loop because of interrupt, there are 3
possibilities:
First Option

• The first possibility is to have the processor hardware ignore the interrupt-request line until the
execution of the first instruction of the interrupt-service routine has been completed.
• Then, by using an Interrupt-disable instruction as the first instruction in the interrupt-service
routine, the programmer can ensure that no further interruptions will occur until an Interrupt-
enable instruction is executed.
• Typically, the Interrupt-enable instruction will be the last instruction in the interrupt-service
routine before the Return-from-interrupt instruction. The processor must guarantee that
execution of the Return-from-interrupt instruction is completed before further interruption can
occur.

Second Option

• The second option is to have the processor automatically disable interrupts before starting the
execution of the ISR.
• After saving the contents of the PC and the processor status register (PS) on the stack, the
processor performs the equivalent of executing an Interrupt-disable instruction. It is often the
case that one bit in the PS register, called Interrupt-enable, indicates whether interrupts are
enabled.

Third option

• In the third option, the processor has a special interrupt-request line for which the interrupt-
handling circuit responds only to the leading edge of the signal. Such a line is said to be edge-
triggered. Processor will receive only one request hence there will not be multiple interruption.

Summary:
Sequence of events involved in handling an interrupt-request from a single device is as follows:
1. The device raises an interrupt request.
2. The processor interrupts the program currently being executed.
3. Interrupts are disabled by changing the control bits in the PS (except in the case of edge-triggered
interrupts).
4. The device is informed that its request has been recognized, and in response, it deactivates the
interrupt-request signal.
5. The action requested by the interrupt is performed by the interrupt-service routine.
6. Interrupts are enabled and execution of the interrupted program is resumed.
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Handling Multiple Devices

• An I/O device requests a service by activating a bus line called interrupt request. There may be
more than one I/O devices in a system which request service. Since these devices operate
independently, there is no specific order in which they generate interrupts. In another case,
several devices may send request at the same time.
.
When several devices requests interrupt at the same time, it raises some questions. They are
• How can the processor recognize the device requesting an interrupt?
• How can the processor obtain the starting address of the appropriate routine?
• Should a device be allowed to interrupt the processor while another interrupt is being serviced?
• How should two or more simultaneous interrupt requests be handled?
• Information needed to determine whether a device is requesting an interrupt is available in its
status-register. When a device raises an interrupt-request, it sets IRQ bit to 1 in its status-register.
• KIRQ and DIRQ are the interrupt-request bits for keyboard & display. Simplest way to identify
interrupting device is to have ISR poll all I/O devices connected to bus.
• The first device encountered with its IRQ bit set is the device that should be serviced. After
servicing this device, next requests may be serviced.

Figure 6: A program that reads one line from the keyboard, stores it in memory buffer, and echoes it
back to the display
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Vectored Interrupts

• To reduce the polling process time, a device requesting an interrupt may identify itself directly to
the processor. Now, the processor can immediately start executing the corresponding ISR. Such
interrupts are called as vectored interrupts. A device requesting an interrupt can identify itself
by sending a special code to the processor over the bus.
• This enables the processor to identify individual devices even if they share a single interrupt-
request line. The code supplied by the device may represent the starting address of the interrupt-
service routine for that device.
• The code length is typically in the range of 4 to 8 bits. The remainder of the address is supplied
by the processor based on the area in its memory where the addresses for interrupt-service
routines are located.
• The address stored at the location pointed to by interrupting-device is called the interrupt-vector.
The processor reads this address, called the interrupt vector, and loads it into PC then executes
appropriate ISR. Interrupting-device must wait to put data on bus only when processor is ready
to receive it.
• When processor is ready to receive interrupt-vector code, it activates INTA line. I/O device
responds by sending its interrupt-vector code & turning off the INTR signal.

Interrupt Nesting

• Computer keeps track of the time of the day using real-time clock. Device sends IR to processor
at regular intervals to update time in seconds, minutes.
• For some device, a long delay is responding to an interrupt request may cause error in the
operation of computer. Such interrupts are acknowledge and serviced even though processor is
executing an interrupt service routine for another device system of interrupts that allows an
interrupt service routine to be implemented is known as nested interrupts.

Multiple Priority Scheme:

• In multiple level priority schemes, we assign a priority level to the processor that can be changed
under program control.
• The priority level of the processor is the priority of the program that is currently being executed.
• The processor accepts interrupts only from devices that have priorities higher than its own.
• At the time of execution of an ISR for some device is started, the priority of the processor is
raised to that of the device.
• The action disables interrupts from devices at the same level of priority or lower.

Privileged Instruction:

• The processor priority is usually encoded in a few bits of the Processor Status word. It can also
be changed by program instruction & then it is writing into PS. These instructions are called
privileged instruction.
• This can be executed only when the processor is in supervisor mode. The processor is in
supervisor mode only when executing OS routines. It switches to the user mode before
beginning to execute application program.

Privileged Exception:

• Processor will have privileged instructions to run in supervisor mode.

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• User program cannot accidently or intentionally change the priority of the processor & disrupts
the system operation. An attempt to execute a privileged instruction while in user mode, leads to
a special type of interrupt called the privileged exception.
• Each of the interrupt request line is assigned a different priority level. Interrupt request received
over these lines are sent to a priority arbitration circuit in the processor. A request is accepted
only if it has a higher priority level than that currently assigned to the processor

Figure 7: implementation of interrupt priority using individual interrupt-request and acknowledge lines

Simultaneous Requests:
Daisy Chain:

• The interrupt request line INTR is common to all devices. The interrupt acknowledge line INTA
is connected in a daisy chain fashion such that INTA signal propagates serially through the
devices.

• When several devices raise an interrupt request, the INTR is activated & the processor responds
by setting INTA line to 1. This signal is received by device. Device1 passes the signal on to
device2 only if it does not require any service. If devices1 has a pending request for interrupt
blocks that INTA signal & proceeds to put its identification code on the data lines. Therefore, the
device that is electrically closest to the processor has the highest priority.

Figure 8: Interrupt priority schemes

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Arrangement of Priority Groups:

Here the devices are organized in groups & each group is connected at a different priority level. Within
a group, devices are connected in a daisy chain.