ELE2C02-Electronic circuits

Introduction to Digital Electronics:

The term digital is derived from digits. Any device or system which works on
digits is a digital device or system. A digital voltmeter indicates the value of
Le-Ment College of Advanced Studies-Pattambi voltage in the form of digits, e.g., 230.25v
Reading an analog instrument introduces human error and also requires more
University of Calicut
time. A digital reading is more accurate, eliminates human error and can be read
B.Sc ELECTRONICS (2019 admission onwards)
quickly.
(Complementary)-Electronics
In communication systems the initial signal waveform is always analog. To use
digital transmission, the signal waveform is sampled and the digital representation
Semester: Three
transmitted. The process of converting analog signal to digital form is also known
as digitizing. For multiple channels of transmission, Time Division Multiplexing
is used.
Digital methods have the following advantages over analog methods:
1. Digital devices work only in two states (ON or OFF). Thus their operation is
very simple and reliable.
2. Digital display is very accurate and can be read at a fast speed. Human error
is eliminated.
3. Electronic components exhibit change in behaviour due to ageing, change of
ambient temperature etc. Therefore, the behaviour of analog circuits tends to
be somewhat unpredictable. However, digital circuits are free from these
defects.
Pradeep C P ( M.Sc,,M.Phil ) 4. Digital ICs are very cheap and compact in size.
Assistant professor (Electronics)
5. Variety of digital ICs is available.
Le-Ment College Of Advanced Studies.
(Affiliated to Calicut University) 6. Power requirement of digital circuits is very low.
Pattambi 7. Digital systems have the characteristic advantage of memory. Thus
Palakkad information can be stored over a period of time. The space required for this
stage is very small. One compact disc can store information contained in
many books.

LCAS-Pattambi 1|Page
 ELE2C02-Electronic circuits

8. Digital systems have high fidelity and provide noise free operations. Octal :
9. By integrating system peripheral functions on a DSP chip, the reliability can An octal number system (base 8) is composed of eight digits (0, 1, 2, 3, 4, 5, 6, 7)
be enhanced and cost reduced. An octal number such as 2478 can be expressed in decimal equivalent by
10. When volumes are high, they can be manufactured at low cost. successive power of ‘8’.
11. The same digital system can be used with a variety of software for a number (247)8 = 2 × 82 + 4 × 81 + 7 × 80 = 16710 (decimal)
of tasks. Hexa decimal:
12. Standardisation & Repeatability Hexa decimal format :- 0,1,2,3….8,9,A,B,C,D,E,F
Number systems and Codes: A= decimal 10, B= decimal 11, …..and F= decimal 15 so on…
A number system is simply a way of representing numeric values. It uses symbols
An hexa decimal number system (base 16) is composed of 16 digits
called numerals to represent numeric quantities. Electronic and Digital systems
(0,1,2,3…..A,B,C,D,E,F)
may use a variety of different number systems, (e.g. Decimal, Hexadecimal,
An hexa decimal number such as 2D5 can be expressed in decimal equivalent by
Octal, and Binary).
successive power of ‘16’.
The table below describes four number system, their base and their distinct
(2D5)16 = 2 × 162 + D× 161 + 5 × 160 = 72510 (decimal).
symbols:
BCD (Binary coded decimal)
Number Codes Used in Digital Electronics:
Binary-coded decimal (BCD) is used to represent each digit of a decimal number
Number system Base / radix Distinct Symbols as a 4-bit binary number.
Binary 2 (1011)2 0 or 1 For example, the number 15010 in BCD is expressed as;
Octal 8 (2047)8 0 to 7 1 5 0 = 15010 0001 0101 0000) (BCD)
Decimal 10 (7901)10 0 to 9
Hexa decimal 16 (5B0F)16 0 to F
0001 0101 0000
Binary: Conversion of numbers:
A binary number is composed of two binary digits, 0 and 1, and the number  Binary Decimal
system have base “2”.  Decimal Octal
Which are also called bits (e.g., 0 = low voltage, 1= high voltage).
 Binary Octal
A binary number such as (11100)2 can be expressed in decimal equivalent by
 Binary Hexadecimal
successive powers of ‘2’:
 Decimal Hexadecimal
(11100)2 = 1 × 24 + 1 × 23 + 1 × 22 + 0 × 21 + 0 × 20 = 2810 (decimal)
 Octal Hexadecimal

LCAS-Pattambi 2|Page
 ELE2C02-Electronic circuits

Conversion table: Binary to Decimal (Fractional number)

The fractional binary numbers to the right of the binary point, the weight of each
Hex Decimal Octal Binary
digit becomes more negative giving: 2 -1, 2-2, 2-3, 2-4, and so on. The weighted
0 0 0 0
1 1 1 1 values of each bit position become;
2 2 2 10
…24, 23,22,21,20, 2-1, 2-2, 2-3, 2-4….. So on
3 3 3 11
4 4 4 100
5 5 5 101
6 6 6 110
7 7 7 111
8 8 10 1000
9 9 11 1001
A 10 12 1010
B 11 13 1011
C 12 14 1100
D 13 15 1101
E 14 16 1110
F 15 17 1111
Binary Fractions Example.
Binary - Decimal
Now let’s suppose we have the following binary number of: 1101.01112, what will
Binary Number − 111012
be its decimal number equivalent.
Calculating Decimal Equivalent
1101.01112 = (1×23) + (1×22) + (0×21) + (1×20) +
Step Binary Decimal Number
Number (0×2-1) + (1×2-2) + (1×2-3) + (1×2-4)
Step 1 111012 ((1 × 24) + (1 × 23) + (1 × 22) + (0 × 21) + = 8 + 4 + 0 + 1 + 0 + 1/4 + 1/8 + 1/16
(1 × 20))10
Step 2 111012 (16 + 8 + 4 + 0 + 1)10 = 8 + 4 + 0 + 1 + 0 + 0.25 + 0.125 + 0.0625 = 13.437510
Step 3 111012 2910 Hence the decimal equivalent number of 1101.01112 is given as: 13.437510
Binary Number − 111012 = Decimal Number − 2910

LCAS-Pattambi 3|Page
 ELE2C02-Electronic circuits

Decimal to Binary; Note that you can add any number of 0’s in leftmost bit (or in most significant bit)
Short Division by Two with Remainder for integer part and add any number of 0’s in rightmost bit (or in least significant
Convert decimal number 25 into binary number, since given number is decimal bit) for fraction part for completing the group of 3 bit.
integer number, so by using above algorithm performing short division by 2 with
Example-1 − Convert binary number 1010111100 into octal number. Since there
remainder.
is no binary point here and no fractional part.

Thus the Binary Equivalent of 2510 = 110012 So the octal equivalent of the Binary number is;

= (1010111100)2
Decimal to Binary conversion (fractional number)
To convert fraction to binary, start with the fraction in question and multiply it
= (001 010 111 100)2

by 2 keeping notice of the resulting integer and fractional part. Continue multiplying by 2 = (1 2 7 4)8
until you get a resulting fractional part equal to zero. Then just write out the integer parts = (1274)8
from the results of each multiplication.
Here is an example of such conversion using the fraction 0.37510.
Binary to Octal conversion (Fractional conversion):
0.375 x 2 = 0.750
0.75 x 2 = 1.50
Example-2 Convert binary number (0110 011.1011)2 into octal number. Since

0.50 x 2 = 1.00 there is binary point here and fractional part. So,
Thus the Binary Equivalent of 0.37510 = .0112
Decimal to binary fraction example: - Binary equivalent of 12.37510 = 1100.0112

Binary to Octal conversion:

There are only 8 digits (from 0 to 7) in octal number system, so we can represent
any digit of octal number system using only 3 bit.

LCAS-Pattambi 4|Page
 ELE2C02-Electronic circuits

Therefore, set the Binary into group of three bits, thus the octal form of binary is. Hexa to Binary conversion ;

= (0110 011.1011)2 To convert a hexadecimal number to a binary number, convert each hexadecimal
= (0 110 011. 101 1 )2 digit to its four digit equivalent. For example, consider the hexadecimal number
= (110 011.101 100)2 (9AF)16 which is converted into a binary digit.
= (6 3.5 4)8
= (63.54)8

Octal to Binary conversion with Fractional

Converting the octal number (35.346)8 to its equivalent binary number
Therefore the equivalent binary number is (1001 1010 1111)2.

Decimal to Octal conversion with fraction:

For converting the decimal number into an octal number, the octal dabbles
method is used. In the octal double method, the integer octal
number is divided by the digit 8. And for converting the fractional decimal
number into an octal number, it is multiplied by the digit 8 and record the carry.
Thus the required binary number is (011 101. 011 100 110) 2.
When these carry read down, it gives the fractional octal number.
Binary to Hexa conversion.
To convert the binary number into its equivalent hexadecimal number rewrite the Example: Consider the conversion of the decimal number (123.53)10. The

binary number of the sets of four digits and then place the hexadecimal digit in conversion of integer part is shown below.

front of each four digit set of a binary number as explained by the following
number.

Thus the equivalent hexadecimal number of Binary is (E8D6)16.

LCAS-Pattambi 5|Page
 ELE2C02-Electronic circuits

And the fraction part

Thus the octal number of Decimal (123.53)10 is (173.4172)8.

Octal to decimal conversion with fraction:
In octal number system, each digit position has the weight
eight regarding power eight shown in the figure below

Thus the Hex equivalent of decimal (374.37)10 is (176.5EB8)16

Hexa decimal to Decimal conversion:

Convert Hexadecimal (54.D2)16 to Decimal

.
Example – Consider the octal number (354.42)8 into its equivalent decimal
number. The integer part 354 converts to octal shown below.

10

And the fractional parts 0.42 convert to octal

The decimal equivalent of (354.42)8 is (236.53125)10. Decimal Equivalent of (54.D2)16 = (84.8203125)10

Decimal to Hexa conversion:
Octal to Hexa conversion:
The conversion of the given decimal number into hexadecimal number requires
Convert the octal number (536)8 to hexadecimal number:
the application of hex-dabble method that is the number has to divide the given
number by 16. Convert 536(octal) into its binary equivalent we get
Consider the conversion of the decimal number (374.37)10 into its hexadecimal (536)8 = (101) (011) (110) = (101011110)2
Equivalent number. Now forming the group of 4 binary bits to obtain its hexadecimal equivalent,

LCAS-Pattambi 6|Page
 ELE2C02-Electronic circuits

(101011110)2= (0001) (0101) (1110) Then we can use a single bit to identify the sign of a signed binary number as
= (15E)16 being positive or negative in value.
For signed binary numbers the most significant bit (MSB) is used as the sign bit.
So the hexadecimal number of (536)8 is (15E)16.
If the sign bit is “0”, this means the number is positive in value. If the sign bit is
Hexa to octal conversion:
“1”, then the number is negative in value. The remaining bits in the number are
Convert (15E)16 into octal equivalent: used to represent the magnitude of the binary number in the usual unsigned binary
Convert 15E (Hex) into its binary equivalent; ie : number format way.
(15E)16 = (0001) (0101) (1110) = (000101011110)2 Positive Signed Binary Numbers and Negative Signed Binary Numbers
Now forming the group of 3 binary bits to obtain its Octal equivalent:

(000101011110)2 = (000) (101) (011) (110)

= (0536)8 otherwise eliminate the ‘0’,so it become (536)8
BCD conversion:
If you want to convert any number system to BCD, first convert the number into
Decimal equivalent and convert to respective BCD The disadvantage here is that whereas before we had a full range n-bit unsigned
Signed and unsigned Binary Numbers: binary number, we now have an n-1 bit signed binary number giving a reduced
However, in digital circuits there is no provision made to put a plus or even a range of digits from:
minus sign to a number, since digital systems operate with binary numbers that are -2(n-1) to +2(n-1)
represented in terms of ‘0’sand “1’s. When used together in microelectronics,
Example: If the four bit Binary number: 11112 ; the MSB bit ‘1’indicate the
these “1’s and “0’s, called a bit (being a contraction of Binary digit), fall into number is Negative.
several range sizes of numbers which are referred to by common names, such as Thus the decimal value become: 1111 = - (1x22+1x21+1x20) = -7
a byte or a word. 1’s and 2’s complements:
Mathematical numbers are generally made up of a sign and a value (magnitude) in Complements are used in digital computers in order to simply the subtraction
which the sign indicates whether the number is positive, (+) or negative, (–) with operation and for the logical manipulations. For the Binary number (base-2)
the value indicating the size of the number, for example 23, +156 or -274. system, there are two types of complements: 1’s complement and 2’s complement.
We know that binary digits, or bits only have two values, either a “1” or a “0” and
1’s Complement of a Binary Number:
conveniently for us, a sign also has only two values, being a “+” or a “–“.
The algorithm to convert a binary number into 1’s complement. To get 1’s
complement of a binary number, simply invert the given number.

LCAS-Pattambi 7|Page
 ELE2C02-Electronic circuits

Example: 1’s complement of: 1010102 is 0101012 OR gate:

2’s Complement of a Binary Number:

The algorithm to convert a binary number into 2’s complement. To get 2’s
complement of a binary number, simply invert the given number and add 1 to the
least significant bit (LSB) of given result.

Example: 2’s complement of 110011 become

First convert the binary into 1’s complement. Ie: 001100
Then add ‘1’ to the LSB of 1’s complement form ie : 001101
AND gate:
Logic gates

Digital electronic circuits that operates on One or more input signals to produce an
output.
Logic gates contain two states which are ON or OFF , The ON means Logic “1”
and OFF means Logic “0” .
“Boolean algebra specifies the relationship between Boolean Variables which is
used to design combinational logic circuits using Logic gates”.
“The truth table used to represent the Boolean expression of a logic gate function
called “Truth table”. NOT gate :

Basic logic gates:

3 types : OR, AND, NOT

Universal gates :

2 types : NAND , NOR

“ NAND or NOR can be used to design all basic gates “

LCAS-Pattambi 8|Page
 ELE2C02-Electronic circuits

UNIVERSAL GATES Uses :

NAND gate:
1. Digital watches, clock
2. Computer, calculators
3. All types of Digital processors.
Universal properties of NAND and NOR
Basic gates using NAND gate

NOR gate :

Basic gates using NOR gate

EX-OR gate :
The Exclusive OR gate gives HIGH output when the inputs are not at
equal logic level. The Exclusive OR operation is widely used in digital
circuit. It is also called as XOR.

LCAS-Pattambi 9|Page
 ELE2C02-Electronic circuits

Boolean laws:

Commutative Law

A . B = B . A The order in which two variables are AND’ed makes no

difference.

A + B = B + A The order in which two variables are OR’ed makes no

difference.

Distributive Law

A(B + C) = A.B + A.C (OR Distributive Law)

A + (B.C) = (A + B).(A + C) (AND Distributive Law)

Table showing verification of the De Morgan's first theorem
Associative Law

A + (B + C) = (A + B) + C = A + B + C (OR Associate Law)

A(B.C) = (A.B)C = A . B . C (AND Associate Law)

De morgan’s theorem

De Morgan has suggested two theorems which are extremely useful in Boolean
algebra. The two theorems are discussed below. Theorem 2

Theorem 1

 The LHS of this theorem represents a NOR gate with inputs A and B,
 The left hand side (LHS) of this theorem represents a NAND gate with
whereas the RHS represents an AND gate with inverted inputs.
inputs A and B, whereas the right hand side (RHS) of the theorem represents
an OR gate with inverted inputs.  This AND gate is called as Bubbled AND.

 This OR gate is called as Bubbled OR.

LCAS-Pattambi 10 | P a g e
 ELE2C02-Electronic circuits

UNIT-2
Standard representation of logic functions (SOP and POS),
Representation of Boolean expression can be primarily done in two ways. They
are as follows:
1. Sum of Products (SOP) form
2. Product of Sums (POS) form
If the number of input variables is n, then the total number of combinations in
Boolean algebra is 2n
If the input variable (let A) value is :

 Zero (0) – a is LOW -It should be represented as A’ (Complement of A)

 One (1) – a is HIGH -It should be represented as A
Table showing verification of the De Morgan's second theorem −
In Boolean logic,

AND is represented as '.'

A AND B is written as 'A.B'
OR is represented as '+'
A OR B is written as 'A+B'
For example, Considering number of input variables =3, Say A, B and C.
Total number of combinations are: 23=8.
A B C
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 1

LCAS-Pattambi 11 | P a g e
 ELE2C02-Electronic circuits

Sum of Products (SOP): Product of Sums (POS):

It is one of the ways of writing a Boolean expression. As the name suggests, it is As the name suggests, it is formed by multiplying(AND operation) the sum terms.
formed by adding (OR operation) the product terms. These product terms are also These sum terms are also called as ‘max-terms’. Max-terms are represented with
called as ‘min-terms’. Min-terms are represented with ‘m’, they are the ‘M’, they are the sum (OR operation) of Boolean variables either in normal form
product (AND operation) of Boolean variables either in normal form or or complemented form.
complemented form. Therefore, POS is product of maxterms and is represented as:
Therefore, SOP is sum of minterms and is represented as: F in SOP = ΠM(1, 2) Here, F is product of maxterm1 and maxterm2.
F in SOP =Σ m(0, 3) A=0, B=1, C=0 Maxterm is A'+B+C'
Here, F is sum of minterm0 and minterm3. A=1, B=1, C=1 Maxterm is A+B+C
For Example: Consider a function X, whose truth table is as follows:
A=0, B=0, C=0 Minterm is A'.B'.C' A B C X
A=1, B=0, C=1 Minterm is A.B'.C 0 0 0 0
0 0 1 1
Consider a function X, whose truth table is as follows: 0 1 0 0
A B C X 0 1 1 1
0 0 0 0 1 0 0 0
0 0 1 1 1 0 1 0
0 1 0 0 1 1 0 1
0 1 1 1 1 1 1 0
1 0 0 0
1 0 1 0
1 1 0 1 The function X can be written in POS form by multiplying all the max-terms
1 1 1 0
when X is LOW(0).
The function X can be written in SOP form by adding all the min-terms when X is
While writing POS, the following convention is to be followed:
HIGH(1).
If variable A is Low(0) - A
While writing SOP, the following convention is to be followed:
A is High(1) - A'
If variable A is Low (0) - A'
X (SOP) = ΠM(0, 2, 4, 5, 7)
A is High (1) - A
= (A+B+C).(A+B'+C).(A'+B+C).(A'+B+C').(A'+B'+C')
X (SOP) = Σm (1, 3, 6)
= A’.B’.C + A’.B.C + A.B.C’

LCAS-Pattambi 12 | P a g e
 ELE2C02-Electronic circuits

Difference between SOP and POS : 2 Variable K-Map

The number of cells in 2 variable K-map is four, since the number of variables is
s.no. SOP POS
two. The following figure shows 2 variable K-Map.
A way of representing boolean A way of representing boolean
1 expressions as sum of product terms. expressions as product of sum terms.

SOP uses minterms. Minterm is POS uses maxterms. Maxterm is

2 product of boolean variables either in sum of boolean variables either in
normal form or complemented form. normal form or complemented form.

It is sum of minterms. Minterms are It is product of maxterms. Maxterms

3 represented as ‘m’ are represented as ‘M’
 There is only one possibility of grouping 4 adjacent min terms.
SOP is formed by considering all the POS is formed by considering all the
4
minterms, whose output is HIGH(1) maxterms, whose output is LOW(0)  The possible combinations of grouping 2 adjacent min terms are {(m0, m1),
While writing minterms for SOP, While writing maxterms for POS, (m2, m3), (m0, m2) and (m1, m3)}.
input with value 1 is considered as input with value 1 is considered as
5 the variable itself and input with the complement and input with 3 Variable K-Map
value 0 is considered as complement value 0 is considered as the variable The number of cells in 3 variable K-map is eight, since the number of variables is
of the input. itself.
three. The following figure shows 3 variable K-Map

Karnaugh Map (K-MAP)

Boolean functions are generally solved using Boolean postulates and theorems. It
is a time consuming process and we have to re-write the simplified expressions
after each step. To overcome this difficulty; Karnaugh introduced a method for
simplification of Boolean functions in an easy way. This method is known as
Karnaugh map method or K-map method. It is a graphical method, which consists  There is only one possibility of grouping 8 adjacent min terms.
of 2 cells for ‘n’ variables. The adjacent cells are differed only in single bit
n
 The possible combinations of grouping 4 adjacent min terms are {(m0, m1,
position.
m3, m2), (m4, m5, m7, m6), (m0, m1, m4, m5), (m1, m3, m5, m7), (m3, m2, m7,
m6) and (m2, m0, m6, m4)}.

LCAS-Pattambi 13 | P a g e
 ELE2C02-Electronic circuits

 The possible combinations of grouping 2 adjacent min terms are {(m0, m1), Solving Boolean expression Using K-map
(m1, m3), (m3, m2), (m2, m0), (m4, m5), (m5, m7), (m7, m6), (m6, m4), (m0, Let us simplify the following Boolean function, F= Σm {W, X, Y, Z} = WX’Y’ +
m4), (m1, m5), (m3, m7) and (m2, m6)}. WY + W’YZ’ using K-map.
The given Boolean function is in sum of products form. It is having 4 variables
 If x=0, then 3 variable K-map becomes 2 variable K-map.
W, X, Y & Z. So, we require 4 variable K-map. The 4 variable K-map with ones
4 Variable K-Map
corresponding to the given product terms is shown in the following figure.
The number of cells in 4 variable K-map is sixteen, since the number of variables
is four. The following figure shows 4 variable K-Map.

Here, 1s are placed in the following cells of K-map.

 The cells, which are common to the intersection of Row 4 and columns 1 &
2 are corresponding to the product term, WX’Y’.
 The cells, which are common to the intersection of Rows 3 & 4 and columns
 There is only one possibility of grouping 16 adjacent min terms. 3 & 4 are corresponding to the product term, WY.

 Let R1, R2, R3 and R4 represents the min terms of first row, second row,  The cells, which are common to the intersection of Rows 1 & 2 and column
third row and fourth row respectively. Similarly, C1, C2, C3 and 4 are corresponding to the product term, W’YZ’.

C4 represents the min terms of first column, second column, third column There are no possibilities of grouping either 16 adjacent ones or 8 adjacent ones.
and fourth column respectively. The possible combinations of grouping 8 There are three possibilities of grouping 4 adjacent ones. After these three
adjacent min terms are {(R1, R2), (R2, R3), (R3, R4), (R4, R1), (C1, C2), (C2, groupings, there is no single one left as ungrouped. So, we no need to check for
C3), (C3, C4), (C4, C1)}. grouping of 2 adjacent ones. The 4 variable K-map with these three groupings is
shown in the following figure.
 If w=0, then 4 variable K-map becomes 3 variable K-map.

LCAS-Pattambi 14 | P a g e
 ELE2C02-Electronic circuits

There are no possibilities of grouping either 8 adjacent zeroes or 4 adjacent

zeroes. There are three possibilities of grouping 2 adjacent zeroes. After these
Here, we got three prime implicants WX’, WY & YZ’. All these prime three groupings, there is no single zero left as ungrouped. The 3 variable K-
implicants are essential because of following reasons. map with these three groupings is shown in the following figure.

 Two ones (m8 & m9) of fourth row grouping are not covered by any other
groupings. Only fourth row grouping covers those two ones.

 Single one (m15) of square shape grouping is not covered by any other
groupings. Only the square shape grouping covers that one.

 Two ones (m2 & m6) of fourth column grouping are not covered by any
other groupings. Only fourth column grouping covers those two ones.
Here, we got three prime implicants X + Y, Y + Z & Z + X. All these prime
Therefore, the simplified Boolean function is
implicants are essential because one zero in each grouping is not covered by any
F= WX’ + WY + YZ’ other groupings except with their individual groupings.

Example Therefore, the simplified Boolean function is

F = X+Y .Y+Z .Z+X

Let us simplify the following Boolean function,
F(X, Y, Z) = ∏M (0, 1, 2, 4) using K-map. Question:
The given Boolean function is in product of Max terms form. It is having 3 Solve the Boolean expression using K-map
variables X, Y & Z. So, we require 3 variable K-map. The given Max terms are 1. F(P,Q,R,S)= Σm (2,6,8,9,10,12,13,14)
2. F(A,B,C,D)= ΠM (1,3,5,7,8,9,10,11)
M0, M1, M2 & M4. The 3 variable K-map with zeroes corresponding to the given
3. F(X,Y,Z) = Σm (0,2,4,6)
Max terms is shown in the following figure. 4. F(M,N,O) = ΠM (1,3,5,7)

LCAS-Pattambi 15 | P a g e
 ELE2C02-Electronic circuits

ADDERS AND SUBTACTORS: These are the least possible single-bit combinations. But the result for 1+1 is 10,
the sum result must be re-written as a 2-bit output. Thus, the equations can be
Adders and subtractors are digital logic circuit in electronics that implements
written as
addition and subtraction of numbers. In many computers and other types of 0+0 = 00
processors, these circuit logics are used to calculate addresses, similar operations 0+1 = 01
1+0 = 01
and table indices in the ALU and also in other parts of the processors. These can
1+1 = 10
be built for many numerical representations like excess-3 or binary coded decimal. Now it has been cleared that 1-bit adder can be easily implemented with the help
of the XOR Gate for the output ‘SUM’ and an AND Gate for the ‘Carry’.
Adders are classified into two types: half adder and full adder. The half adder
Symbol Truth Table
circuit has two inputs: A and B, which add two input digits and generate a carry
B A SUM CARRY
and sum. The full adder circuit has three inputs: A and C, which add the three
input numbers and generate a carry and sum. 0 0 0 0

0 1 1 0
The subtractor circuit uses binary numbers (0,1) for the subtraction. The circuit of
1 0 1 0
the half subtractor can be built with two logic gates namely NAND and EX-OR
1 1 0 1
gates. This circuit gives two elements such as the difference as well as the borrow.

Half adder: Half Adder Truth Table with Carry-Out

A half adder is a logical circuit that performs a addition operation on two binary From the truth table of the half adder we can see that the SUM (S) output is the
digits. The half adder produces a sum and a carry bit.
result of the Exclusive-OR gate and the Carry-out (Cout) is the result of
the AND gate. Then the Boolean expression for a half adder is as follows.

For the SUM bit: SUM = A XOR B = A ⊕ B

For the CARRY bit: CARRY = A AND B = A.B

Full adder :
0+0 = 0
0+1 = 1 This adder is difficult to implement than a half-adder. The difference between a
1+0 = 1
half-adder and a full-adder is that the full-adder has three inputs and two outputs,
1+1 = 10
whereas half adder has only two inputs and two outputs. The first two inputs are A
and B and the third input is an input carry as C-in

LCAS-Pattambi 16 | P a g e
 ELE2C02-Electronic circuits

Decoders and encoders:

It is a combinational circuit that converts n lines of input into 2n lines of output.

Let’s take an example of 3-to-8 line decoder
The implementation may be:
D0 = X’ Y’ Z’
the full adder circuit is basically two half adders connected together, the truth
D1 = X’ Y’ Z
table for the full adder includes an additional column to take into account
the Carry-in, CIN input as well as the summed output, S and the Carry- D2 = X’ Y Z’

out, COUT bit. D3 = X’ Y Z

D4 = X Y’ Z’
D5 = X Y’ Z
Full Adder Truth Table with Carry
D6 = X Y Z’
Symbol Truth Table
C-in B A Sum C-out D7 = X Y Z
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Then the Boolean expression for a full adder is as follows.

For the SUM (S) bit:

SUM = (A XOR B) XOR Cin = (A ⊕ B) ⊕ Cin

For the CARRY-OUT (Cout) bit:

CARRY- OUT = A AND B OR Cin(A XOR B) = A.B + Cin(A ⊕ B)

LCAS-Pattambi 17 | P a g e
 ELE2C02-Electronic circuits

X Y Z D0 D1 D2 D3 D4 D5 D6 D7 Implementation of 8:3 encoder

0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0 Q0 = D1 + D3 + D5 + D7
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
Q1 = D2 + D3 + D6 + D7
1 0 0 0 0 0 0 1 0 0 0
Q2 = D4 + D5 + D6 + D7
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1

Encoders:

An encoder is a combinational circuit that converts binary information in the form

of a 2N input lines into N output lines.

One limitation of this encoder is that only one input can be active at any given
time. If more than one input is active, then the output is undefined. For example, if
D6 and D3 are both active, then, our output would be 111 which is the output for
D7. To overcome this, we use Priority Encoders.

Seven segment Display Decoder

The truth table for implementing Octal to Binary or 8:3 Encoders
A Display Decoder is a combinational circuit which decodes and n-bit input value
D7 D6 D5 D4 D3 D2 D1 D0 Q2 Q1 Q0 into a number of output lines to drive a display
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 0 0 0 1 A Digital Decoder IC, is a device which converts one digital format into another
0 0 0 0 0 1 0 0 0 1 0
and one of the most commonly used devices for doing this is called the Binary
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 0
Coded Decimal (BCD) to 7-Segment Display Decoder.
0 0 1 0 0 0 0 0 1 0 1
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1

LCAS-Pattambi 18 | P a g e
 ELE2C02-Electronic circuits

2. The Common Anode Display (CAD) – In the common anode display, all
the anode connections of the LED’s are joined together to logic “1” and the
individual segments are illuminated by connecting the individual Cathode
terminals to a “LOW”, logic “0” signal.

Common Cathode and Common Anode Format

7-segment displays consist of seven individual coloured LED’s (called the

segments), within one single display package. In order to produce the required
numbers or HEX characters from 0 to 9 and A to F respectively, on the display the
correct combination of LED segments need to be illuminated and BCD to 7-
segment Display Decoders such as the 74LS47

A standard 7-segment LED display generally has eight (8) input connections, one
for each LED segment and one that acts as a common terminal or connection for
all the internal display segments. Some single displays have also have an
7-Segment Display Format
additional input pin to display a decimal point in their lower right or left hand
corner.

So in order to display the number “3” for example,

In electronics there are two important types of 7-segment LED digital display.
segments a, b, c, d and g would need to be illuminated. If we wanted to display a
1. The Common Cathode Display (CCD) – In the common cathode different number or letter then a different set of segments would need to be
display, all the cathode connections of the LED’s are joined together to illuminated. Then for a 7-segment display, we can produce a truth table giving the
logic “0” or ground. The individual segments are illuminated by application
of a “HIGH”, logic “1” signal to the individual Anode terminals.

LCAS-Pattambi 19 | P a g e
 ELE2C02-Electronic circuits

segments that need to be illuminated in order to produce the required character as Binary Coded Decimal
shown below. Binary Coded Decimal (BCD or “8421” BCD) numbers are made up using just 4
data bits (a nibble or half a byte) similar to the Hexadecimal numbers we saw in
Individual Segments display Individual segments display
the binary tutorial, but unlike hexadecimal numbers that range in full
a b c d e f g a b c d e f g
from 0 through to F, BCD numbers only range from 0 to 9, with the binary
× × × × × × 0 × × × × × × × 8
number patterns of 1010 through to 1111 (A to F) being invalid inputs for this
× × 1 × × × × × × 9
type of display and so are not used as shown below.
× × × × × 2 × × × × × × a
× × × × × 3 × × × × × b Decimal Binary pattern BCD Decimal Binary pattern BCD

× × × × 4 × × × × c 8 4 2 1 8 4 2 1

× × × × × 5 × × × × × d 0 0 0 0 0 0 8 1 0 0 0 8

× × × × × × 6 × × × × × e 1 0 0 0 1 1 9 1 0 0 1 9
× × × 7 × × × × f 2 0 0 1 0 2 10 1 0 1 0 Invalid
3 0 0 1 1 3 11 1 0 1 1 Invalid

Truth Table for a 7-segment display 4 0 1 0 0 4 12 1 1 0 0 Invalid

5 0 1 0 1 5 13 1 1 0 1 Invalid
6 0 1 1 0 6 14 1 1 1 0 Invalid
7 0 1 1 1 7 15 1 1 1 1 Invalid

It can be seen that to display any single digit number from 0 to 9 in binary or
letters from A to F in hexadecimal, we would require seven separate segment BCD to 7-Segment Display Decoders
connections plus one additional connection for the LED’s “common” connection.
A binary coded decimal (BCD) to 7-segment display decoder such as the TTL
Also as the segments are basically a standard light emitting diode, the driving
74LS47 or 74LS48, have 4 BCD inputs and 7 output lines, one for each LED
circuit would need to produce up to 20mA of current to illuminate each individual
segment. This allows a smaller 4-bit binary number (half a byte) to be used to
segment and to display the number “8”, all seven segments would need to be lit
display all the denary numbers from 0 to 9 and by adding two displays together; a
resulting a total current of nearly 140mA, (8 x 20mA).
full range of numbers from 00 to 99 can be displayed with just a single byte of
eight data bits.

LCAS-Pattambi 20 | P a g e
 ELE2C02-Electronic circuits

BCD to 7-Segment Decoder the maximum current flow. There are different display decoders and drivers
available for the different types of available displays, either LED or LCD. For
example, the 74LS48 for common-cathode LED types, the 74LS47 for common-
anode LED types, or the CMOS CD4543 for liquid crystal display (LCD) types.

Liquid crystal displays (LCD´s) have one major advantage over similar LED types
in that they consume much less power and nowadays, both LCD and LED
displays are combined together to form larger Dot-Matrix Alphanumeric type
displays which can show letters and characters as well as numbers in standard Red
The use of packed BCD allows two BCD digits to be stored within a single byte or Tri-colour outputs.
(8-bits) of data, allowing a single data byte to hold a BCD number in the range
Multiplexers and DE multiplexers:
of 00 to 99.
A multiplexer is a circuit that accept many input but give only one output, used to
An example of the 4-bit BCD input ( 0100 ) representing the number “4” is given
select and route any one of the several input signals to a signal output.
below.
Multiplexer handle two type of data that is analog and digital. For analog
Display Decoder Example No1
application, multiplexer are built of relays and transistor switches. For digital
application, they are built from standard logic gates.

The multiplexer used for digital applications, also called digital multiplexer, is a
circuit with many input but only one output. By applying control signals, we can
steer any input to the output. Few types of multiplexer are 2-to-1, 4-to-1, 8-to-1,
16-to-1 multiplexer.

In practice current limiting resistors of about 150Ω to 220Ω would be connected

in series between the decoder/driver chip and each LED display segment to limit

LCAS-Pattambi 21 | P a g e
 ELE2C02-Electronic circuits

If the control input is changed to AB =11, all gates are disabled except the bottom
AND gate. In this case, D3 is transmitted to the output and Y = D3.
Understanding 4-to-1 Multiplexer:
The 4-to-1 multiplexer has 4 input bit, 2 control bits, and 1 output bit. The four Truth table
input bits are D0,D1,D2 and D3. only one of this is transmitted to the output y.
Data select Output
The output depends on the value of AB which is the control input. The control
A B Y
input determines which of the input data bit is transmitted to the output.
0 0 D0
For instance, as shown in fig. when AB = 00, the upper AND gate is enabled
0 1 D1
while all other AND gates are disabled. Therefore, data bit D0 is transmitted to the
1 0 D2
output, giving Y = Do.
1 1 D3

Applications of Multiplexer:
Multiplexer are used in various fields where multiple data need to be transmitted
using a single line. Following are some of the applications of multiplexers –

LCAS-Pattambi 22 | P a g e
 ELE2C02-Electronic circuits

1. Communication system – Communication system is a set of system that

enable communication like transmission system, relay and tributary station,
and communication network. The efficiency of communication system can be
increased considerably using multiplexer. Multiplexer allow the process of
transmitting different type of data such as audio, video at the same time using
a single transmission line.
2. Telephone network – In telephone network, multiple audio signals are
integrated on a single line for transmission with the help of multiplexers. In
this way, multiple audio signals can be isolated and eventually, the desire Understanding 1- to-4 Demultiplexer:
audio signals reach the intended recipients. The 1-to-4 demultiplexer has 1 input bit, 2 control bit, and 4 output bits.
3. Computer memory – Multiplexers are used to implement huge amount of
memory into the computer, at the same time reduces the number of copper
lines required to connect the memory to other parts of the computer circuit.
4. Transmission from the computer system of a satellite – Multiplexer can
be used for the transmission of data signals from the computer system of a
satellite or spacecraft to the ground system using the GPS (Global
Positioning System) satellites.

Demultiplexer:
Demultiplexer means one to many. A demultiplexer is a circuit with one input and
many output. By applying control signal, we can steer any input to the output.
Few types of demultiplexer are 1-to 2, 1-to-4, 1-to-8 and 1-to 16 demultiplexer.

The input bit is labelled as Data D. This data bit is transmitted to the data bit of
the output lines. This depends on the value of AB, the control input.

LCAS-Pattambi 23 | P a g e
 ELE2C02-Electronic circuits

When AB = 01, the upper second AND gate is enabled while other AND gates are original form of the data at the receiving end. The multiplexer and
disabled. Therefore, only data bit D is transmitted to the output, giving Y1 = Data. demultiplexer work together to carry out the process of transmission and
If D is low, Y1 is low. IF D is high,Y1 is high. The value of Y1 depends upon the reception of data in communication system.
value of D. All other outputs are in low state. 3. ALU (Arithmetic Logic Unit) – In an ALU circuit, the output of ALU can be
If the control input is changed to AB = 10, all the gates are disabled except the stored in multiple registers or storage units with the help of demultiplexer. The
third AND gate from the top. Then, D is transmitted only to the Y2 output, and Y2 output of ALU is fed as the data input to the demultiplexer. Each output of
= Data. demultiplexer is connected to multiple register which can be stored in the
Truth table : registers.

Data input Select input Outputs 4. Serial to parallel converter – A serial to parallel converter is used for

D A B Y3 Y2 Y1 Y0 reconstructing parallel data from incoming serial data stream. In this

technique, serial data from the incoming serial data stream is given as data
D 0 0 0 0 0 D
input to the demultiplexer at the regular intervals. A counter is attach to the
D 0 1 0 0 D 0
control input of the demultiplexer. This counter directs the data signal to the
D 1 0 0 D 0 0
output of the demultiplexer where these data signals are stored. When all data
D 1 1 D 0 0 0
signals have been stored, the output of the demultiplexer can be retrieved and
read out in parallel.
Applications of Demultiplexer:

1. Demultiplexer is used to connect a single source to multiple destinations. The Sequential Logic Circuits
main application area of demultiplexer is communication system where Unlike combinational Logic circuits that change state depending upon the actual
multiplexer are used. Most of the communication system are bidirectional i.e. signals being applied to their inputs at that time, Sequential Logic circuits have
they function in both ways (transmitting and receiving signals). Hence, for some form of inherent “Memory” built in.
most of the applications, the multiplexer and demultiplexer work in sync.
This means that sequential logic circuits are able to take into account their
Demultiplexer are also used for reconstruction of parallel data and ALU
previous input state as well as those actually present, a sort of “before” and “after”
circuits.
effect is involved with sequential circuits.
2. Communication System – Communication system use multiplexer to carry
multiple data like audio, video and other form of data using a single line for In other words, the output state of a “sequential logic circuit” is a function of the

transmission. This process make the transmission easier. The demultiplexer following three states, the “present input”, the “past input” and/or the “past

receive the output signals of the multiplexer and converts them back to the output”. Sequential Logic circuits remember these conditions and stay fixed in

LCAS-Pattambi 24 | P a g e
 ELE2C02-Electronic circuits

their current state until the next clock signal changes one of the states, giving SR-Latch using NOR gate.
sequential logic circuits “Memory”. This circuit has two inputs S & R and two outputs Q & Q’. The upper NOR
gate has two inputs R & complement of present state, Q’ and produces next state
Sequential logic circuits are generally termed as two state or Bistable devices
Q.
which can have their output or outputs set in one of two basic states, a logic level
Similarly, the lower NOR gate has two inputs S & present state, Q and produces
“1” or a logic level “0” and will remain “latched” (hence the name latch)
complement of next state, Q’.
indefinitely in this current state or condition until some other input trigger pulse or
signal is applied which will cause the Bistable to change its state once again. We know that a 2-input NOR gate produces an output, which is the complement
of another input when one of the input is ‘0’. Similarly, it produces ‘0’ output,
The word “Sequential” means that things happen in a “sequence”, one after
when one of the input is ‘1’.
another and in Sequential Logic circuits, the actual clock signal determines when
things will happen next. Simple sequential logic circuits can be constructed from
standard Bistable circuits such as: Flip-flops, Latches and Counters and which
themselves can be made by simply connecting together universal NAND Gates
and/or NOR Gates in a particular combinational way to produce the required
sequential circuit.

THE SR-LATCH The working of SR-Latch can be explained by its truth table of NOR gate:

A Bistable multivibrator has two stable states, as indicated by the prefix bi in its Working of SR-Latch.

name. Typically, one state is referred to as set and the other as reset .The simplest Case I : if R=1, and S= 0; which produce Q= 0, and Q’= 1 : ie Latch is
Bistable device, therefore, is known as a SET-RESET or S-R, latch. To create an RESET because Q=0.
S-R latch, we can wire two NOR gate in such a way that the output of one feeds
If we remove the input ,as R=0, and S=0 : the previous condition of Q and Q’
back to the input of another, and vice versa, like this.
sustain. Which consider as the latch is Memory state.

Case II : if R=0, and S= 1; which produce Q= 1, and Q’= 0 : ie Latch is SET

because Q=1.

If we remove the input, as R=0, and S=0 : the Latch remain in SET condition.
Which consider as the latch is Memory state.
or

LCAS-Pattambi 25 | P a g e
 ELE2C02-Electronic circuits

Case III: if R=1, and S= 1; which make a confusion in the latch ,that the out put
Q and Q’ become Toggle to either ‘0’ or ‘1’.Thus the condition is consider as
invalid and not used.

Similarly if the both inputs are ‘0’, The latch hold the previous condition of the
latch when it turned ON.

The status of SR-Latch using NOR can be realise using the table given below: This circuit is formed by adding two NAND gates to NAND based SR flip – flop.
The inputs are active high as the extra NAND gate inverts the inputs. A clock
pulse is given as input to both the extra NAND gates.

Hence the transition of the clock pulse is a key factor in functioning of this
device.

The above Clocked SR flip flop is designed using NAND gate, first of all ,the
truth table of NAND gate shows any of the input have LOW or ‘logic 0’ the
The SR-Latch using NAND has some different at which the R and S inputs of output become ‘1’.
NOR SR latch is replaced by S and R.

Before going to the detailed analysis of clocked SR flip flop, we have to go

through the realization of SR Latch. Here the realization table of SR latch using
Clocked SR Flip – Flops
NAND gate become.
Two types of clocked SR flip – flops are possible: based on NAND and based on
NOR. The circuit of clocked SR flip – flop using NAND gates is shown below

LCAS-Pattambi 26 | P a g e
 ELE2C02-Electronic circuits

Let’s discuss about clocked SR flip-flop. Realization table of Clocked SR flip-flop:

Clock S R Q Q’
0 X X MEMORY
1 0 0 MEMORY
1 0 1 0 1
1 1 0 1 0
1 1 1 NOT USED

Initially S* = (S.clk)’ and

D-type Flip-Flop
R* = (R.clk)’
One of the main disadvantages of the basic SR NAND Gate Bistable circuit is
Case 1.Consider Clock = 0 ; S* = 1 and R* = 1
that the indeterminate input condition of SET = “0” and RESET = “0” is
If S*=R*=1 the flip-flop is in memory state (from SR Latch forbidden. This state make useless in the circuit operation and it generate
realization table).
unwanted delay until the SET and RESET input change its input. But in order to
Case 2 : If clock = 1 , and S = 0, R = 0 : S* = 1 and R* = 1
prevent this from happening an inverter can be connected between the “SET” and
If S* = R* = 1 , the flip-flop remain in Memory state. the “RESET” inputs to produce another type of flip flop circuit known as a Data
Latch, Delay flip flop, D-type Bistable, D-type Flip Flop or just simply a D Flip
Case 3 : If clock =1 ,and S=0 , R= 1 ; S* = 1 and R* = 0 .
Flop as it is more generally called.
If S* = 1 and R* = 0 then Q = 0 , Q’ = 1 (Flip flop in RESET)
The D-type flip flop is constructed from a gated SR flip-flop with an inverter
Case 4 : If clock =1 ,and S=1 , R= 0 ; S* = 0 and R* = 1 . added between the S and the R inputs to allow for a single D (Data) input.

If S* = 0 and R* = 1 then Q = 1 , Q’ = 0 (Flip flop in SET) Then this single data input, labelled “D” and is used in place of the “Set” signal,

Case 5 : If clock =1 ,and S=1 , R= 1 ; S* = 0 and R* = 0 . and the inverter is used to generate the complementary “Reset” input thereby
making a level-sensitive D-type flip-flop from a level-sensitive SR-latch as now S
If S* = 0 and R* = 0 then Q and , Q’ become unpredictable and not
= D and R = not D as shown.
used.

LCAS-Pattambi 27 | P a g e
 ELE2C02-Electronic circuits

D-type Flip-Flop Circuit “set” and “reset” inputs of the flip-flop are both held at logic level “1” so it will
not change state and store whatever data was present on its output before the clock
transition occurred. In other words the output is “latched” at either logic “0” or
logic “1”.
Truth Table for the D-type Flip Flop

CLK D Q Q’ Description
0 X Q Q’ Memory no change
1 0 0 1 RESET
1 1 1 0 SET
We remember that a simple SR flip-flop requires two inputs, one to “SET” the
output and one to “RESET” the output. By connecting an inverter (NOT gate) to
the SR flip-flop we can “SET” and “RESET” the flip-flop using just one input as The JK Flip Flop
now the two input signals are complements of each other. This complement
The JK Flip-flop is similar to the SR Flip-flop but there is no change in state when
avoids the ambiguity inherent in the SR latch when both inputs are LOW, since
the J and K inputs are both LOW The basic S-R NAND flip-flop circuit has many
that state is no longer possible.
advantages and uses in sequential logic circuits but it suffers from two basic
Thus this single input is called the “DATA” input. If this data input is held HIGH switching problems.
the flip flop would be “SET” and when it is LOW the flip flop would change and
1. The Set = 0 and Reset = 0 condition (S = R = 0) must always be avoided
become “RESET”. However, this would be rather pointless since the output of the
flip flop would always change on every pulse applied to this data input. 2. If Set or Reset change state while the enable (EN) input is high the
correct latching action may not occur
To avoid this an additional input called the “CLOCK” or “ENABLE” input is
Then to overcome these two fundamental design problems with the SR flip-flop
used to isolate the data input from the flip flop’s latching circuitry after the desired
design, the JK flip Flop was developed.
data has been stored. The effect is that D input condition is only copied to the
output Q when the clock input is active. This then forms the basis of another This simple JK flip Flop is the most widely used of all the flip-flop designs and is
sequential device called a D Flip Flop. considered to be a universal flip-flop circuit. The two inputs labelled “J” and “K”
is not shortened abbreviated letters of other words, such as “S” for Set and “R” for
The “D flip flop” will store and output whatever logic level is applied to its data
Reset, but are themselves autonomous letters chosen by its inventor Jack Kilby to
terminal so long as the clock input is HIGH. Once the clock input goes LOW the
distinguish the flip-flop design from other types.

LCAS-Pattambi 28 | P a g e
 ELE2C02-Electronic circuits

The sequential operation of the JK flip flop is exactly the same as for the previous condition of S = “1” and R = “1” state to be used to produce a “toggle action” as
SR flip-flop with the same “Set” and “Reset” inputs. The difference this time is the two inputs are now interlocked.
that the “JK flip flop” has no invalid or forbidden input states of the SR Latch
If the circuit is now “SET” the J input is inhibited by the “0” status of Q through
even when S and R are both at logic “1”.
the lower NAND gate. If the circuit is “RESET” the K input is inhibited by the
The JK flip flop is basically a gated SR flip-flop with the addition of a clock input “0” status of Q through the upper NAND gate. As Q and Q are always different
circuitry that prevents the illegal or invalid output condition that can occur when we can use them to control the input. When both inputs J and K are equal to logic
both inputs S and R are equal to logic level “1”. Due to this additional clocked “1”, the JK flip flop toggles as shown in the following truth table.
input, a JK flip-flop has four possible input combinations, “logic 1”, “logic 0”,
“no change” and “toggle”. The symbol for a JK flip flop is similar to that of an SR The Truth Table for the JK Function
Bistable Latch as seen in the previous tutorial except for the addition of a clock
input.

The Basic JK Flip-flop

Then the JK flip-flop is basically an SR flip flop with feedback which enables
only one of its two input terminals, either SET or RESET to be active at any one
time thereby eliminating the invalid condition seen previously in the SR flip flop
circuit.

Also when both the J and the K inputs are at logic level “1” at the same time, and
Both the S and the R inputs of the previous SR Bistable have now been replaced
the clock input is pulsed “HIGH”, the circuit will “toggle” from its SET state to a
by two inputs called the J and K inputs, respectively after its inventor Jack Kilby.
RESET state, or visa-versa. This result in the JK flip flop acting more like a T-
Then this equates to: J = S and K = R.
type toggle flip-flop when both terminals are “HIGH”.
The two 2-input AND gates of the gated SR Bistable have now been replaced by
Although this circuit is an improvement on the clocked SR flip-flop it still suffers
two 3-input NAND gates with the third input of each gate connected to the outputs
from timing problems called “race” if the output Q changes state before the timing
at Q and Q. This cross coupling of the SR flip-flop allows the previously invalid

LCAS-Pattambi 29 | P a g e
 ELE2C02-Electronic circuits

pulse of the clock input has time to go “OFF”. To avoid this the timing pulse Truth Table of T flip – flop
period ( T ) must be kept as short as possible (high frequency). As this is
sometimes not possible with modern TTL IC’s the much improved Master-Slave
JK Flip-flop was developed.

T flip – flop
T flip – flop is also known as “Toggle Flip – flop”. To avoid the occurrence of
intermediate state in SR flip – flop, we should provide only one input to the flip –
flop called Trigger input or Toggle input (T). Then the flip – flop acts as a Toggle As mentioned earlier, T flip – flop is an edge triggered device. For example,
switch. Toggling means ‘Changing the next state output to complement of the consider a T flip – flop made of NAND SR latch as shown below.
present state output’. If the output Q = 0, then the upper NAND is in enable state and lower NAND gate
We can design the T flip – flop by making simple modifications to the JK flip – is in disable condition. This allows the trigger to pass the S inputs to make the flip
flop. The T flip – flop is a single input device and hence by connecting J and K – flop in SET state i.e. Q = 1.
inputs together and giving them with single input called T we can convert a JK If the output Q = 1, then the upper NAND is in disable state and lower NAND
flip – flop into T flip – flop. So a T flip – flop is sometimes called as single input gate is in enable condition. This allows the trigger to pass the R inputs to make the
JK flip – flop. flip – flop in RESET state i.e. Q =0.
The logic symbol of T flip – flop is shown below. It has one Toggle input (T) & In simple terms, the operation of the T flip – flop is
one clock signal input (CLK).
When the T input is low, then the next sate of the T flip flop is same as the present
state.

 T = 0 and present state = 0 then the next state = 0

 T = 1 and present state = 1 then the next state = 1

Working When the T input is high and during the positive transition of the clock signal, the
T flip – flop is an edge triggered device i.e. the low to high or high to low next state of the T flip – flop is the inverse of present state.
transitions on a clock signal of narrow triggers that is provided as input will cause
 T = 1 and present state = 0 then the next state = 1
the change in output state of flip – flop.
 T = 1 and present state = 1 then the next state = 0

LCAS-Pattambi 30 | P a g e
 ELE2C02-Electronic circuits

As each incoming trigger alternately changes the set and reset inputs, the flip – and in/out of the registers by applying clock pulses. An n-bit shift register can be
flop toggles. So to complete one full cycle of output wave form it need two formed by connecting n flip-flops where each flip flop stores a single bit of data.
triggers. This means that the T flip flop produces the output at exactly half of the Shift registers are basically of 4 types. These are:
frequency of input frequency. So a T flip – flops will act as “Frequency Divider
1. Serial In Serial Out shift register
Circuit”.
2. Serial In parallel Out shift register
The main disadvantage of T flip – flop is that the state of the flip – flop at an
3. Parallel In Serial Out shift register
applied trigger pulse is known only when the previous state is known.
4. Parallel In parallel Out shift register
SHIFT REGISTERS
Serial-In Serial-Out Shift Register (SISO)
A register capable of shifting its binary information in one or both directions is
The shift register, which allows serial input (one bit after the other through a
called a shift register. The logical configuration of a shift register consist of a
single data line) and produces a serial output is known as Serial-In Serial-Out shift
chain of flip-flop is cascade, with the output of one flip-flop connected to the
register. Since there is only one output, the data leaves the shift register one bit at
input of the next flip-flop. All flip-flops receive common clock pulses that initiate
a time in a serial pattern, thus the name Serial-In Serial-Out Shift Register.
the shift from one stage to the next.
The logic circuit given below shows a serial-in serial-out shift register. The circuit
consists of four D flip-flops which are connected in a serial manner. All these flip-
flops are synchronous with each other since the same clock signal is applied to
each flip flop.

A shift register basically consists of several single bit “D-Type Data Latches”, one
for each data bit, either a logic “0” or a “1”, connected together in a serial type
daisy-chain arrangement so that the output from one data latch becomes the input
of the next latch and so on. The above circuit is an example of shift right register, taking the serial data input
The information stored within these registers can be transferred with the help from the left side of the flip flop. The main use of a SISO is to act as a delay
of shift registers. Shift Register is a group of flip flops used to store multiple bits element.
of data. The bits stored in such registers can be made to move within the registers

LCAS-Pattambi 31 | P a g e
 ELE2C02-Electronic circuits

Serial-In Parallel-Out shift Register (SIPO) Parallel-In Serial-Out Shift Register (PISO)
The shift register, which allows serial input (one bit after the other through a The shift register, which allows parallel input (data is given separately to each flip
single data line) and produces a parallel output, is known as Serial-In Parallel-Out flop and in a simultaneous manner) and produces a serial output is known as
shift register. Parallel-In Serial-Out shift register.
The logic circuit given below shows a serial-in-parallel-out shift register. The The logic circuit given below shows a parallel-in-serial-out shift register. The
circuit consists of four D flip-flops which are connected. The clear (CLR) signal is circuit consists of four D flip-flops which are connected. The clock input is
connected in addition to the clock signal to all the 4 flip flops in order to RESET directly connected to all the flip flops but the input data is connected individually
them. The output of the first flip flop is connected to the input of the next flip flop to each flip flop through a multiplexer at the input of every flip flop. The output of
and so on. All these flip-flops are synchronous with each other since the same the previous flip flop and parallel data input are connected to the input of the
clock signal is applied to each flip flop. MUX and the output of MUX is connected to the next flip flop. All these flip-
flops are synchronous with each other since the same clock signal is applied to
each flip flop.

The above circuit is an example of shift right register, taking the serial data input
from the left side of the flip flop and producing a parallel output. They are used in
communication lines where de-multiplexing of a data line into several parallel
lines is required because the main use of the SIPO register is to convert serial data
into parallel data.
A Parallel in Serial out (PISO) shift register us used to convert parallel data to
serial data.

LCAS-Pattambi 32 | P a g e
 ELE2C02-Electronic circuits

Parallel-In Parallel-Out Shift Register (PIPO) Counters:

The shift register, which allows parallel input (data is given separately to each flip
Flip-flops can be connected together to perform counting operation, such a group
flop and in a simultaneous manner) and also produces a parallel output is known
of flip-flops is a counter. Counters are classified into two broad categories
as Parallel-In parallel-Out shift register.
according to the way they are clocked: asynchronous and synchronous. In
The logic circuit given below shows a parallel-in-parallel-out shift register. The
asynchronous counter, commonly called ripple counters, the first flip-flop is
circuit consists of four D flip-flops which are connected. The clear (CLR) signal
clocked by the external clock pulse and then each successive flip-flop is clocked
and clock signals are connected to all the 4 flip flops. In this type of register, there
by the output of the preceding flip-flop. In synchronous counters, the clock input
are no interconnections between the individual flip-flops since no serial shifting of
is connected to all of the flip-flops so that they are clocked simultaneously.
the data is required. Data is given as input separately for each flip flop and in the
Asynchronous counter:
same way, output also collected individually from each flip flop.
The figure shows a 2-bit counter connected for asynchronous operation. The clock
(CLK) is applied to the clock input (C) of only the first flip-flop.FF0,which is
always the LSB.The second flip-flop FF1 changes only when triggered by a
positive-going transition of the Q0’ output of FF0. Because of the inherent
propagation delay time through a flip-flop, a transition of the input clock pulse
(CLK) and a transition of the Q0’ output of FF0 can never occur at exactly the
same time. Therefore, the two flip-flops are never simultaneously triggered, so the
counter operation is asynchronous. The asynchronous counters are also known as
ripple counters.

A Parallel in Parallel out (PIPO) shift register is used as a temporary storage

device and like SISO Shift register it acts as a delay element.

LCAS-Pattambi 33 | P a g e
 ELE2C02-Electronic circuits

The timing Diagram shows, during the positive –going edge of CLK 1, Q0 goes will toggle and Q0 will therefore go HIGH. During second CLK, the input of J1
HIGH and Q0’ is LOW. This will not affect in FF1, because flip-flop is triggered and K1 of flip-flop FF1 goes LOW because Q0 become LOW. Here there is a
propagation delay from the triggering edge of the clock pulse until the Q output
only at Positive going –edge. During second clock pulse Q0’ goes HIGH,
actually makes a transition.
simultaneously FF1 triggered and gives HIGH.
Computer memory:

Digital memory is a physical semiconductor device ,that store data or

information's in the form of ‘0’s and ‘1’s. The basic unit of memory is ‘bits’
Semiconductor memory is made up of registers are the combination of memory
cells .The memory cell/Register is the fundamental building block of computer
memory .Each memory cells is fabricated using circuits like Flip flops. Flip flop
is a sequential logic circuit designed using Logic gates which store One bit data.
Synchronous counter
Logic gates are fabricated using Integrated circuits like combination of
In a synchronous counter, all the flip-flops are synchronized to the same clock
Transistors and capacitors.
input. This means that for every clock pulse, all the flip-flops will generate an
Memory is primarily of three types –
output. Since the clocking is done in a parallel manner, synchronous counters are
 Cache Memory
also known as parallel counters/simultaneous counters.
 Primary Memory/Main Memory
 Secondary Memory

Cache Memory
Cache memory is a very high speed semiconductor memory which can speed up
the CPU. It acts as a buffer between the CPU and the main memory. It is used to
hold those parts of data and program which are most frequently used by the
CPU.
The advantages of cache memory are as follows –
 Cache memory is faster than main memory.
 It consumes less access time as compared to main memory.
 It stores the program that can be executed within a short period of time.
First ,assume that the counter is initially in the binary 0 state; that is ,both flip-
 It stores data for temporary use.
flops are RESET .When the positive edge of the first clock pulse is applied,FF0

LCAS-Pattambi 34 | P a g e
 ELE2C02-Electronic circuits

The disadvantages of cache memory are as follows – Characteristics of Secondary Memory

 Cache memory has limited capacity.  These are magnetic and optical memories.
 It is very expensive.  It is known as the backup memory.
 It is a non-volatile memory.
Primary Memory (Main Memory)
 Data is permanently stored even if power is switched off.
Primary memory holds only those data and instructions on which the computer is
 It is used for storage of data in a computer.
currently working. It has a limited capacity and data is lost when power is
 Computer may run without the secondary memory.
switched off. It is generally made up of semiconductor device. These memories
are not as fast as registers. The data and instruction required to be processed  Slower than primary memories.

resides in the main memory. It is divided into two subcategories RAM and ROM. Random access memory (RAM) and Read Only Memory (ROM)

Memory is the most essential element of a computing system because without

Characteristics of Main Memory
memory computer can’t perform simple tasks. Computer memory is of two basic
 These are semiconductor memories. type – Primary memory (RAM and ROM) and Secondary memory (hard drive,

 It is known as the main memory. CD, etc.). Random Access Memory (RAM) is primary-volatile memory and Read

 Usually volatile memory. Only Memory (ROM) is primary-non-volatile memory.

 Data is lost in case power is switched off.

 It is the working memory of the computer.
 Faster than secondary memories.
 A computer cannot run without the primary memory.

Secondary Memory

This type of memory is also known as external memory or non-volatile. It is

slower than the main memory. These are used for storing data/information
permanently. CPU directly does not access these memories; instead they are
accessed via input-output routines. The contents of secondary memories are first
transferred to the main memory, and then the CPU can access it. For example,
Hard disk, CD-ROM, DVD, etc.

LCAS-Pattambi 35 | P a g e
 ELE2C02-Electronic circuits

Random Access Memory (RAM) Types of Read Only Memory (ROM)

 It is also called as read write memory or the main memory or the primary 1. PROM (Programmable read-only memory) – It can be programmed by user.
memory. Once programmed, the data and instructions in it cannot be changed.
 The programs and data that the CPU requires during execution of a program 2. EPROM (Erasable Programmable read only memory) – It can be
are stored in this memory. reprogrammed. To erase data from it, expose it to ultra violet light. To
 It is a volatile memory as the data loses when the power is turned off. reprogram it, erase all the previous data.
 RAM is further classified into two types- SRAM (Static Random Access 3. EEPROM (Electrically erasable programmable read only memory) – The
Memory) and DRAM (Dynamic Random Access Memory). data can be erased by applying electric field, no need of ultra violet light. We
can erase only portions of the chip.

4. EAPROM stands for Electronically Alterable Programmable Read-Only

Memory. It is a type of PROM whose contents can be changed. It acts as
a non-volatile storage device, and its individual bits can be re-programmed
during the course of system operation.

Read Only Memory (ROM)

1. Stores crucial information essential to operate the system, like the program
essential to boot the computer.
2. It is not volatile.
3. Always retains its data.
4. Used in embedded systems or where the programming needs no change.
5. Used in calculators and peripheral devices.
6. ROM is further classified into 4 types- ROM, PROM, EPROM, and EEPROM.

LCAS-Pattambi 36 | P a g e
 ELE2C02-Electronic circuits

References
1. Thomas L. Floyd , Digital Fundamentals.
2. R.L. Tokheim, Digital Principles.
3. Donald P. Leach, Albert Paul Malvino, Digital Principles and
Applications,
4. M. Morris Mano, Michael D. Ciletti, Digital Design
5. R.P. Jain, Modern Digital Electronics.

LCAS-Pattambi 37 | P a g e