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LOD311B Chapter 8B

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6 views12 pages

LOD311B Chapter 8B

Uploaded by

nayraditsela
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Fundamentals of Digital Logic With VHDL 1

CHAPTER 8
Synchronous Sequential Circuits
Introduction
2

 A finite State machine or FSM , is a computation that


can be used to simulate sequential logic, or to
represent and control execution flow. FSM can be
used to model problems in many fields, including
mathematics, artificial intelligence, games or
linguistics.

Fundamentals of Digital Logic With VHDL


FSM Design
Step 1:
 Obtain the specifications of the circuit
◼ The circuit has one input, w, and one output, z.
◼ All changes occur on the positive edge of the clock signal
◼ z is equal to 1 if during two immediate preceding clock cycles the input, w,
was equal to 1. Otherwise, z is equal to 0.

Clockcycle: t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10
w: 0 1 0 1 1 0 1 1 1 0 1
z: 0 0 0 0 0 1 0 0 1 1 0

Fundamentals of Digital Logic


Chp 8.1 p481 3
With VHDL
FSM Design
Step 1:
 Obtain the specifications of the circuit
◼ The circuit has one input, w, and one output, z.
◼ All changes occur on the positive edge of the clock signal
◼ z is equal to 1 if during three immediate preceding clock cycles the input, w,
was equal to 1 0 11 . Otherwise, z is equal to 0.

Clockcycle: t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10
w: 0 1 0 1 1 0 1 1 1 0 1
z: 0 0 0 0 0 1 0 0 1 1 0

Fundamentals of Digital Logic


Chp 8.1 p481 4
With VHDL
Difference between Meally and
5
Moore System
 Moore Update the output in the state while mealy
update the output during transition
 The output of Moore depends only on the current
state while the output of Meally depends on both
current state and the input

Fundamentals of Digital Logic With VHDL


FSM Design
Step 3

 Create the state diagram of 11 sequence.

Fundamentals of Digital Logic


6
With VHDL
FSM : Meally

 Create the state table of 11 sequence.

Fundamentals of Digital Logic


7
With VHDL
FSM : Meally

 Create the state assigned table of 11 sequence.

Fundamentals of Digital Logic


8
With VHDL
FSM : Meally

Fundamentals of Digital Logic


9
With VHDL
Example

 Draw the state table of a Meally type FSM to detect


the code: 101
Reset

w = 1
w = 0 Az= 0 Bz= 0

w = 0

w = 0 w = 1

Cz = 1

w = 1

Fundamentals of Digital Logic


10
With VHDL
FSM Design
Step 6b
 Use the State-assigned table to derive Next-State and
Output expressions
 These output expressions will result in logic circuits for the
combinational blocks of the General sequential circuit

Fundamentals of Digital Logic


11
With VHDL
Reference
12

 State table for FSM to detect 101:


https://www.youtube.com/watch?v=HYBxoz6yGO
Q
 http://web.eece.maine.edu/eason/ece275/Mealy
Moore.pdf
 https://www.geeksforgeeks.org/design-101-
sequence-detector-mealy-machine/
 https://www.ques10.com/p/6738/design-mealy-
sequence-detector-to-detect-a-seque-1/
Fundamentals of Digital Logic With VHDL

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