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Lab 1 DP

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0% found this document useful (0 votes)
24 views9 pages

Lab 1 DP

Uploaded by

anujpasaya7
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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EL467 – Digital Programming

Name:Anuj Pasaya
ID: 202101509
Lab 1

Q1:

Structural Code:

module ex_1(out, v1, v2, v3, v4, v5, v6);

input v1, v2, v3, v4, v5, v6;

output out; wire w1, w2, w3;

and g1(w1, v1, v2), g2(w2, v3, v4), g3(w3, v5, v6);

or g4(out, w1, w2, w3);

endmodule

RTL Code:

module ex_1(out, v1, v2, v3, v4, v5, v6);

input v1, v2, v3, v4, v5, v6;

output out;

wire w1, w2, w3;

assign w1 = v1 & v2, w2 = v3 & v4, w3 = v5 & v6;

assign out = w1 | w2 | w3;


endmodule

Behavioral Code:

module ex_1 (out, v1, v2, v3, v4, v5, v6);

input v1, v2, v3, v4, v5, v6; output reg out;

always @(*)

Begin

if ((v1 && v2) || (v3 && v4) || (v5 && v6))

out = 1'b1;

else

out = 1'b0;

end

Endmodule

Output:
Q2:

Instance Code:

module ex_2(outa, va, vb, vc);

input va, vb, vc; output outa;

wire out;

ex_1 sys(out, va, 1'b1, vb, 1'b1, vc, 1'b1);

nand g1(outa, out, 1'b1);

endmodule

Output:
Q3:

Structural Code:

module half_adder (sum, carry, a, b);

input a, b;

output sum, carry;

xor g1(sum, a, b);

and g2(carry, a, b);

endmodule

RTL Code:
module half_adder (sum, carry, a, b);

input a, b;

output sum, carry;

assign sum = a ^ b;

assign carry = a & b;

Endmodule

Behavioral Code:

module half_adder (sum, carry, a, b);

input a, b;

output reg sum, carry;

always @ (a or b)

begin

if(a ^ b) sum = 1'b1;

else sum = 1'b0;

if(a & b) carry = 1'b1;

else carry = 1'b0;

end

Endmodule
Q4:

Code:

module full_adder (sum, cout, a, b, cin);

input a, b, cin;

//output sum, cout;

// Structural Level Modeling

/*

wire s1, c1, c2;

xor g1(s1, a, b);

xor g2(sum, s1, cin);

and g3(c1, a, b);

and g4(c2, s1, cin);

or g5(cout, c1, c2);

*/

// RTL Modeling
/*

assign sum = a ^ b ^ cin;

assign cout = (a & b) | (b & cin) | (cin & a);

*/

// Behavioral Modeling

output reg sum, cout;

always @ (a or b or cin)

begin

if(a ^ b ^ cin) sum = 1'b1;

else sum = 1'b0;

if((a & b) | (b & cin) | (cin & a)) cout = 1'b1;

else cout = 1'b0;

end

Endmodule
Q5:

Code:

module half_adder (

input a, b,

output sum, carry

);

assign sum = a ^ b;

assign carry = a & b;

endmodule

module full_adder (sum, cout, a, b, cin);

input a, b, cin;

output sum, cout;

wire sum1, carry1, carry2;

// Instantiating two half adders

half_adder ha1 (.a(a), .b(b), .sum(sum1), .carry(carry1));

half_adder ha2 (.a(sum1), .b(cin), .sum(sum), .carry(carry2));

// Calculating final carry

assign cout = carry1 | carry2;

Endmodule

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