Lab 1 DP
Lab 1 DP
Name:Anuj Pasaya
ID: 202101509
Lab 1
Q1:
Structural Code:
and g1(w1, v1, v2), g2(w2, v3, v4), g3(w3, v5, v6);
endmodule
RTL Code:
output out;
Behavioral Code:
input v1, v2, v3, v4, v5, v6; output reg out;
always @(*)
Begin
out = 1'b1;
else
out = 1'b0;
end
Endmodule
Output:
Q2:
Instance Code:
wire out;
endmodule
Output:
Q3:
Structural Code:
input a, b;
endmodule
RTL Code:
module half_adder (sum, carry, a, b);
input a, b;
assign sum = a ^ b;
Endmodule
Behavioral Code:
input a, b;
always @ (a or b)
begin
end
Endmodule
Q4:
Code:
input a, b, cin;
/*
*/
// RTL Modeling
/*
*/
// Behavioral Modeling
always @ (a or b or cin)
begin
end
Endmodule
Q5:
Code:
module half_adder (
input a, b,
);
assign sum = a ^ b;
endmodule
input a, b, cin;
Endmodule