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Verilog HDL Using Quartus Prime

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0% found this document useful (0 votes)
59 views13 pages

Verilog HDL Using Quartus Prime

Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Installation of Quartus Prime

1. Download the Intel® Quartus® Prime Lite Edition Design Software Version 20.1.1 from the
following link
https://www.intel.com/content/www/us/en/software-kit/660907/intel-quartus-prime-lite-editio
n-design-software-version-20-1-1-for-windows.html

2. Extract the downloaded file.

3. Run the setup.bat file.

4. During installation make sure the following components are selected.

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Simulating Verilog HDL using Quartus Prime
1. Find the following icon on your PC and run the software by double-clicking the icon.

2. For using the Quartus Prime very first time we need to locate the directory of ModelSim Altera.
For that execute Tool → Options → EDA Tool Options and give the proper location of ModelSim
Altera and click OK. Normally the location is

C:\intelFPGA_lite\20.1\modelsim_ase\win32aloem
or
C:\intelFPGA\20.1\modelsim_ase\win32aloem

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3. The following window will pop up. Now click on the New project wizard.

4. Click Next on the following window.

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5. In the following window change the working directory of the project to your directory (e.g.
D:\150205022 VLSI-2) and give a name to the project as shown and click Next three times.
[Project name must be same as the top module]

6. After clicking Next three times the following window will pop up then choose any device family
according to Device availability and click next. Here “Cyclone-IV E” E4CE6E22C6 model is
selected.

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7. Now set the simulation tool as “ModelSim – Altera” , format as “Verilog HDL” and make sure the
“Run gate-level simulation automatically after compilation” check box is not checked in the
EDA tool settings window. After that click Next.

8. The summary window will appear and click Finish.

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9. Execute File → New. In the New window select the Verilog HDL file and click ok. The editor
window will appear.

10. In the editor window write the Verilog module of your design.

11. Now click on the compilation icon for compiling the design. In this step, the software will ask you
to save the Verilog HDL file. Save it with the identical name of the project file.

12. After successful compilation you will get the following message. Ignore the warnings.

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13. The RTL view of the Verilog module can be obtained in Quartus prime by executing Tools →
Netlist Viewers → RTL Viewer.

14. The RTL view of our design will be like the following figure.

15. Now to launch ModelSim, execute Tool→ Run Simulation Tool → RTL Simulation.

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16. The ModelSim will be launched, and the following window will open.

17. Now go to the Library window present on the left side of the ModelSim window and execute
rtl_work→ <double click on your project module name>

18. The input and output variables defined in the Verilog will appear in the Objects window.

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19. Now select all the input and output variables of the Objects window and by right-clicking on
your mouse execute Add Wave to place them in the Wave window.

20. All the input and output variables will be placed on the wave window and the wave window will
look like the following.

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21. Now apply clocks to each input variable. Right-clicking any input variable and from the
popped-up menu execute Modify → Clock.

22. The Define Clock window will appear. Set parameters as per your requirement keep in mind all
the units are in picoseconds by default.

23. After defining all the input clocks, to evaluate the outputs write run 100 ps on the Transcript of
ModelSim. Then the simulation will be performed for 100 ps.
[Give run length according to your requirement.]

Alternatively, we can run the wave output using the Run icon by typing the Run length

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24. The wave window will look like the following figure after simulation.

If you need to change the clock pulse you must reset all the clocks before changing clocks otherwise
the inputs and outputs will change after the previous run time which is not a convenient way to
represent the inputs and outputs. The command “restart” is used in the transcript for resetting all
the clocks. Alternatively, restart can be performed by executing Simulate → Restart

Showing Binary values on the Wave


Sometimes it is hard to verify the functionality of a digital system from the wave. For easy functional
verification, we can read the binary values from the wave of ModelSim by doing the following steps.

I. Select all the input and output variables on the clock and right-click on the mouse and
execute Radix → Binary.

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II. After changing the Radix, change the Format type similarly by selecting all input and
output variables on the wave by right-clicking on the mouse and then executing Format
→ Literal.

III. Now on the wave, binary values will be displayed which can be easily analyzed.

Changing Clock Unit


In step 23 it is mentioned that ModelSim’s default timing unit is picosecond. But in some cases, we may
need to define clocks in other units. Let us consider, that we need to define the period of a, b, and c as
10ms, 5ms, and 2.5ms respectively. Now define the clock a, b, and c as shown in the below figures.

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To view the output for all the input combinations the run length should be equal to the maximum
period.

As all the units are in milliseconds, for easy visualization we can change the time units of the wave grid
by executing Wave → Wave Preferences → Grid & Timeline → Time units → ms.

Now the ModelSim wave window will look like the following figure.

Similarly, for femtoseconds, nanoseconds, and microseconds, we can use fs, ns, and ms respectively

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