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Packed U Cells Multilevel Converter Topology: Theoretical Study and

Experimental Validation

Article in IEEE Transactions on Industrial Electronics · May 2011

DOI: 10.1109/TIE.2010.2050412 · Source: IEEE Xplore

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1294 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 58, NO. 4, APRIL 2011

Packed U Cells Multilevel Converter Topology:

Theoretical Study and Experimental Validation
Youssef Ounejjar, Member, IEEE, Kamal Al-Haddad, Fellow, IEEE, and Luc-André Grégoire

Abstract—In this paper, authors propose a new power multilevel with high potential for further development. The most attrac-
converter topology that is very competitive compared to the exist- tive applications of this technology are in the medium–high
ing ones. It consists of packed U cells (PUC). Each U cell consists voltage ranges, and include the following: 1) motor drives;
of an arrangement of two power switches and one capacitor. It
offers high-energy conversion quality using a small number of 2) photovoltaic systems; 3) power distribution; 4) power qual-
capacitors and power devices and consequently, has a very low ity; and 5) power conditioning applications. Due to their
production cost. An averaged model of the topology is detailed. ability to synthesize waveforms with a controlled harmonic
The operating principle of the transformerless seven-level inverter spectrum and to attain higher voltages, and to overcome the
is analyzed and detailed. The multilevel sinusoidal modulation has limited semiconductor voltage and current ratings, multilevel
been adapted for use with the PUC-based structure. The control
strategy has been designed to reduce the harmonic contents of the inverters have been receiving increasing attention for the past
load voltage. With such converters, filters’ rating is considerably few years [8]. By generating high voltage with low harmonic
reduced. A comparative study is performed to highlight the ad- contents, while reducing switches’ stress, multilevel convert-
vantages of the new packed U cells topology. The operation of the ers allow an effective high power exchange between multiple
proposed converter topology has been verified through simulation. sources. Traditional multilevel converters like the following:
Experimental validation was performed using DS1103 DSP of
dSpace. 1) neutral point-clamped converters (NPC) proposed by
Nabae et al. [9]; 2) flying capacitors converters (FCC) proposed
Index Terms—DSP implementation, harmonics, multilevel con- by Meynard et al. [10]; 3) and classic cascaded H-bridges
verter topologies, power quality, unity power factor operation.
proposed by Peng et al. [11], present many drawbacks if the
number of voltage levels is increased. In fact, the number of
I. I NTRODUCTION
switches, diodes and capacitors grows excessively, resulting in

F OR DECADES, renewable energy resources have been

the focus for researchers, and different families of power
converters have been designed to ease the integration of these
prohibitive cost and their implementation becomes very com-
plicated. Hybrid cascaded H-bridges topology [12] presents
many advantages and typically, they use a small number of
types of systems into the distribution grid [1]. Nowadays, power active and passive components. In the last few years, many
conversion is a well-studied topic by academics and industries propositions have been presented to improve their efficiency
due to the power demand and the integration of power sources [13]–[27].
in the electrical grid or in stand-alone applications [2]. The In this paper, the authors propose a novel multilevel compet-
domain of power conversion quality is subdivided into two itive topology which offers high power quality using a small
broad classes. The first considers power converters as pollution number of passive and active components. It can be classified
emitters particularly in terms of harmonics and power factor. as a compromise between the flying capacitor and the cascaded
In this technology, research has been focused to improve the H-bridges topologies. A detailed comparative study of these
power quality by using additional hardware like active/hybrid converters is given to show the advantages and the effectiveness
filters [3]–[7]. This affects greatly the efficiency of power of the proposed schemes. The novel topology can be seen as
exchange and the cost of the installations. asymmetric flying capacitors or packed U cells. Each U cell
The aim of the second is to provide a low-cost nonpolluant consists of two power switches and one capacitor as shown
converter with high energy efficiency. Multilevel converters in Fig. 1(a). Simulation results and experimental validation are
belong to this technology. Multilevel power conversion tech- presented to confirm the advantages of the proposed concept.
nology is a very rapidly growing area of power electronics
II. P RESENTATION OF THE P ROPOSED
Manuscript received June 15, 2009; revised October 30, 2009, February 6,
2010, and March 19, 2010; accepted April 27, 2010. Date of publication June 1, M ULTILEVEL T OPOLOGY
2010; date of current version March 11, 2011. This work was supported by
the Natural Sciences and Engineering Research Council of Canada (NSERC), The proposed topology is subdivided into many multilevel
by the Canada Research Chair in Electric Energy Conversion and Power converters. Each one is characterized by the number of at-
Electronics, and by FQRNT of Quebec. tainable voltage levels. Fig. 1(b) shows the transformerless
The authors are with the Department of Electrical Engineering, École
De Technologie Supérieure, Montréal, QC H3C 1K3, Canada (e-mail: single-phase seven-level inverter, Fig. 1(c) shows the seven-
[email protected]; [email protected]; luc-andre.gregoire.1@ level rectifier, Fig. 1(d) shows the topology in the case of
ens.etsmtl.ca). 31-level single-phase converter, whereas Fig. 1(e) presents the
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. three- phase seven-level converter. The number of voltage levels
Digital Object Identifier 10.1109/TIE.2010.2050412 across the line-to-line load voltage is 13. Moreover, the number

0278-0046/$26.00 © 2010 IEEE

OUNEJJAR et al.: PACKED U CELLS MULTILEVEL CONVERTER TOPOLOGY 1295

Fig. 1. Different converter schemes. (a) Single U cell. (b) Single-phase seven-level inverter. (c) Single-phase seven-level rectifier. (d) Single-phase 30 one-level
inverter. (e) Three-phase seven-level inverter.

TABLE I
VOLTAGES VALUES OF DIFFERENT MULTILEVEL CONVERTERS OF THE PROPOSED TOPOLOGY

of voltage levels depends on the value of the voltage across the der to obtain these levels, the second capacitor voltage (V2 )
capacitors. To determine the values of voltages V2 , V3 , and V4 must be regulated to V 1/3. Classic multilevel converters, such
[of Fig. 1(d)], one can carry out a comparative analysis which as the Cascaded H-Bridge Converter, require many dc sources
is illustrated in Table I. which may result in the use of an excessive number of trans-
In case of using two capacitors, the output voltage formers. In order to reduce these, a transformerless inverter
is therefore obtained from the following seven levels configuration is proposed. However, like other transformerless
(V dc, 2.V dc/3, V dc/3, 0, −V dc/3, −2.V dc/3, −V dc). In or- inverters, it suffers from a common drawback manifested at low
1296 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 58, NO. 4, APRIL 2011

at medium frequency. The combination of two GTOs and four

IGBTs in the seven-level PUC topology permits to achieve
optimally designed and efficient high power conversion unit.

III. O PERATION OF THE S EVEN -L EVEL

PACKED U C ELLS C ONVERTER
Fig. 3 shows the scheme of the converter under study which
makes use of two capacitors. The first one is the dc source
V 1 which is generated from the ac supply network, and the
second is V 2 which is regulated by the converter control circuit
to the desired voltage level that is required to produce the
exact number of voltage levels across the load. The proposed
topology makes use of six semiconductor devices T1,2,3 and
T1,2,3 . Each switch consists of a MOSFET with its antiparallel
diode and has only two operating states. Since only three
switches form one leg, then eight possible state combinations
can be identified (Fig. 3).
Fig. 2. Output voltage and holding voltage of different Ti switches. Two of the states are redundant and represent the zero voltage
and the other six active states apply the appropriate voltage
level across the load as seen in Table II. The sequence of the
modulation indices, where auxiliary capacitors are not charged
operation of the converter describing the eight possible states is
because they are never connected to the main dc bus. The
therefore given in Fig. 3. As shown in this figure, the ac load
number of the voltage levels of the proposed PUC topology is
is fed by seven-level V1 , V1 − V2 , V2 , 0, −V2 , V2 − V1 , and
governed by a geometric progression of the following form:
−V1 , single-phase topology. Moreover, for other applications,
un = a.u(n−1) + b if required, a dc load can be placed across the capacitor.
By subdividing the desired sinusoidal waveform into three
u0 = U. (1) positive and three negative zones as shown in Fig. 4, and
using seven-level sinusoidal modulation, one can produce four
The nth term can be written as follows: rectangular signals with two values two or one for the three
1 − an positive zones and −2 or −1 for the three negative ones; also,
un = an U + b . (2) two rectangular signals with two values one or zero for the
1−a
positive zone and zero or −1 for the negative zone. Summing
Thus, these signals leads to a unique signal S having eight levels as
shown in Fig. 5. The later shows the signal which synthesizes
Ni = 2N ci +1 − 1 (3) the desired output voltage. In this signal, the redundant states,
which correspond to the null voltage, are identified for a better
where N ci is the number of used capacitors, Ni is the number
use of the switching devices. If the modulating frequency is not
of voltage levels, and i is an integer. By the same, the number of
equal to a multiple of the fundamental frequency (60 Hz), then,
produced voltage levels Ni according to the number of power
there is an asymmetry in the resulting signal. Figs. 7 and 9 are
switches N swi is given by the following equation:
obtained with a modulating frequency equal to 960 Hz. These
N swi
Ni = 2 2 − 1. (4) levels correspond to the desired seven-level output voltages
with the redundant null one. Thus, the use of a lookup switching
When using four capacitors, the number of voltage levels will table (Table II) allows the generation of the synthesized seven-
be N4 = 31. In this case, only ten power switches are required. level voltages as shown in Fig. 13(a).
Fig. 2 shows the holding voltage of T1 , T2 , and T3 switches
for a seven-level converter with V 1 = 150 V and V 2 = 50 V,
operating under sinusoidal modulation. The total converter ac IV. C OMPARATIVE S TUDY OF THE P ROPOSED
voltage Vab is given by the following equation: T OPOLOGY W ITH OTHER C OMPETITIVE
M ULTILEVEL T OPOLOGIES
Vab = Vaa1 − Va2a1 − Vba2 . (5) A. Comparison Toward Neutral Point Diode Clamped NPC
and Flying Capacitors Topologies
By observing Vaa1 , Va2a1 , and Vba2 , one can notice the
potential of using a combination of two types of semicon- This section of the paper presents a comparative study of the
ductor devices technologies (GTO and IGBT) in this high- proposed topology with two other topologies that make use of
power conversion scheme. In fact, the major drawback of the NPC and flying capacitors configurations. However, one must
GTO technology is its limited switching frequency; whereas, take into account the additional drawback of NPC which uses
IGBT technology cannot sustain high power, while operating additional clamping diodes that characterize the NPC topology.
OUNEJJAR et al.: PACKED U CELLS MULTILEVEL CONVERTER TOPOLOGY 1297

Fig. 3. One cycle operating states of the proposed packed U cells seven-level topology.

TABLE II
SWITCHING TABLE OF THE PROPOSED SEVEN-LEVEL CONVERTER

Fig. 5. Signal S waveform.

In a flying capacitor converter [e.g., the three-level shown in

Fig. 6(a) and the four-level shown in Fig. 6(c)], the zero voltage
is produced by the subtraction of the flying capacitor and the
half of the dc bus voltages, because it cannot be produced
otherwise.
Based on the architecture of the three-level flying capacitors
converter [Fig. 6(a)], two switching devices have been added
in order to produce the zero-voltage level and to remove the
dependence between the flying and the dc bus capacitors volt-
Fig. 4. Seven-level sinusoidal modulation. ages resulting in the proposed seven-level converter topology
1298 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 58, NO. 4, APRIL 2011

Fig. 6. Converters schemes of the (a) three-level flying capacitors, (b) proposed seven-level, and (c) four-level flying capacitors.

as shown in Fig. 6(b). FC topology requires 12 switches and

six capacitors; whereas, the proposed one generates the same
voltage levels with 200% of cost reduction in terms of passive
components and 100% in terms of active components. That is
to say the number of semiconductors has been reduced from
12 to six, and the number of capacitors is reduced from six to
two. Consequently, when compared with an FC converter, the
U-cell topology might achieve smaller physical size thereby
resulting in a very compact power conversion unit. The cost
saving, in terms of the capacitors, depending on the desired
number of levels in the output voltage is given by the following
equation:

gc = (N − log2 (N + 1)) × pc (6)

where, “pc” is the price of one capacitor and N is the desired

number of levels in the output voltage (e.g., N = 7 means
seven-level converter). gc is the number of saved capacitors

log(x)
log2 (x) = . (7)
log(2)

This cost can be expressed in percent by

N − log2 (N + 1)
gc (in%) = 100 × . (8)
log2 (N + 1) − 1

Fig. 7(a) shows the evolution of the cost saving in terms

of the capacitors in percent depending on the desired number
of voltage levels. The power semiconductor devices saving Fig. 7. Benefits of the PUC compared to FC topology. (a) Cost saving in (%)
in terms of capacitors according to the number of voltage levels. (b) Power
depending on the desired number of levels in the output voltage quality gain in (%) in terms of voltage levels according to the number of
is given by equation capacitors.

gsw = (2 × (N − 1 − log2 (N + 1))) . (9)

For the same number of capacitors, the use of the proposed
The number of voltage levels according to the number of topology against flying capacitors one improves the number of
capacitors of a flying capacitors converter is given by levels in the output voltage by

N = Nc + 1. (10) 2N c+1 − Nc − 2
g1 = 100 × %. (12)
Nc + 1
From equations (3) and (10), we deduce the power quality
gain in terms of voltage level surplus which is given by The evolution of this gain is shown in Fig. 7(b). For three
capacitors (Nc = 3), the use of the proposed topology against
gq = 2N c+1 − Nc − 2. (11) flying capacitors gives eleeven additional voltage levels.
OUNEJJAR et al.: PACKED U CELLS MULTILEVEL CONVERTER TOPOLOGY 1299

Fig. 8. Seven-level converters. (a) Classic cascaded H-bridges. (b) Hybrid cascaded H-bridges (E2 equals the third of E1). (c) Proposed topology.

TABLE III
NUMBER OF VOLTAGE LEVELS SURPLUS ACCORDING
TO THE N UMBER OF C APACITORS

B. Comparison Toward Cascaded H-Bridges Topology

Fig. 8(a) shows a classic seven-level cascaded H-bridges con-
verter. To produce the same voltage levels, a hybrid cascaded
converter uses less number of active and passive components
as shown in Fig. 8(b), where E2 equals the third of E1. The
proposed U-cell converter topology can be seen as a hybrid
cascaded H-bridges converter using less number of semicon-
ductor devices as depicted in Fig. 8(c). For the classic cascaded
H-bridges converter, the number of the generated voltage levels
according to the number of capacitors is given by the following
relation:
N = 2Nc + 1 (13)
where Nc is the number of capacitors, (e.g., if Nc = 2, the
classic cascaded H-bridges converter is N = 5 level).
For a given number of capacitors, the gain in terms of voltage
level surplus is
Fig. 9. Benefits of the PUC compared to cascaded H-bridges topology.
(a) Gain in (%) of voltage levels according to the number of capacitors.
gqh = 2N c+1 − 2Nc − 2. (14) (b) Gain in (%) of voltage levels according to the number of power switches.
In percent, this gain becomes
2N c+1 − 2Nc − 2 If one chooses the classic cascaded H-bridges converter
g2 = 100 × %. (15)
2Nc + 1 to generate 31 voltage levels, eleven capacitors will be lost,
which represent a surplus of 275% compared to the proposed
Table III depicts the gain gqh . Fig. 9(a) shows the evolution topology.
of the gain g2 . In the case of hybrid cascaded H-bridges converter, the
Conversely, for a desired number of voltage levels, the cost number of the generated voltage levels according to the number
saving in terms of capacitors is given by of power switches is given by the following relation:
 
N +1
gch = − log2 (N + 1) × pc (16) Nsw
2 N =2 4 +1
−1 (17)

where, “pc” is the price of one capacitor. where Nsw is the number of power switches.
1300 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 58, NO. 4, APRIL 2011

TABLE IV
COMPARISON OF SEVEN LEVELS CLASSIC TOPOLOGIES
AND THE P ROPOSED O NE

TABLE V Fig. 10. Averaged control strategy of the seven-level PUC operating in
COMPARISON OF FIFTEEN LEVELS CLASSIC TOPOLOGIES rectifier mode.
AND THE P ROPOSED O NE

For a given number of power switches, the gain in terms of

the number of voltage levels is given by
N sw N sw
gqhh = 2 2 −2 4 +1 . (18)

This gain can be expressed in percent by Fig. 11. Seven-level PUC rectifier output voltages.
N sw N sw
2 2 −2 4 +1 Also,
g3 = 100 × . (19)

N sw
2 4 +1 −1 i1 = S1 × is
i2 = S2 × is (22)
The evolution of g3 is shown in Fig. 9(b). For example, for
i3 = S3 × is .
eight power switches (Nsw = 8), the use of the proposed topol-
ogy against hybrid cascaded H-bridges gives eight additional where is and es are, respectively the line current and the supply
voltage levels (gqhh = 8). voltage.
A comparison of the proposed topology in case of seven- and Then,
15-level converters toward classic ones is given in Tables IV
and V. One can notice the considerable reduction of the semi- dis es − Rs is − (S2 − S1) × V 1 − (S3 − S2) × V 2
= .
conductor components in the proposed topology. dt Ls
(23)

V. AVERAGED M ODEL OF A S EVEN -L EVEL PACKED Let ui be duty cycle of switch Ti . Then, assuming that
U-C ELL ACTIVE R ECTIFIER 1) Line current is constant in a switching period
According to Fig. 1(c), Ti and Ti switches operate comple-
2) u1 + u2 + u3 = 1.5. (24)
mentarily. Let Si be a switching function of Ti switch where
i = (1, 2, 3). Si is defined by Let x1 , x2 , x3 , and x4 be the state variables of the
 source–converter–load system defined by
1, if Ti is ON
Si = (20)
0, if Ti is OFF.
x1 = is , x2 = V 1 and x3 = V 2. (25)

From Fig. 1(b), one can write The averaged model of the source–converter–load system
⎧ can be given by the following matrix equation:
⎨ Vaa1 = −(1 − S1) × V 1
Va1a2 = (1 − S2)(V 1 − V 2) (21) dX
⎩ = F (X) + G(X) × U + C (26)
Va2b = (1 − S3) × V 2. dt
OUNEJJAR et al.: PACKED U CELLS MULTILEVEL CONVERTER TOPOLOGY 1301

Fig. 12. Source voltage and line current of the seven-level PUC rectifier.

Fig. 14. Output voltage Vab, load current iL , principal V 1 and auxiliary dc
bus V 2 voltages.

where
⎡ ⎤ ⎡ −Rs x1 ⎤ ⎡ es ⎤
x1 Ls Ls
X = ⎣ x2 ⎦ , F (X) = ⎣ 0 ⎦ , C=⎣ −I1
C1
⎦
x3 0 −I2
C2
⎡ ⎤
u1
U = ⎣ u2 ⎦ (27)
u3
⎡ x2 x3 −x2 −x3 ⎤
Ls Ls Ls
G(X) = ⎣ C1
x1 −x1
C1 0 ⎦. (28)
Fig. 13. (a) Proposed modulation scheme. (b) Scheme of the proposed trans- x1 −x1
formerless seven-level converter with block diagram of the control circuit. 0 C2 C2
TABLE VI
SIMULATION PARAMETERS The input vector can then be obtained by the following
equation:

⎡ ⎤ ⎡ x2 +x3 −1 1 ⎤⎡ Rs x1 −es ⎤
u1 3x1 x3 3x2 3 u11 + Ls
⎣ u2 ⎦ = ⎢ x−2x3
⎣ 3x1 x2 2 1 ⎥⎣
⎦ I2
u31 + C2 ⎦ (29)
3x2 3
u3 −2x2 −x3 −1 1 1.5
3x1 x2 3x2 3
1302 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 58, NO. 4, APRIL 2011

Fig. 15. Harmonic contents of output voltage.

Fig. 17. (a) Block diagram of the seven-level converter feeding ac and dc
loads. (b) Output voltage and holding voltage of different Ti switches.

The proposed control strategy used for the seven-level PUC

active rectifier is depicted in Fig. 10. The system parameters are
the following:
Switching frequency f s = 600 Hz;
Fig. 16. (a) Waveforms of the output voltage V ab, load current iL , principal Line inductance Ls = 3 mH;√
and auxiliary DC buses voltages V 1 and V 2, respectively. (b)Loop effects on Source voltage es = 120 2 sin(120πt).
transient.
Simulation was performed in Matlab Simulink environment
where using the SimPowerSystem toolbox.
  In order to verify the system dynamics, a dc link voltage
Ki11 reference variation is applied from 200 V to 250 V at time
u11 = −(x1ref − x1 ) Kp11 +
s t = 4 s. A sudden load change is applied, at time t = 2 s, the
  upper capacitor load changes from 25 Ω to 15 Ω, whereas the
Ki21
u21 = −(x2ref − x2 ) Kp21 + lower capacitor remains uncharged until time t = 6 s when its
s
  load becomes 25 Ω. Fig. 11 shows the output voltages’ good
Ki31 dynamic response. Output voltages ripples are kept below 4%
u31 = −(x3ref − x3 ) Kp31 + . (30)
s at full power.
OUNEJJAR et al.: PACKED U CELLS MULTILEVEL CONVERTER TOPOLOGY 1303

Fig. 18. Output voltage Vab , load current iL , principal and auxiliary dc bus voltages current. (b) Harmonic contents of load voltage.

Fig. 12 shows the source voltage and line current under Finally, load current is near sinusoidal as shown in Fig. 14.
unbalanced loads, hence confirming the unity power factor Fig. 16 shows the waveforms when a reduced capacitor size
operation after disturbances. of 680μ is considered. One can notice that at time t = 4 s, a
sudden change of the ac load resistor from 40 Ω to 20 Ω occurs.
Moreover, Fig. 16(b) shows a loop effects on transient of load
VI. C ONTROL OF THE S EVEN -L EVEL T RANSFORMERLESS voltage and current, and also the dc buses voltages. One can
PACKED U C ELLS C ONVERTER notice the good dynamic response of the proposed concept even
during sudden load variations.
The principal dc-bus (V 1) is the source voltage, which is
generated from the ac supply network using a diode bridge
rectifier. In order to generate seven levels of output voltage,
B. Experimental Validation
one must control the capacitor voltage set point equal to V 1/3.
Thus, the seven-level voltages are therefore obtained as given The Matlab Real-Time Workshop (RTW) is used to au-
in Table IV. The modulator stage produces the signal S, which tomatically generate C code from Simulink block diagrams
pass through a switching table to generate finally the gate pulses [Fig. 17(a)]. The code used to implement the converter control
(Fig. 13). is optimized for real-time application. Afterwards, the interface
between Simulink and DS1103 of dSpace [28]–[30] allows the
control algorithm to run the hardware, which is a MPC8240
VII. S IMULATION AND E XPERIENTIAL VALIDATION OF processor. Three analog-to-digital converters (ADC) are used to
THE P ROPOSED M ULTILEVEL P OWER acquire load current iL , principal and auxiliary dc-bus voltages
C ONVERTER T OPOLOGY V 1 and V 2, respectively. An electronic circuit is designed
for sensing these signals. Six digital I/O are used to output
A. Simulation Results
the MOSFET gate pulses. An opto-isolated interface board is
The system parameters are given in Table VI. The auxiliary also designed to isolate the low-power logic signals from the
dc bus of Fig. 13(a), which is loaded by 40 Ω, is controlled power stage. We choose the PolarHV HiPerFET IXF44N50P
to the third of the principal dc bus voltage V 1, which is MOSFET as power switches. The circuit components values
maintained at 150 V. The ac load is constituted by a 20 Ω are as chosen in the simulation section. Fig. 17 shows the block
resistor and an inductor of 12 mH. The switching frequency of diagram of the implemented circuit, the output voltage, and the
the sinusoidal PWM modulator is set at 1 kHz. The simulation holding voltage of T1 , T2 , and T3 switches, respectively from
was performed using SimPowerSystems in Matlab Simulink the top to the bottom. Fig. 18 shows the steady-state results
environment. Fig. 14 shows the principal and auxiliary dc bus of the converter operation as simulated in Fig. 14. One can
voltages, the ac load current, and voltage waveforms evolution. conclude a high concordance between simulation and experi-
A loop effect shows the steady-state operation. The ac load mentation of the proposed concept.
voltage has seven levels and its harmonic contents are centered The harmonic distortion of the load voltage is nearly similar
on multiples of the PWM frequency as shown in Fig. 15. The to the simulation results, as seen by comparing the results
computed output voltage THD is 24.32%. Moreover, as de- of Figs. 15 and 18(b). Harmonics with highest amplitude are
picted in Fig. 15, the amplitude of the load voltage fundamental centered on the PWM frequency which is 1 kHz. Fig. 19 shows
component, which has the frequency of 60 Hz, is equal to steps variations of ±100% of the nominal dc bus voltage. The
115.6 V. loop effects during both transients and steady states show that
1304 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 58, NO. 4, APRIL 2011

Fig. 19. Output voltage, load current, principal, and auxiliary dc bus voltages.

Fig. 20. System dynamic under load step with loop effect during transition.
OUNEJJAR et al.: PACKED U CELLS MULTILEVEL CONVERTER TOPOLOGY 1305

the auxiliary dc bus is well regulated and follows the reference [14] R. Kieferndorf, G. Venkataramanan, and M. D. Manjrekar, “A power
value which is the one-third of the principal one. In case of electronic transformer (PET) fed nine-level H-bridge inverter for large
induction motor drives,” in Conf. Rec. IEEE IAS Annu. Meeting,
load variation, Fig. 20 depicts good dynamic response of the Oct. 8–12, 2000, pp. 2489–2495.
proposed control law. Moreover, compared with Fig. 16, one [15] K. C. Sekhar and G. T. R. Das, “A nine-level inverter system for an open-
can conclude a good correlation between the simulation and end winding induction motor drive,” in Proc. IEEE Ind. Electron. Appl.,
May 2006, pp. 1–6.
experimental results. In this figure, channel C1 is the load [16] K. A. Corzine, M. W. Wielebski, F. Z. Peng, and J. Wang, “Control
voltage (vab ), C2 is the regulated auxiliary dc bus (V 2), C3 of cascaded multilevel inverters,” IEEE Trans. Power Electron., vol. 19,
is the input dc voltage (V 1), whereas, C4 is the load current. no. 3, pp. 732–738, May 2004.
[17] S. Mariethoz and M. Veenstra, “Alimentation d’onduleurs multiniveaux
Channels Z1, Z2, Z3, and Z4 are the zoom effects around the asymétriques: Analyse des possibilités de réalisation et méthodes de
instant of the load step. répartition de la puissance,” in Proc. JCGE, Saint-Nazaire, France,
Jun. 5–6, 2003.
[18] K. A. Corzine, “Method and apparatus for a reduced parts-counts multi-
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1306 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 58, NO. 4, APRIL 2011

Kamal Al-Haddad (S’82–M’88–SM’92–F’07) was Luc-André Grégoire was born in Joliette, Canada,
born in Beirut, Lebanon, in 1954. He received the on December 8, 1981. He received the B.Ing de-
B.Sc.A. and M.Sc.A. degrees from the University gree from École de Technologie Supérieure (ETS),
of Québec à Trois-Rivières, Trois-Rivières, QC, Montréal, QC, Canada, in 2008.
Canada, in 1982 and 1984, respectively, and the Since June 2008, he has worked under the supervi-
Ph.D. degree from the Institut National Polythech- sion of K. Al-Haddad and of M. Ounejjar on experi-
nique, Toulouse, France, in 1988. mental prototype of multilevel power converter at the
From June 1987 to June 1990, he was a Professor Groupe de Recherche en Électronique de Puissance
with the Department of Engineering, Université du et Commande Industrielle (GREPCI-ETS).
Québec à Trois Rivières. Since June 1990, he has
been a Professor with the Electrical Engineering
Department, École de Technologie Supérieure (ETS), Montreal, QC, Canada,
where he has been the holder of the Canada Research Chair in Electric Energy
Conversion and Power Electronics since 2002. He has supervised more than
70 Ph.D. and M.Sc.A. students working in the field of power electronics. He
was the Director of graduate study programs at the ETS from 1992 to 2003.
He is a Consultant and has established very solid link with many Canadian
industries working in the field of power electronics, electric transportation,
aeronautics, and telecommunications. He is the Chief of ETS-Bombardier
Transportation North America division, a joint industrial research laboratory
on electric traction system and power electronics. He is the Coauthor of the
Power System Blockset software of Matlab. He has coauthored more than 300
transactions and conference papers. His fields of interest are in high-efficiency
static power converters, harmonics and reactive power control using hybrid
filters, switch mode and resonant converters including the modeling, control,
and development of prototypes for various industrial applications in electric
traction, power supply for drives, telecommunication, etc.
Dr. Al-Haddad is a Fellow Member of the Canadian Academy of Engineer-
ing, a Life Member of the Circle of Excellence of the University of Quebec and
received the outstanding researcher award from ETS in 2000. He is active in the
IEEE Industrial Electronics Society where he is Vice President for Technical
Activities, an AdCom Member and serves as an Associate Editor of the IEEE
T RANSACTIONS ON I NDUSTRIAL E LECTRONICS.

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