Introduction To Systemc: Damien Hubaux - Cetic
Introduction To Systemc: Damien Hubaux - Cetic
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Introduction to SystemC
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Outline
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Why SystemC?
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Needs
Increasing complexity, gate number, simulation time, verification effort, hw/sw co-design, etc.
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Why SystemC?
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EDA developers
Small market (compared to SW) Base a new language on an existing widely used language
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What is SystemC?
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A Hardware Description language A C++ library that implements hardware concepts (clock, ports, concurrency, etc)
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What is SystemC?
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What is SystemC?
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There are (have been) 2 (successive) "opinions" about SystemC RTL modeling using C++
What is the benefit compared to my favourite HDL? (Looks suspect to HW designers)
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Outline
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You can write (RTL) SystemC without really knowing C++ Let's make a short comparison: VHDL / SystemC
ENTITY Mouse IS SC_MODULE(Mouse)
SC_METHOD(Phone); sensitive<<ring;
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Declaration
entity my_module is [ports] end my_name SC_MODULE(my_module) { [ports] [signals] [modules] [processes (decl.)] SC_CTOR(my_module){ [processes (sensitivity)] } };
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architecture my_arch of my_module is [components] [types] [signals] begin [processes (all)] [combinatorial] end
[processes (implementation)]
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Entity / Ports
entity my_name is port( ... [ports] ); end my_name SC_MODULE(my_name) { [ports] };
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Hierarchy
architecture my_arch of my_module is component child port(...); end component; Begin child_inst : child port map( in => signal1; ... ); ...
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#include "child.h" //decl SC_MODULE(my_module) { child* child_inst; SC_CTOR{ child_inst = new child; child_inst.in->(signal1); ... } };
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Processes
process my_process (clk, reset) if (reset) ... elseif(clk'event and clk=='1') ... endif void my_process(); SC_CTOR(){ SC_METHOD(my_process); sensitive_pos<<clk; sensitive<<reset; }
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Outline
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A C++ library
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Classes that implement hardware datatypes and concepts A simulation kernel: registering functions in order to allow "parallel" execution. Possibility to extend with own datatypes, concepts
Support for own methodology Support for own libraries Support all C/C++ you want
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A C++ libray
Some C++ constructs are replaced by macro's The module properties and functions are in fact inherited. HDL: access through ports C++: member access
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SC_MODULE(my_module) { SC_CTOR(my_module){}; };
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Outline
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SystemC advantages
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SystemC advantages
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Verification
System testbench can be applied at each level of abstraction
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SystemC advantages
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Standard
Exchange models with "Hardware" behaviour
hierarchy Data-types clock / timed etc
Synthesisable subset
It is possible to synthesise from SystemC code, but only from the RTL subset. It is possible to use a SystemC to VHDL/Verilog converter and to build a design flow above current RTL design flow
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Outline
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SystemC drawbacks
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Synthesis
Tool support, model availability, etc
Debugging
Tools debug C++, not SystemC
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SystemC drawbacks
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Beware that the OSCI reference simulator is not optimised for speed -> vendor SystemC kernel?
Some limitations
No dynamic instantiation of modules (logic from a purely hardware point of view)
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SystemC drawbacks
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Adoption?
There are alternatives:
Modified HDL: SystemVerilog Other C based languages: Handel-C Direct C synthesis Other high level languages: pure C++, Matlab Other verification languages
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Outline
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Perspectives
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Tools
EDA use custom languages, custom tools SystemC allows to rely heavily on software tools (compare number of HDL users to software users)
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Perspectives
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CASE tools
Versionning (also works with VHDL) Documentation: generate (HTML) documentation from code UML: standard graphical representation UML: coding rules, partial C++ code generation
State machines Classes Sequence diagrams Structured classes (new in UML2)
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Perspectives
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SystemC is C++ but codesign (HW-SW) is not trivial: you have to set-up your how methodology (but easier with a single language) Extended synthesisable subset
Templates Inheritance
Use / Adoption
See Doulos survey...
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Follow up
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Conclusion?
first see other presentations...
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