Datasheet - HK Emc2302 1 Aizl TR 4570526

EMC2302
Dual RPM-Based PWM

Fan Controller
PRODUCT FEATURES Datasheet
General Description Features

The EMC2302 is an SMBus compliant fan controller with Two Programmable Fan Control circuits (EMC2302)
up to two independently controlled PWM fan drivers. — 4-wire fan compatible
Each fan driver is controlled by a programmable — High speed PWM (26 kHz)
— Low speed PWM (9.5Hz - 2240 Hz)
frequency PWM driver and Fan Speed Control algorithm
— Optional detection of aging fans
that operates in either a closed loop fashion or as a — Fan Spin Up Control and Ramp Rate Control
directly PWM-controlled device. — Alert on Fan Stall
The closed loop Fan Speed Control algorithm (FSC) has Watchdog Timer
the capability to detect aging fans and alert the system. RPM-based fan control algorithm
It will likewise detect stalled or locked fans and trigger — 0.5% accuracy from 500 RPM to 16k RPM (external
an interrupt. crystal oscillator)
— 1% accuracy from 500 RPM to 16k RPM (internal clock)
Additionally, the EMC2302 offers a clock output so that SMBus 2.0 Compliant
multiple devices may be chained and slaved to the — SMBus Alert compatible
same clock source for optimal performance in large CLK Pin can provide a clock source output
distributed systems. Available in a 10-pin MSOP Lead-free RoHS
Compliant package
Applications
Servers
Projectors
Industrial and Networking Equipment
Notebook Computers
Block Diagram
CLK
TACH1
Tachometer
Tach
Limit
Measurement
Registers
TACH2
SMCLK
SMBus
Slave SMDATA
Protocol
ALERT#
PWM1 Fan Speed Control Algorithm
PWM
Drivers
PWM2 Fan Speed Control Algorithm
SMSC EMC2302 DATASHEET Revision 1.1 (10-12-09)

Dual RPM-Based PWM Fan Controller
Datasheet
ORDER NUMBER:
ORDERING NUMBER PACKAGE FEATURES
EMC2302-1-AIZL-TR 10-pin MSOP (Lead-free Two RPM-based fan speed control

RoHS compliant) algorithms. SMBus address 0101_110(r/w)
EMC2302-2-AIZL-TR 10-pin MSOP (Lead-free Two RPM-based fan speed control

RoHS compliant) algorithms. SMBus address 0101_111(r/w)
This product meets the halogen maximum concentration values per IEC61249-2-21
For RoHS compliance and environmental information, please visit www.smsc.com/rohs
80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123
Copyright © 2009 SMSC or its subsidiaries. All rights reserved.

Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for
construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC
reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications
before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent
rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated
version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors
known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not
designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property
damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of
this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered
trademark of Standard Microsystems Corporation (“SMSC”). Product names and company names are the trademarks of their respective holders.
SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE
OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL
DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT;
TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD
TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Revision 1.1 (10-12-09) 2 SMSC EMC2302

DATASHEET
Datasheet
Table of Contents
Chapter 1 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Chapter 2 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.1 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 SMBus Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Chapter 3 Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1 System Management Bus Interface Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1.1 SMBus Start Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1.2 SMBus Address and RD / WR Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1.3 SMBus Data Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1.4 SMBus ACK and NACK Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1.5 SMBus Stop Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1.6 SMBus Time-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1.7 SMBus and I2C Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 SMBus Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2.1 Write Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2.2 Read Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2.3 Send Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2.4 Receive Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2.5 Block Write Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2.6 Block Read Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2.7 Alert Response Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Chapter 4 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.1 Fan Control Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.2 PWM Fan Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.3 RPM-based Fan Speed Control Algorithm (FSC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.3.1 Programming the RPM-based Fan Speed Control Algorithm . . . . . . . . . . . . . . . . . . . . . 18
4.4 Tachometer Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.4.1 Stalled Fan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.4.2 Aging Fan or Invalid Drive Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.5 CLK Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.5.1 External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.5.2 Internal Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.6 Spin Up Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.7 Ramp Rate Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.8 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.8.1 Power Up Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.8.2 Continuous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Chapter 5 Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.1 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1.1 Lock Entries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.2 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.3 Fan Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.3.1 Fan Status - 24h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.3.2 Fan Stall Status - 25h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.3.3 Fan Spin Status - 26h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.3.4 Fan Drive Fail Status - 27h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.4 Fan Interrupt Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
SMSC EMC2302 3 Revision 1.1 (10-12-09)

DATASHEET
Datasheet
5.5 PWM Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5.5.1 PWM Polarity Config - 2Ah . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.5.2 PWM Output Config - 2Bh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.6 PWM Base Frequency Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.7 Fan Setting Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.8 PWM Divide Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.9 Fan Configuration 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.10 Fan Configuration 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.11 Gain Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.12 Fan Spin Up Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.13 Fan Max Step Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.14 Fan Minimum Drive Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.15 Valid TACH Count Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.16 Fan Drive Fail Band Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.17 TACH Target Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.18 TACH Reading Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.19 Software Lock Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.20 Product ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.21 Manufacturer ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.22 Revision Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Chapter 6 Typical Operating Curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Chapter 7 Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7.1 EMC2302 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.2 Package Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

DATASHEET
Datasheet
List of Figures
Figure 1.1 EMC2302 Pin Diagram (10-Pin MSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3.1 SMBus Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 4.1 System Diagram of EMC2302 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 4.2 Spin Up Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 4.3 Ramp Rate Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 7.1 EMC2302 Package Drawing - 10-Pin MSOP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 7.2 EMC2302 Package Markings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

DATASHEET
Datasheet
List of Tables
Table 1.1 Pin Description for EMC2302 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 1.2 Pin Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 2.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 2.2 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 2.3 SMBus Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 3.1 Protocol Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 3.2 Write Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 3.3 Read Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 3.4 Send Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 3.5 Receive Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 3.6 Block Write Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 3.7 Block Read Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 3.8 Alert Response Address Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 4.1 Fan Controls Active for Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 5.1 EMC2302 Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 5.2 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 5.3 Fan Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 5.4 Fan Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 5.5 PWM Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 5.6 PWM Base Frequency Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 5.7 PWM_BASEx[1:0] Bit Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 5.8 Fan Driver Setting Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 5.9 PWM Divide Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 5.10 Fan Configuration 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 5.11 Range Decode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 5.12 Minimum Edges for Fan Rotation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 5.13 Update Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 5.14 Fan Configuration 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 5.15 Derivative Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 5.16 Error Range Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 5.17 Gain Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 5.18 Gain Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 5.19 Fan Spin Up Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 5.20 DRIVE_FAIL_CNT[1:0] Bit Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 5.21 Spin Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 5.22 Spin Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 5.23 Fan Max Step Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 5.24 Minimum Fan Drive Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 5.25 Valid TACH Count Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 5.26 Fan Drive Fail Band Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 5.27 TACH Target Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 5.28 TACH Reading Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 5.29 Software Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 5.30 Product ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 5.31 Manufacturer ID Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 5.32 Revision Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

DATASHEET
Datasheet
Chapter 1 Pin Description
SMDATA 1 10 ALERT#
SMCLK 2 9 CLK
EMC2302
VDD 3 8 TACH2
10-MSOP
GND 4 7 PWM2
PWM1 5 6 TACH1
Figure 1.1 EMC2302 Pin Diagram (10-Pin MSOP)
Table 1.1 Pin Description for EMC2302
PIN NUMBER PIN NAME PIN FUNCTION PIN TYPE
SMBus data input/output - requires

1 SMDATA DIOD (5V)
external pull-up resistor
SMBus clock input - requires external

2 SMCLK DI (5V)
pull-up resistor
3 VDD Power Supply Power
4 GND Ground Power
Push-Pull PWM output driver for Fan 1 DO

5 PWM1
Open Drain PWM output driver for Fan 1 OD (5V)
Open drain tachometer input for Fan 1-

6 TACH1 DI (5V)
requires pull-up resistor
Push-Pull PWM output driver for Fan 2 DO

7 PWM2
Open Drain PWM output driver for Fan 2 OD (5V)
Open drain tachometer input for Fan 2 -

8 TACH2 DI (5V)
requires pull-up resistor

DATASHEET
Datasheet
Table 1.1 Pin Description for EMC2302 (continued)
PIN NUMBER PIN NAME PIN FUNCTION PIN TYPE
Clock input for tachometer measurement DI (5V)
9 CLK Push Pull Clock output to other fan

controllers to synchronize Fan Speed DO
Control
Active low interrupt - requires external

10 ALERT# OD (5V)
pull-up resistor.
The pin types are described in detail below. All pins labeled with (5V) are 5V tolerant.
APPLICATION NOTE: For the 5V tolerant pins that have a pull-up resistor, the voltage difference between VDD and
the 5V tolerant pad must never be more than 3.6V.
Table 1.2 Pin Types
PIN TYPE DESCRIPTION
Power This pin is used to supply power or ground to the device.
Digital Input - this pin is used as a digital input. This pin is

DI 5V tolerant.
Push / Pull Digital Output - this pin is used as a digital

DO output. It can both source and sink current.
Digital Input / Open Drain Output this pin is used as a

DIOD digital I/O. When it is used as an output, it is open drain
and requires a pull-up resistor. This pin is 5V tolerant.
Open Drain Digital Output - this pin is used as a digital

OD output. It is open drain and requires a pull-up resistor. This
pin is 5V tolerant.

DATASHEET
Datasheet
Chapter 2 Electrical Specifications
Table 2.1 Absolute Maximum Ratings
Voltage on 5V tolerant pins (V5VT_pin) -0.3 to 5.5 V
Voltage on 5V tolerant pins (|V5VT_pin - VDD|) (see Note 2.1) 0 to 3.6 V
Voltage on VDD pin -0.3 to 4 V
Voltage on any other pin to GND -0.3 to VDD + 0.3 V
Package Thermal Restance - Junction to Ambient (θJA) 132 °C/W
Operating Ambient Temperature Range -40 to 125 °C
Storage Temperature Range -55 to 150 °C
ESD Rating, All Pins, HBM 2000 V
Note: Stresses above those listed could cause permanent damage to the device. This is a stress
rating only and functional operation of the device at any other condition above those indicated
in the operation sections of this specification is not implied.
Note 2.1 For the 5V tolerant pins that have a pull-up resistor, the pull-up voltage must not exceed
3.6V when the EMC2302 is unpowered.
2.1 Electrical Specifications
Table 2.2 Electrical Specifications
VDD = 3V to 3.6V, TA = -40°C to 125°C, all Typical values at TA = 27°C unless otherwise noted.
CHARACTERISTIC SYMBOL MIN TYP MAX UNIT CONDITIONS
DC Power
Supply Voltage VDD 3 3.3 3.6 V
Supply Current IDD 400 550 uA
PWM Fan Driver
PWM Resolution PWM 256 Steps
PWM Duty Cycle DUTY 0 100 %
RPM-based Fan Controller
Tachometer Range TACH 480 16000 RPM
Tachometer Setting ΔTACH ±0.5 ±1 % External oscillator 32.768kHz

Accuracy
ΔTACH ±1 ±2 % Internal Oscillator
Input High Voltage VIH 2.0 V
Input Low Voltage VIL 0.8 V

DATASHEET
Datasheet
Table 2.2 Electrical Specifications (continued)
VDD = 3V to 3.6V, TA = -40°C to 125°C, all Typical values at TA = 27°C unless otherwise noted.
CHARACTERISTIC SYMBOL MIN TYP MAX UNIT CONDITIONS
Output High Voltage VDD - 8 mA current drive

VOH V
0.4
Output Low Voltage VOL 0.4 V 8 mA current sink
Leakage current ALERT# pin

ILEAK Powered and unpowered
±5 uA 0°C < TA < 85°C
pull-up voltage < 3.6V
Note 2.2 All voltages are relative to ground.
2.2 SMBus Electrical Specifications
Table 2.3 SMBus Electrical Specifications
VDD= 3V to 3.6V, TA = -40°C to 125°C Typical values are at TA = 27°C unless otherwise noted.
CHARACTERISTIC SYMBOL MIN TYP MAX UNITS CONDITIONS
SMBus Interface
Input High Voltage VIH 2.0 V
Input Low Voltage VIL 0.8 V
Output High Voltage VDD

VOH V
- 0.4
Output Low Voltage VOL 0.4 V 4 mA current sink
Input High/Low Current Powered and unpowered

IIH / IIL ±5 uA 0°C < TA < 85°C
Input Capacitance CIN 5 pF
SMBus Timing
Clock Frequency fSMB 10 400 kHz
Spike Suppression tSP 50 ns
Bus free time Start to tBUF 1.3 us

Stop
Setup Time: Start tSU:STA 0.6 us
Setup Time: Stop tSU:STP 0.6 us
Data Hold Time tHD:DAT 0.6 6 us
Data Setup Time tSU:DAT 0.6 72 us

DATASHEET
Datasheet
Table 2.3 SMBus Electrical Specifications (continued)
VDD= 3V to 3.6V, TA = -40°C to 125°C Typical values are at TA = 27°C unless otherwise noted.
CHARACTERISTIC SYMBOL MIN TYP MAX UNITS CONDITIONS
Clock Low Period tLOW 1.3 us
Clock High Period tHIGH 0.6 us
Clock/Data Fall time tFALL 300 ns Min = 20+0.1CLOAD ns
Clock/Data Rise time tRISE 300 ns Min = 20+0.1CLOAD ns
Capacitive Load CLOAD 400 pF per bus line

DATASHEET
Datasheet
Chapter 3 Communications
3.1 System Management Bus Interface Protocol

The EMC2302 communicates with a host controller, such as an SMSC SIO, through the SMBus. The
SMBus is a two-wire serial communication protocol between a computer host and its peripheral
devices. A detailed timing diagram is shown in Figure 3.1. Stretching of the SMCLK signal is supported;
however, the EMC2302 will not stretch the clock signal.
TLOW THIGH THD:STA

TSU:STO
TRISE TFALL
SMCLK
THD:STA THD:DAT TSU:DAT TSU:STA
SMDATA
TBUF
P S S - Start Condition S P - Stop Condition P
Figure 3.1 SMBus Timing Diagram
3.1.1 SMBus Start Bit

The SMBus Start bit is defined as a transition of the SMBus Data line from a logic ‘1’ state to a logic
‘0’ state while the SMBus Clock line is in a logic ‘1’ state.
3.1.2 SMBus Address and RD / WR Bit

The SMBus Address Byte consists of the 7-bit client address followed by a RD / WR indicator bit. If
this RD / WR bit is a logic ‘0’, then the SMBus Host is writing data to the client device. If this RD / WR
bit is a logic ‘1’, then the SMBus Host is reading data from the client device.
The EMC2103-1 SMBus address is set at 0101_110(r/w)b.
The EMC2103-2 SMBus address is set at 0101_111(r/w)b.
3.1.3 SMBus Data Bytes

All SMBus Data bytes are sent most significant bit first and composed of 8-bits of information.
3.1.4 SMBus ACK and NACK Bits

The SMBus client will acknowledge all data bytes that it receives (as well as the client address if it
matches and the ARA address if the ALERT# pin is asserted). This is done by the client device pulling
the SMBus Data line low after the 8th bit of each byte that is transmitted.
The Host will NACK (not acknowledge) the data received from the client by holding the SMBus data
line high after the 8th data bit has been sent.

DATASHEET
Datasheet
3.1.5 SMBus Stop Bit

The SMBus Stop bit is defined as a transition of the SMBus Data line from a logic ‘0’ state to a logic
‘1’ state while the SMBus clock line is in a logic ‘1’ state. When the EMC2302 detects an SMBus Stop
bit has been communicating with the SMBus protocol, it will reset its client interface and prepare to
receive further communications.
3.1.6 SMBus Time-out

The EMC2302 includes an SMBus timeout feature. Following a 30ms period of inactivity on the
SMBus, the device will time-out and reset the SMBus interface.
The SMBus timeout feature is disabled by default and can be enabled via clearing the DIS_TO bit in
the Configuration register (20h).
3.1.7 SMBus and I2C Compliance

The major difference between SMBus and I2C devices is highlighted here. For complete compliance
information refer to the SMBus 2.0 specification.
1. Minimum frequency for SMBus communications is 10kHz (I2C has no minimum frequency).
2. The slave protocol will reset if the clock is held low for longer than 30ms (I2C has no timeout).
3. The slave protocol will reset if both the clock and data lines are held high for longer than 150us.
4. I2C devices do not support the Alert Response Address functionality (which is optional for SMBus).
5. The Block Read and Block Write protocols are only compliant with I2C data formatting. They do
not support SMBus formatting for Block Read and Block Write protocols.
3.2 SMBus Protocols

The EMC2302 is SMBus 2.0 compatible and supports Send Byte, Read Byte, Receive Byte and Write
Byte as valid protocols as shown below. It will respond to the Alert Response Address protocol but is
not in full compliance.
All of the below protocols use the convention in Table 3.1. When reading the protocol blocks, the value
of YYYY_YYYb should be replaced with the respective SMBus addresses.
Table 3.1 Protocol Format
DATA SENT DATA SENT TO

TO DEVICE THE HOST
# of bits sent # of bits sent
3.2.1 Write Byte

The Write Byte is used to write one byte of data to the registers as shown below Table 3.2.
Table 3.2 Write Byte Protocol
SLAVE REGISTER REGISTER

START ADDRESS WR ACK ADDRESS ACK DATA ACK STOP
1 -> 0 YYYY_YYYb 0 0 XXh 0 XXh 0 0 -> 1

DATASHEET
Datasheet
3.2.2 Read Byte

The Read Byte protocol is used to read one byte of data from the registers as shown in Table 3.3.
Table 3.3 Read Byte Protocol
START SLAVE WR ACK Register ACK START Slave RD ACK Register NACK STOP
ADDRESS Address Address Data
1 -> 0 YYYY_YYYb 0 0 XXh 0 0 -> 1 YYYY_YYYb 1 0 XXh 1 0 -> 1
3.2.3 Send Byte

The Send Byte protocol is used to set the internal address register pointer to the correct address
location. No data is transferred during the Send Byte protocol as shown in Table 3.4.
Table 3.4 Send Byte Protocol
SLAVE REGISTER
START ADDRESS WR ACK ADDRESS ACK STOP
1 -> 0 YYYY_YYYb 0 0 XXh 0 0 -> 1
3.2.4 Receive Byte

The Receive Byte protocol is used to read data from a register when the internal register address
pointer is known to be at the right location (e.g. set via Send Byte). This is used for consecutive reads
of the same register as shown in Table 3.5.
Table 3.5 Receive Byte Protocol
SLAVE
START ADDRESS RD ACK REGISTER DATA NACK STOP
1 -> 0 YYYY_YYYb 1 0 XXh 1 0 -> 1
3.2.5 Block Write Protocol

The Block Write is used to write multiple data bytes to a group of contiguous registers as shown in
Table 3.6. It is an extension of the Write Byte Protocol.
Table 3.6 Block Write Protocol
SLAVE REGISTER REGISTER

START ADDRESS WR ACK ADDRESS ACK DATA ACK
1 ->0 YYYY_YYYb 0 0 XXh 0 XXh 0
REGISTER REGISTER REGISTER

DATA ACK DATA ACK ... DATA ACK STOP
XXh 0 XXh 0 ... XXh 0 0 -> 1

DATASHEET
Datasheet
3.2.6 Block Read Protocol

The Block Read is used to read multiple data bytes from a group of contiguous registers as shown in
Table 3.7. It is an extension of the Read Byte Protocol.
Table 3.7 Block Read Protocol
START SLAVE WR ACK REGISTER ACK START SLAVE RD ACK REGISTER

ADDRESS ADDRESS ADDRESS DATA
1->0 YYYY_YYYb 0 0 XXh 0 1 ->0 YYYY_YYYb 1 0 XXh

ACK REGISTER ACK REGISTER ACK REGISTER ACK ... REGISTER NACK STOP
DATA DATA DATA DATA
0 XXh 0 XXh 0 XXh 0 ... XXh 1 0 -> 1
3.2.7 Alert Response Address

The ALERT# output can be used as a processor interrupt or as an SMBus Alert when configured to
operate as an interrupt.
When it detects that the ALERT# pin is asserted, the host will send the Alert Response Address (ARA)
to the general address of 0001_100xb. All devices with active interrupts will respond with their client
address as shown in Table 3.8.
Table 3.8 Alert Response Address Protocol
ALERT
RESPONSE DEVICE
START ADDRESS RD ACK ADDRESS NACK STOP
1 -> 0 0001_100b 1 0 YYYY_YYYb 1 0 -> 1
The EMC2302 will respond to the ARA in the following way if the ALERT# pin is asserted.
1. Send Slave Address and verify that full slave address was sent (i.e. the SMBus communication
from the device was not prematurely stopped due to a bus contention event).
2. Set the MASK bit to clear the ALERT# pin.

DATASHEET
Datasheet
Chapter 4 Product Description
The EMC2302 is an SMBus compliant fan controller with two programmable frequency PWM fan
drivers. The fan drivers can be operated using two modes: the RPM-based Fan Speed Control
Algorithm or the direct fan drive setting.
Figure 4.1 shows a system diagram of the EMC2302.
3.3V
VDD
tachometer
SMCLK TACH2
MCU SMDATA Drive
PWM2
Circuit
ALERT#
32.768KHz Clock CLK

Input or Output
EMC2302 tachometer
TACH1
Drive
PWM1
Circuit
GND
Figure 4.1 System Diagram of EMC2302
4.1 Fan Control Modes of Operation

The EMC2302 has two modes of operation for each fan driver. Each mode of operation uses the Ramp
Rate control and Spin Up Routine.
1. Direct Setting Mode - in this mode of operation, the user directly controls the fan drive setting.
Updating the Fan Driver Setting Register (see Section 5.7) will instantly update the PWM fan drive.
Ramp Rate control is optional and enabled via the EN_RRC bits.
Whenever the Direct Setting Mode is enabled, the current drive will be changed to what was
last written into the Fan Driver Setting Register.
2. Fan Speed Control Mode (FSC) - in this mode of operation, the user determines a target
tachometer count and the PWM drive setting is automatically updated to achieve this target speed.
The algorithm uses the Spin Up Routine and has user definable ramp rate controls.
This mode is enabled setting the EN_ALGO bit in the Fan Configuration Register.

DATASHEET
Datasheet
Table 4.1 Fan Controls Active for Operating Mode
DIRECT SETTING MODE FSC MODE
Fan Driver Setting (read / write) Fan Driver Setting (read only)
EDGES[1:0] EDGES[1:0]
(Fan Configuration)
- RANGE[1:0]
(Fan Configuration)
UPDATE[2:0] UPDATE[2:0]
(Fan Configuration) (Fan Configuration)
LEVEL LEVEL
(Spin Up Configuration) (Spin Up Configuration)
SPINUP_TIME[1:0] SPINUP_TIME[1:0]
(Spin Up Configuration) (Spin Up Configuration)
Fan Step Fan Step
- Fan Minimum Drive
Valid TACH Count Valid TACH Count
- TACH Target (read / write)
TACH Reading TACH Reading
- DRIVE_FAIL_CNT[1:0] and Drive Band Fail Registers
4.2 PWM Fan Driver

The EMC2302 supports 2 PWM output drivers. Each output driver can be configured to operate as an
open-drain (default) or push-pull driver and each driver can be configured with normal or inverse
polarity. Additionally, the PWM frequencies are independently programmable with ranges from 9.5Hz
to 26kHz in four programmable frequency bands.
4.3 RPM-based Fan Speed Control Algorithm (FSC)

The EMC2302 includes 2 RPM-based Fan Speed Control Algorithms. Each algorithm operates
independently and controls a separate fan driver. Each algorithm is controlled manually (by setting the
target fan speed).
This fan control algorithm uses Proportional, Integral, and Derivative terms to automatically approach
and maintain the system’s desired fan speed to an accuracy directly proportional to the accuracy of
the clock source.
The desired tachometer count is set by the user inputting the desired number of 32.768kHz cycles that
occur per fan revolution. This is done by manually setting the TACH Target Register. The user may
change the target count at any time. The user may also set the target count to FFh in order to disable
the fan driver for lower current operation.
For example, if a desired RPM rate for a 2-pole fan is 3000 RPMs, then the user would input the
hexidecimal equivalent of 1296 (51h in the TACH Target Register). This number represents the number
of 32.768KHz cycles that would occur during the time it takes the fan to complete a single revolution
when it is spinning at 3000RPMs.

DATASHEET
Datasheet
The EMC2302’s RPM-based Fan Speed Control Algorithm has programmable configuration settings
for parameters such as ramp-rate control and spin up conditions. The fan driver automatically detects
and attempts to alleviate a stalled/stuck fan condition while also asserting the ALERT# pin. The
EMC2302 works with fans that operate up to 16,000 RPMs and provide a valid tachometer signal.
The fan controller will function either with an externally supplied 32.768kHz clock source or with it’s
own internal 32kHz oscillator depending on the required accuracy. The EMC2302 offers a clock output
that enables additional devices to be slaved to the same clock source.
4.3.1 Programming the RPM-based Fan Speed Control Algorithm

The RPM-based Fan Speed Control Algorithm is disabled upon device power up. The following
registers control the algorithm. The EMC2302 fan control registers are pre-loaded with defaults that
will work for a wide variety of fans so only the TACH Target Register is required to set a fan speed.
The other fan control registers can be used to fine-tune the algorithm behavior based on application
requirements.
Note that steps 1 - 6 are optional and need only be performed if the default settings do not provide
the desired fan response.
1. Set the Spin Up Configuration Register to the Spin Up Level and Spin Time desired.
2. Set the Fan Step Register to the desired step size.

3. Set the Fan Minimum Drive Register to the minimum drive value that will maintain fan operation.
4. Set the Update Time and Edges options in the Fan Configuration Register.
5. Set the Valid TACH Count Register to the highest tach count that indicates the fan is spinning.
Refer to AN17.4 RPM to TACH Counts Conversion for examples and tables for supported RPM
ranges (500, 1k, 2k, 4k).
6. Set the TACH Target Register to the desired tachometer count.
7. Enable the RPM-based Fan Speed Control Algorithm by setting the EN_ALGO bit.
4.4 Tachometer Measurement

The tachometer measurement circuitry is used in conjunction with the RPM-based Fan Speed Control
Algorithm to update the fan driver output. Additionally, it can be used in Direct Setting mode as a
diagnostic for host based fan control.
This method monitors the TACHx signal in real time. It constantly updates the tachometer
measurement by reporting the number of clocks between a user programmed number of edges on the
TACHx signal (see Table 5.12).
The tachometer measurement provides fast response times for the RPM-based Fan Speed Control
Algorithm and the data is presented as a count value that represents the fan RPM period.
APPLICATION NOTE: The tachometer measurement method works independently of the drive settings. If the
device is put into Direct Setting and the fan drive is set at a level that is lower than the fan
can operate (including zero drive), then the tachometer measurement may signal a Stalled
Fan condition and assert an interrupt.
4.4.1 Stalled Fan

A Stalled fan is detected if the tach counter exceeds the user-programmable Valid TACH Count setting.
If a stall is detected, the device will flag the fan as stalled and trigger an interrupt.
If the RPM-based Fan Speed Control Algorithm is enabled, the algorithm will automatically attempt to
restart the fan until it detects a valid tachometer level or is disabled.

DATASHEET
Datasheet
The FAN_STALL Status bit indicates that a stalled fan was detected. This bit is checked conditionally
depending on the mode of operation.
Whenever the Direct Setting Mode or the Spin Up Routine is enabled, the FAN_STALL interrupt
will be masked for the duration of the programmed Spin Up Time (see Table 5.22) to allow the fan
to reach a valid speed without generating unnecessary interrupts.
In Direct Setting Mode, whenever the TACH Reading Register value exceeds the Valid TACH Count
Register setting, the FAN_STALL status bit will be set.
When using the RPM-based Fan Speed Control Algorithm, the stalled fan condition is checked
whenever the Update Time is met and the fan drive setting is updated. It is not a continuous check.
4.4.2 Aging Fan or Invalid Drive Detection

This is useful to detect aging fan conditions (where the fan’s natural maximum speed degrades over
time) or a speed setting that is faster than the fan is capable of. The EMC2302 contains circuitry that
detects that the programmed fan speed can be reached by the fan. If the target fan speed cannot be
reached within a user defined band of tach counts at maximum drive, the DRIVE_FAIL status bits are
set and the ALERT# pin is asserted.
4.5 CLK Pin

The CLK pin has multiple functionality as determined by the settings of the Configuration register.
4.5.1 External Clock

The EMC2302 allows the user to choose between supplying an external 32.768kHz clock or use of
the internal 32kHz oscillator to measure the tachometer signal. This clock source is used by the RPM-
based Fan Speed Control Algorithm to calculate the current fan speed. This fan controller accuracy is
directly proportional to the accuracy of the clock source.
When this function is used, the external clock is driven into the device via the CLK pin.
4.5.2 Internal Clock

Alternately, the EMC2302 may be configured to use its internal clock as a clock output to drive other
fan driver devices. When configured to operate in this mode, the device uses its internal clock for
tachometer reading and drives the CLK pin using a push-pull driver.
4.6 Spin Up Routine

The EMC2302 also contains programmable circuitry to control the spin up behavior of the fan driver
to ensure proper fan operation.
The Spin Up Routine is initiated in Direct Setting mode when the setting value changes from 00h to
anything else.
When the Fan Speed Control Algorithm is enabled, the Spin Up Routine is initiated under the following
conditions:
1. The TACH Target Register value changes from a value of FFh to a value that is less than the Valid
TACH Count (see Section 5.15).
2. The RPM-based Fan Speed Control Algorithm’s measured TACH Reading Register value is greater
than the Valid TACH Count setting.
When the Spin Up Routine is operating, the fan driver is set to full scale (optional) for one quarter of
the total user defined spin up time. For the remaining spin up time, the fan driver output is set at a
user defined level (30% through 65% drive).

DATASHEET
Datasheet
After the Spin Up Routine has finished, the EMC2302 measures the TACHx signal. If the measured
TACH Reading Register value is higher than the Valid TACH Count Register setting, the FAN_SPIN
status bit is set and the Spin Up Routine will automatically attempt to restart the fan.
Figure 4.2 shows an example of the Spin Up Routine in response to a programmed fan speed change
based on the first condition above.
100%
(optional)
30% through 65%

Fan Step
New Target Count

Algorithm controlled drive
Prev Target
Count = FFh
¼ of Spin Up Time
Update Time
Spin Up Time
Target Count Check TACH Target Count
Changed Reached
Figure 4.2 Spin Up Routine
4.7 Ramp Rate Control

The Fan Driver can be configured with automatic ramp rate control. Ramp rate control is accomplished
by adjusting the drive output settings based on the Maximum Fan Step Register settings and the
Update Time settings.
If the RPM-based Fan Speed Control Algorithm is used, then this ramp rate control is automatically
used. The user programs a maximum step size for the fan drive setting and an update time. The
update time varies from 100ms to 1.6s while the fan drive maximum step can vary from 1 count to 31
counts.
When a new fan drive setting is entered, the delta from the next fan drive setting and the previous fan
drive setting is determined. If this delta is greater than the Max Step settings, then the fan drive setting
is incrementally adjusted every 100ms to 1.6s as determined by the Update Time until the target fan
drive setting is reached. See Figure 4.3.

DATASHEET
Datasheet
Next Desired
Setting
Max
Step
Max
Step
Previous
Setting
Update Update
Time Time
Setting Changed
Figure 4.3 Ramp Rate Control
4.8 Watchdog Timer

The EMC2302 contains an internal Watchdog Timer for all fan drivers. The Watchdog timer monitors
the SMBus traffic for signs of activity and works in two different modes based upon device operation.
These modes are Power Up Operation and Continuous Operation as described below.
For either mode of operation, if four (4) seconds elapse without activity detected by the host, then the
watchdog will be triggered and the following will occur:
1. The WATCH status bit will be set.
2. The fan driver will be set to full scale drive. It will remain at full scale drive until it is disabled.
APPLICATION NOTE: When the Watchdog timer is activated, the Fan Speed Control Algorithm is automatically
disabled. Disabling the Watchdog will not automatically set the fan drive nor re-activate the
Fan Speed Control Algorithm. This must be done manually.
4.8.1 Power Up Operation

The Watchdog Timer only starts immediately after power-up. Once it has been triggered or deactivated,
it will not restart although it can be configured to operate in Continuous operation. While the Watchdog
timer is active, the device will not check for a Stalled Fan condition.
In the Power Up Operation, the Watchdog Timer is disabled by any of the following actions:
1. Writing the Fan Setting Register will disable the Watchdog Timer.
2. Enabling the RPM-based Fan Speed Control Algorithm by setting the EN_ALGO bit will disable the
Watchdog Timer. The fan driver will be set based on the RPM-based Fan Speed Control Algorithm.
Writing any other configuration registers will not disable the Watchdog Timer upon power up.

DATASHEET
Datasheet
4.8.2 Continuous Operation

When configured to operate in Continuous Operation, the Watchdog timer will start immediately. The
timer will be reset by any access (read or write) to the SMBus register set. The four second Watchdog
timer will restart upon completion of SMBus activity.

DATASHEET
Datasheet
Chapter 5 Register Set
5.1 Register Map

The following registers are accessible through the SMBus Interface. All register bits marked as ‘-’ will
always read ‘0’. A write to these bits will have no effect.
Table 5.1 EMC2302 Register Set
REGISTER DEFAULT
ADDR R/W NAME FUNCTION VALUE LOCK PAGE
Configuration and control
Configures the clocking and watchdog

20h R/W Configuration 40h SWL Page 25
functionality
Stores the status bits for the RPM-

24h R-C Fan Status 00h No Page 26
based Fan Speed Control Algorithm
Stores status bits associated with a

25h R-C Fan Stall Status 00h No Page 26
stalled fan
Stores status bits associated with a

26h R-C Fan Spin Status 00h No Page 26
spin-up failure
Stores status bits associated with drive

27h R-C Drive Fail Status 00h No Page 26
failure
Fan Interrupt Controls the masking of interrupts on all

29h R/W 00h No Page 27
Enable Register fan related channels
PWM Polarity
2Ah R/W Configures Polarity of all PWM drivers 00h No Page 28
Config
PWM Output
2Bh R/W Configures Output type of PWM drivers 00h No Page 28
Config
PWM Base Selects the base frequency for PWM

2Dh R/W 00h No Page 28
Frequency output 2
Fan 1 Control Registers
Always displays the most recent fan

driver input setting for Fan 1. If the
30h R/W Fan 1 Setting RPM-based Fan Speed Control 00h No Page 29
Algorithm is disabled, allows direct user
control of the fan driver.
Stores the divide ratio to set the

31h R/W PWM 1 Divide 01h No Page 29
frequency for Fan 1
Sets configuration values for the RPM-

Fan 1
32h R/W based Fan Speed Control Algorithm for 2Bh No Page 30
Configuration 1
the Fan 1 driver
Fan 1 Sets additional configuration values for

33h R/W 28h SWL Page 31
Configuration 2 the Fan 1 driver
Holds the gain terms used by the RPM-

35h R/W Gain 1 based Fan Speed Control Algorithm for 2Ah SWL Page 33
the Fan 1 driver

DATASHEET
Datasheet
Table 5.1 EMC2302 Register Set (continued)
REGISTER DEFAULT
Fan 1 Spin Up Sets the configuration values for Spin

Configuration Up Routine of the Fan 1 driver
Sets the maximum change per update

37h R/W Fan 1 Max Step 10h SWL Page 35
for the Fan 1 driver
Fan 1 Minimum Sets the minimum drive value for the 66h
38h R/W SWL Page 36
Drive Fan 1 driver (40%)
Fan 1 Valid TACH Holds the tachometer reading that

39h R/W F5h SWL Page 36
Count indicates Fan 1 is spinning properly
Fan 1 Drive Fail

3Ah R/W Stores the number of Tach counts used 00h SWL
Band Low Byte to determine how the actual fan speed
Page 37
must match the target fan speed at full
Fan 1 Drive Fail
3Bh R/W scale drive 00h SWL
Band High Byte
TACH 1 Target Holds the target tachometer reading low

3Ch R/W F8h No Page 37
Low Byte byte for Fan 1
TACH 1 Target Holds the target tachometer reading

3Dh R/W FFh No Page 37
High Byte high byte for Fan 1
TACH 1 Reading Holds the tachometer reading high byte

3Eh R FFh No Page 38
High Byte for Fan 1
TACH 1 Reading Holds the tachometer reading low byte

3Fh R F8h No Page 38
Low Byte for Fan 1
Fan 2 Control Registers
Always displays the most recent fan

driver input setting for Fan 2. If the
40h R/W Fan 2 Setting RPM-based Fan Speed Control 00h No Page 29
Algorithm is disabled, allows direct user
control of the fan driver.
Stores the divide ratio to set the

41h R/W PWM 2 Divide 01h No Page 29
frequency for Fan 2
Sets configuration values for the RPM-

Fan 2
42h R/W based Fan Speed Control Algorithm for 2Bh No Page 30
Configuration1
Fan 2
Fan 2 Sets additional configuration values for

Configuration 2 the Fan 2 driver
Holds the gain terms used by the RPM-

45h R/W Gain 2 based Fan Speed Control Algorithm for 2Ah SWL Page 33
Fan 2
Fan 2 Spin Up Sets the configuration values for Spin

Configuration Up Routine of the Fan 2 driver
Sets the maximum change per update

47h R/W Fan 2 Max Step 10h SWL Page 35
for Fan 2
Fan 2 Minimum Sets the minimum drive value for the 66h
48h R/W SWL Page 36
Drive Fan 2 driver (40%)

DATASHEET
Datasheet
Table 5.1 EMC2302 Register Set (continued)
REGISTER DEFAULT
Fan 2 Valid TACH Holds the tachometer reading that

49h R/W F5h SWL Page 36
Count indicates Fan 2 is spinning properly
Fan 2 Drive Fail

4Ah R/W Stores the number of Tach counts used 00h SWL
Band Low Byte to determine how the actual fan speed
Page 37
must match the target fan speed at full
Fan 2 Drive Fail
4Bh R/W scale drive 00h SWL
Band High Byte
TACH 2 Target Holds the target tachometer setting low

4Ch R/W F8h No Page 37
Low Byte byte for Fan 2
TACH 2 Target Holds the target tachometer setting high

4Dh R/W FFh No Page 37
High Byte byte for Fan 2
TACH 2 Reading Holds the tachometer reading high byte

4Eh R FFh No Page 38
High Byte for Fan 2
TACH 2 Reading Holds the tachometer reading low byte

4Fh R F8h No Page 38
Low Byte for Fan 2
Lock Register
EF R/W Software Lock Locks all SWL registers 00h SWL Page 39
Revision Registers
FDh R Product ID Stores the unique Product ID 36h No Page 39
FEh R Manufacturer ID Stores the Manufacturer ID 5Dh No Page 39
FFh R Revision Revision 80h No Page 39
During Power-On-Reset (POR), the default values are stored in the registers. A POR is initiated when
power is first applied to the part and the voltage on the VDD supply surpasses the POR level as
specified in the electrical characteristics. Any reads to undefined registers will return 00h. Writes to
undefined registers will not have an effect.
5.1.1 Lock Entries

The Lock Column describes the locking mechanism, if any, used for individual registers. All SWL
registers are Software Locked and therefore made read-only when the LOCK bit is set.
5.2 Configuration Register
Table 5.2 Configuration Register
ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT
USE_
DR_EXT_
20h R/W Configuration MASK DIS_TO WD_EN - - - EXT_ 40h
CLK
CLK
The Configuration Register controls the basic functionality of the EMC2302. The bits are described
below. The Configuration Register is software locked.
Bit 7 - MASK - Blocks the ALERT# pin from being asserted.

DATASHEET
Datasheet
‘0’ (default) - The ALERT# pin is unmasked. If any bit in either status register is set, the ALERT#
pins will be asserted (unless individually masked via the Mask Register).
‘1’ - The ALERT# pin is masked and will not be asserted.
Bit 6 - DIS_TO - Disables the SMBus timeout function for the SMBus client (if enabled).
‘0’ - The SMBus timeout function is enabled.
‘1’ (default) - The SMBus timeout function is disabled allowing the device to be fully I2C compliant.
Bit 5 - WD_EN - Enables the Watchdog timer to operate in Continuous Mode (see Section 4.8.2).
‘0’ (default) - The Watchdog timer does not operate continuously. It will function upon power up and
at no other time.
‘1’ - The Watchdog timer operates continuously as described in Section 4.8.
Bit 1 - DR_EXT_CLK - Enables the internal tachometer clock to be driven out on the CLK pin so that
multiple devices can be synced to the same source.
‘0’ (default) - The CLK pin acts as a clock input.
‘1’ - The CLK pin acts as a clock output and is a push-pull driver.
Bit 0 - USE_EXT_CLK - Enables the EMC2302 to use a clock present on the CLK pin as the
tachometer clock. If the DR_EXT_CLK bit is set, then this bit is ignored and the device will use the
internal oscillator.
‘0’ (default) - The EMC2302 will use its internal oscillator for all Tachometer measurements.
‘1’ - The EMC2302 will use the oscillator presented on the CLK pin for all Tachometer
measurements.
5.3 Fan Status Registers
Table 5.3 Fan Status Registers
DRIVE_ FAN_ FAN_

24h R-C Fan Status WATCH - - - - 00h
FAIL SPIN STALL
Fan Stall FAN2_ FAN1_

25h R-C - - - - - - 00h
Status STALL STALL
Fan Spin FAN2_ FAN1_

26h R-C - - - - - - 00h
Status SPIN SPIN
Fan Drive DRIVE_ DRIVE_

27h R-C - - - - - - 00h
Fail Status FAIL2 FAIL1
The Fan Status registers contain the status bits associated with each fan driver.
5.3.1 Fan Status - 24h

The Fan Status register indicates that one or both of the fan drivers has stalled or failed or that the
Watchdog Timer has expired (see Section 4.8).
Bit 7 - WATCH - Indicates that the Watchdog Timer has expired. When set, each fan is driven to 100%
duty cycle and will remain at 100% duty cycle until they are programmed. This bit is cleared when it
is read.

DATASHEET
Datasheet
Bit 2 - DRIVE_FAIL - Indicates that one or both fan drivers cannot meet the programmed fan speed
at maximum PWM duty cycle. This bit is set when any bit in the Fan Drive Fail Status register is set
and cleared when all bits in the Fan Drive Fail Status register are cleared.
Bit 1 - FAN_SPIN - Indicates that one or both fan drivers cannot spin up. This bit is set when any bit
in the Fan Spin Status register is set and cleared when all of the bits in the Fan Spin Status register
are cleared.
Bit 0 - FAN_STALL - Indicates that one or both fan drivers have stalled. This bit is set when any bit in
the Fan Stall Status register is set and cleared when all of the bits in the Fan Stall Status register are
cleared.
5.3.2 Fan Stall Status - 25h

The Fan Stall Status register indicates which fan driver has detected a stalled condition (see
Section 4.4.1). All bits are cleared upon a read if the error condition has been removed.
Bit 1 - FAN2_STALL - Indicates that Fan 2 has stalled.
Bit 0 - FAN1_STALL - Indicates that Fan 1 has stalled.
5.3.3 Fan Spin Status - 26h

The Fan Spin Status register indicates which fan driver has failed to spin-up (see Section 4.6). All bits
are cleared upon a read if the error condition has been removed.
Bit 1 - FAN2_SPIN - Indicates that Fan 2 has failed to spin up.
Bit 0 - FAN_SPIN - Indicates that Fan 1 has failed to spin up.
5.3.4 Fan Drive Fail Status - 27h

The Fan Drive Fail Status register indicates which fan driver cannot drive to the programmed speed
even at 100% duty cycle (see Section 4.4.2 and Section 5.12). All bits are cleared upon a read if the
error condition has been removed.
Bit 1 - DRIVE_FAIL2 - Indicates that Fan 2 cannot reach its programmed fan speed even at 100% duty
cycle. This may be due to an aging fan or invalid programming.
Bit 0 - DRIVE_FAIL1 - Indicates that Fan 1 cannot reach its programmed fan speed even at 100% duty
cycle. This may be due to an aging fan or invalid programming.
5.4 Fan Interrupt Enable Register
Table 5.4 Fan Interrupt Enable Register
Fan
FAN2_ FAN1_
29h R/W Interrupt - - - - - - 00h
INT_EN INT_EN
Enable
The Fan Interrupt Enable controls the masking for each Fan channel. When a channel is enabled, it
will cause the ALERT# pin to be asserted when an error condition is detected.
Bit 1 - FAN2_INT_EN - Allows Fan 2 to assert the ALERT# pin if an error is detected.
Bit 0 - FAN1_INT_EN - Allows Fan 1 to assert the ALERT# pin if an error condition is detected.

DATASHEET
Datasheet
‘0’ (default) - An error condition on Fan X will not cause the ALERT# pin to be asserted, however
the status registers will be updated normally.
‘1’ - An error condition (Stall, Spin Up, Drive Fail) on Fan X will cause the ALERT# pin to be
asserted.
5.5 PWM Configuration Registers
Table 5.5 PWM Configuration Registers
PWM Polarity POLARITY POLARITY

2Ah R/W Config - - - - - - 2 1 00h
PWM Output
2Bh R/W - - - - - - PWM2_OT PWM1_OT 00h
Config
The PWM Config registers control the output type and polarity of all PWM outputs.
5.5.1 PWM Polarity Config - 2Ah

Bit 1 - POLARITY2 - Determines the polarity of PWM 2.
Bit 0 - POLARITY1 - Determines the polarity of PWM 1.

‘0’ (default) - the Polarity of the PWM driver is normal. A drive setting of 00h will cause the output
to be set at 0% duty cycle and a drive setting of FFh will cause the output to be set at 100% duty
cycle.
‘1’ - The Polarity of the PWM driver is inverted. A drive setting of 00h will cause the output to be
set at 100% duty cycle and a drive setting of FFh will cause the output to be set at 0% duty cycle.
5.5.2 PWM Output Config - 2Bh

Bit 1 - PWM2_OT - Determines the output type of PWM 2 driver.
Bit 0 - PWM1_OT - Determines the output type of the PWM 1 driver.

‘0’ (default) - The PWM 1 output is configured as an open drain output.
‘1’ - The PWM 1 output is configured as a push-pull output.
5.6 PWM Base Frequency Register
Table 5.6 PWM Base Frequency Register
PWM_ PWM_ PWM_ PWM_

PWM Base
2Dh R/W - - - - BASE BASE BASE BASE 00h
Frequency
2_1 2_0 1_1 1_0
The PWM Base Frequency register determines the base frequency that is used with the PWM Divide
register to determine the final PWM frequency. Each PWM frequency is set by the base frequency and
its respective divide ratio (see Section 5.8).
Controls the base frequency of PWM drivers 1-3 2

DATASHEET
Datasheet
Bits 3-2 - PWM_BASE2[1:0] - Determines the base frequency of the PWM2 driver.
Bits 1-0 - PWM_BASE1[1:0] - Determines the base frequency of the PWM1 driver.
Table 5.7 PWM_BASEx[1:0] Bit Decode
PWM_BASEX[1:0]
1 0 BASE FREQUENCY
0 0 26.00kHz (default)
0 1 19.531kHz
1 0 4,882Hz
1 1 2,441Hz
5.7 Fan Setting Registers
Table 5.8 Fan Driver Setting Registers
30h R/W Fan 1 Setting 128 64 32 16 8 4 2 1 00h
40h R/W Fan 2 Setting 128 64 32 16 8 4 2 1 00h
The Fan Setting register always displays the current setting of the respective fan driver. Reading from
any of the registers will report the current fan speed setting of the appropriate fan driver regardless of
the operating mode. Therefore it is possible that reading from this register will not report data that was
previously written into this register.
While the RPM-based Fan Speed Control Algorithm is active, the register is read only. Writing to the
register will have no effect and the data will not be stored.
The contents of the register represent the weighting of each bit in determining the final output voltage.
The output drive for a PWM output is given by Equation [1].
Drive = ⎛ ---------------------⎞ × 100%

VALUE
[1]
⎝ 255 ⎠
5.8 PWM Divide Registers
Table 5.9 PWM Divide Registers
31h R/W Fan 1 Divide 128 64 32 16 8 4 2 1 01h
41h R/W Fan 2 Divide 128 64 32 16 8 4 2 1 01h
The PWM Divide registers determine the final frequency of the respective PWM Fan Driver. Each driver
base frequency is divided by the value of the respective PWM Divide Register to determine the final

DATASHEET
Datasheet
frequency. The duty cycle settings are not affected by these settings, only the final frequency of the
PWM driver. A value of 00h will be decoded as 01h.
5.9 Fan Configuration 1 Registers
Table 5.10 Fan Configuration 1 Registers
Fan 1 EN_
32h R/W RANGE1[1:0] EDGES1[1:0] UPDATE1[2:0] 2Bh
Configuration 1 ALGO1
Fan 2 EN_
42h R/W RANGE2[1:0] EDGES2[1:0] UPDATE2[2:0] 2Bh
Configuration 1 ALGO2
The Fan Configuration 1 registers control the general operation of the RPM-based Fan Speed Control
Algorithm used for the respective Fan Driver.
Bit 7 - EN_ALGOx - enables the RPM-based Fan Speed Control Algorithm.

‘0’ - (default) the control circuitry is disabled and the fan driver output is determined by the Fan
Driver Setting Register.
‘1’ - the control circuitry is enabled and the Fan Driver output will be automatically updated to
maintain the programmed fan speed as indicated by the TACH Target Register.
Bits 6- 5 - RANGEx[1:0] - Adjusts the range of reported and programmed tachometer reading values.
The RANGE bits determine the weighting of all TACH values (including the Valid TACH Count, TACH
Target, and TACH reading) as shown in Table 5.11.
Table 5.11 Range Decode
RANGEX[1:0]
REPORTED MINIMUM TACH COUNT
1 0 RPM MULTIPLIER
0 0 500 1
0 1 1000 (default) 2
1 0 2000 4
1 1 4000 8
Bits 4-3 - EDGESx[1:0] - determines the minimum number of edges that must be detected on the
TACHx signal to determine a single rotation. A typical fan measured 5 edges (for a 2-pole fan). For
more accurate tachometer measurement, the minimum number of edges measured may be increased.
Increasing the number of edges measured with respect to the number of poles of the fan will cause
the TACH Reading registers to indicate a fan speed that is higher or lower than the actual speed. In
order for the FSC Algorithm to operate correctly, the TACH Target must be updated by the user to
accommodate this shift. The Effective Tach Multiplier shown in Table 5.12 is used as a direct multiplier
term that is applied to the Actual RPM to achieve the Reported RPM. It should only be applied if the
number of edges measured does not match the number of edges expected based on the number of
poles of the fan (which is fixed for any given fan).
Contact SMSC for recommended settings when using fans with more or less than 2 poles.

DATASHEET
Datasheet
Table 5.12 Minimum Edges for Fan Rotation
EDGESX[1:0] EFFECTIVE TACH

MINIMUM TACH MULTIPLIER (BASED ON 2
1 0 EDGES NUMBER OF FAN POLES POLE FANS)
0 0 3 1 pole 0.5
0 1 5 2 poles (default) 1
1 0 7 3 poles 1.5
1 1 9 4 poles 2
Bit 2-0 - UPDATEx[2:0] - determines the base time between fan driver updates. The Update Time,
along with the Fan Step Register, is used to control the ramp rate of the drive response to provide a
cleaner transition of the actual fan operation as the desired fan speed changes. The Update Time is
set as shown in Table 5.13.
Table 5.13 Update Time
UPDATEX[2:0]
2 1 0 UPDATE TIME
0 0 0 100ms
0 0 1 200ms
0 1 0 300ms
0 1 1 400ms (default)
1 0 0 500ms
1 0 1 800ms
1 1 0 1200ms
1 1 1 1600ms
5.10 Fan Configuration 2 Registers
Table 5.14 Fan Configuration 2 Registers
Fan 1 EN_ GLITCH_

33h R/W - DER_OPT1 [1:0] ERR_RNG1[1:0] - 28h
Configuration 2 RRC1 EN1
Fan 2 EN_ GLITCH_

43h R/W - DER_OPT2 [1:0] ERR_RNG2[1:0] - 28h
Configuration 2 RRC2 EN2
The Fan Configuration 2 register control the tachometer measurement and advanced features of the
RPM-based Fan Speed Control Algorithm.

DATASHEET
Datasheet
Bit 6 - EN_RRCx - Enables ramp rate control when the corresponding fan driver is operated in the
Direct Setting Mode.
‘0’ (default) - Ramp rate control is disabled. When the fan driver is operating in Direct Setting mode,
the fan setting will instantly transition to the next programmed setting.
‘1’ - Ramp rate control is enabled. When the fan driver is operating in Direct Setting mode, the fan
drive setting will follow the ramp rate controls as determined by the Fan Step and Update Time
settings. The maximum fan drive setting step is capped at the Fan Step setting and is updated
based on the Update Time as given by Table 5.13.
Bit 5 - GLITCH_ENx - Disables the low pass glitch filter that removes high frequency noise injected
on the TACHx pin.
‘0’ - The glitch filter is disabled.
‘1’ (default) - The glitch filter is enabled.
Bits 4 - 3 - DER_OPTx[1:0] - Control some of the advanced options that affect the derivative portion
of the RPM-based Fan Speed Control Algorithm as shown in Table 5.15.
Table 5.15 Derivative Options
DER_OPTX[1:0]
1 0 OPERATION
0 0 No derivative options used
Basic derivative. The derivative of the error from

the current drive setting and the target is added
0 1 to the iterative Fan Drive Register setting (in
addition to proportional and integral terms)
(default)
Step derivative. The derivative of the error from

the current drive setting and the target is added
1 0
to the iterative Fan Drive Register setting and is
not capped by the Fan Step Register.
Both the basic derivative and the step derivative

1 1 are used effectively causing the derivative term to
have double the effect of the derivative term.
Bit 2 - 1 - ERR_RNGx[1:0] - Control some of the advanced options that affect the error window. When
the measured fan speed is within the programmed error window around the target speed, then the fan
drive setting is not updated. The algorithm will continue to monitor the fan speed and calculate
necessary drive setting changes based on the error; however, these changes are ignored.
Table 5.16 Error Range Options
ERR_RNGX[1:0]
1 0 OPERATION
0 0 0 RPM (default)
0 1 50 RPM
1 0 100 RPM
1 1 200 RPM

DATASHEET
Datasheet
5.11 Gain Registers
Table 5.17 Gain Registers
Gain 1
35h R/W - - GAIND1[1:0] GAINI1[1:0] GAINP1[1:0] 2Ah
Register
Gain 2
45h R/W - - GAIND2[1:0] GAINI2[1:0] GAINP2[1:0] 2Ah
Register
The Gain registers store the gain terms used by the proportional and integral portions of each of the
RPM-based Fan Speed Control Algorithms. These gain terms are used as the KD, KI, and KP gain
terms in a classic PID control solution.
Bits 5 - 4 - GAINDX[1:0] - Controls the derivative gain term used by the FSC algorithm as shown in
Table 5.18.
Bits 3-2 - GAINIX[1:0] - Controls the integral gain term used by the FSC algorithm as shown in
Table 5.18.
Bits 1-0 - GAINP[1:0] - Controls the proportional gain term used by the FSC algorithm as shown in
Table 5.18.
Table 5.18 Gain Decode
GAIND OR GAINP OR GAINI [1:0]
1 0 RESPECTIVE GAIN FACTOR
0 0 1x
0 1 2x
1 0 4x (default)
1 1 8x
5.12 Fan Spin Up Configuration Registers
Table 5.19 Fan Spin Up Configuration Registers
Fan 1 Spin Up DRIVE_FAIL_ SPINUP_TIME

36h R/W NOKICK1 SPIN_LVL1[2:0] 19h
Configuration CNT1 [1:0] 1 [1:0]
Fan 2 Spin up DRIVE_FAIL_ SPINUP_TIME

46h R/W NOKICK2 SPIN_LVL2[2:0] 19h
Configuration CNT2 [1:0] 2 [1:0]
The Fan Spin Up Configuration registers control the settings of Spin Up Routine. The Fan Spin Up
Configuration registers are software locked.
Bit 7 - 6 - DRIVE_FAIL_CNTx[1:0] - Determines how many update cycles are used for the Drive Fail
detection function as shown in Table 5.20. This circuitry determines whether the fan can be driven to
the desired tach target.

DATASHEET
Datasheet
Table 5.20 DRIVE_FAIL_CNT[1:0] Bit Decode
DRIVE_FAIL_CNTX[1:0]
1 0 NUMBER OF UPDATE PERIODS
0 0 Disabled - the Drive Fail detection circuitry is disabled (default)
16 - the Drive Fail detection circuitry will count for 16 update

0 1 periods

1 0 periods

1 1 periods
Bit 5 - NOKICKx - Determines if the Spin Up Routine will drive the fan to 100% duty cycle for 1/4 of
the programmed spin up time before driving it at the programmed level.
‘0’ (default) - The Spin Up Routine will drive the fan driver to 100% for 1/4 of the programmed spin
up time before reverting to the programmed spin level.
‘1’ - The Spin Up Routine will not drive the fan driver to 100%. It will set the drive at the
programmed spin level for the entire duration of the programmed spin up time.
Bits 4 - 2 - SPIN_LVLx[2:0] - Determines the final drive level that is used by the Spin Up Routine as
shown in Table 5.21.
Table 5.21 Spin Level
SPIN_LVLX[2:0]
2 1 0 SPIN UP DRIVE LEVEL
0 0 0 30%
0 0 1 35%
0 1 0 40%
0 1 1 45%
1 0 0 50%
1 0 1 55%
1 1 0 60% (default)
1 1 1 65%
Bit 1 -0 - SPINUP_TIMEx[1:0] - determines the maximum Spin Time that the Spin Up Routine will run
for (see Section 4.6). If a valid tachometer measurement is not detected before the Spin Time has
elapsed, then an interrupt will be generated. When the RPM-based Fan Speed Control Algorithm is
active, the fan driver will attempt to re-start the fan immediately after the end of the last spin up attempt.
The Spin Time is set as shown in Table 5.22.

DATASHEET
Datasheet
Table 5.22 Spin Time
SPINUP_TIMEX[1:0]
1 0 TOTAL SPIN UP TIME
0 0 250 ms
0 1 500 ms (default)
1 0 1 sec
1 1 2 sec
5.13 Fan Max Step Registers
Table 5.23 Fan Max Step Registers
Fan 1 Max
37h R/W - - 32 16 8 4 2 1 10h
Step
Fan 2 Max
47h R/W - - 32 16 8 4 2 1 10h
Step
The Fan Max Step registers, along with the Update Time, control the ramp rate of the fan driver
response calculated by the RPM-based Fan Speed Control Algorithm. The value of the register
represents the maximum step size each fan driver will take between update times (see Section 5.9).
When the FSC algorithm is enabled, Ramp Rate control is automatically used. When the FSC is not
active, then Ramp Rate control can be enabled by asserting the EN_RRC bit (see Section 5.10).
APPLICATION NOTE: The UPDATE bits and Fan Step Register settings operate independently of the RPM-based
Fan Speed Control Algorithm and will always limit the fan drive setting. That is, if the
programmed fan drive setting (either as determined by the RPM-based Fan Speed Control
Algorithm or by manual settings) exceeds the current fan drive setting by greater than the
Fan Step Register setting, the EMC2302 will limit the fan drive change to the value of the
Fan Step Register. It will use the Update Time to determine how often to update the drive
settings.
APPLICATION NOTE: If the Fan Speed Control Algorithm is used, the default settings in the Fan Configuration 2
Register will cause the maximum fan step settings to be ignored.
The Fan Max Step registers are software locked.

DATASHEET
Datasheet
5.14 Fan Minimum Drive Registers
Table 5.24 Minimum Fan Drive Registers
Fan 1
66h
38h R/W Minimum 128 64 32 16 8 4 2 1
(40%)
Drive
Fan 2
66h
48h R/W Minimum 128 64 32 16 8 4 2 1
(40%)
Drive
The Fan Minimum Drive registers store the minimum drive setting for each RPM-based Fan Speed
Control Algorithm. The RPM-based Fan Speed Control Algorithm will not drive the fan at a level lower
than the minimum drive unless the target Fan Speed is set at FFh (see Section 5.17).
During normal operation, if the fan stops for any reason (including low drive), the RPM-based Fan
Speed Control Algorithm will attempt to restart the fan. Setting the Fan Minimum Drive Register to a
setting that will maintain fan operation is a useful way to avoid potential fan oscillations as the control
circuitry attempts to drive it at a level that cannot support fan operation.
The Fan Minimum Drive Registers are software locked.
5.15 Valid TACH Count Registers
Table 5.25 Valid TACH Count Registers
Valid TACH
39h R/W 4096 2048 1024 512 256 128 64 32 F5h
Count 1
Valid TACH
49h R/W 4096 2048 1024 512 256 128 64 32 F5h
Count 2
The Valid TACH Count registers store the maximum TACH Reading Register value to indicate that
each fan is spinning properly. The value is referenced at the end of the Spin Up Routine to determine
if the fan has started operating and decide if the device needs to retry. See Equation [2] in Section 5.18
for translating the count to an RPM.
If the TACH Reading Register value exceeds the Valid TACH Count Register (indicating that the Fan
RPM is below the threshold set by this count), then a stalled fan is detected. In this condition, the
algorithm will automatically begin its Spin Up Routine.
If a TACH Target setting is set above the Valid TACH Count setting, then that setting will be ignored
and the algorithm will use the current fan drive setting.
The Valid TACH Count registers are software locked.

DATASHEET
Datasheet
5.16 Fan Drive Fail Band Registers
Table 5.26 Fan Drive Fail Band Registers
Fan 1 Drive
3Ah R/W Fail Band 16 8 4 2 1 - - - 00h
Low Byte
Fan 1 Drive
3Bh R/W Fail Band 4096 2048 1024 512 256 128 64 32 00h
High Byte
Fan 2 Drive
4Ah R/W Fail Band 16 8 4 2 1 - - - 00h
Low Byte
Fan 2 Drive
4Bh R/W Fall Band 4096 2048 1024 512 256 128 64 32 00h
High Byte
The Fan Drive Fail Band Registers store the number of tach counts used by the Fan Drive Fail
detection circuitry. This circuitry is activated when the fan drive setting high byte is at FFh. When it is
enabled, the actual measured fan speed is compared against the target fan speed. These registers
are only used when the FSC is active.
This circuitry is used to indicate that the target fan speed at full drive is higher than the fan is actually
capable of reaching. If the measured fan speed does not exceed the target fan speed minus the Fan
Drive Fail Band Register settings for a period of time longer than set by the DRIVE_FAIL_CNTx[1:0]
bits, then the DRIVE_FAIL status bit will be set and an interrupt generated.
5.17 TACH Target Registers
Table 5.27 TACH Target Registers
TACH Target
3Ch R/W 16 8 4 2 1 - - - F8h
1 Low Byte
TACH Target
3Dh R/W 4096 2048 1024 512 256 128 64 32 FFh
1 High Byte
TACH Target
4Ch R 16 8 4 2 1 - - - F8h
2 Low Byte
TACH Target
4Dh R/W 4096 2048 1024 512 256 128 64 32 FFh
2 High Byte
The TACH Target Registers hold the target tachometer value that is maintained by the RPM-based
Fan Speed Control Algorithm.
The value in the TACH Target Registers will always reflect the current TACH Target value.
If one of the algorithms is enabled, setting the TACH Target Register to FFh will disable the fan driver
(set the fan drive setting to 0%). Setting the TACH Target to any other value (from a setting of FFh)
will cause the algorithm to invoke the Spin Up Routine after which it will function normally.

DATASHEET
Datasheet
The Tach Target is not applied until the high byte is written. Once the high byte is written, the current
value of both high and low bytes will be used as the next Tach target.
5.18 TACH Reading Registers
Table 5.28 TACH Reading Registers
3Eh R Fan 1 TACH 4096 2048 1024 512 256 128 64 32 FFh
Fan 1 TACH
3Fh R 16 8 4 2 1 - - - F8h
Low Byte
4Eh R Fan 2 TACH 4096 2048 1024 512 256 128 64 32 FFh
Fan 2 TACH
4Fh R 16 8 4 2 1 - - - F8h
Low Byte
The TACH Reading Registers’ contents describe the current tachometer reading for each of the fans.
By default, the data represents the fan speed as the number of 32kHz clock periods that occur for a
single revolution of the fan.
Equation [2] shows the detailed conversion from TACH measurement (COUNT) to RPM while Equation
[3] shows the simplified translation of TACH Reading Register count to RPM assuming a 2-pole fan,
measuring 5 edges, with a frequency of 32.768kHz. These equations are solved and tabulated for ease
of use in AN17.4 RPM to TACH Counts Conversion.
Whenever the high byte register is read, the corresponding low byte data will be loaded to internal
shadow registers so that when the low byte is read, the data will always coincide with the previously
read high byte.
where:
poles = number of poles of the fan

(typically 2)
1 (n – 1)
RPM = -------------------- × ---------------------------------- × f TACH × 60 fTACH = the tachometer [2]
( poles ) 1
COUNT × ----- measurement frequency (typically
m 32.768kHz)
n = number of edges measured

(typically 5 for a 2 pole fan)
m = the multiplier defined by the

RANGE bits
3,932,160 × m
RPM = -------------------------------------- [3]
COUNT COUNT = TACH Reading Register
value (in decimal)

DATASHEET
Datasheet
5.19 Software Lock Register
Table 5.29 Software Lock Register
Software
EFh R/W - - - - - - - LOCK 00h
Lock
The Software Lock Register controls the software locking of critical registers. This register is software
locked.
Bit 0 - LOCK - this bit acts on all registers that are designated SWL. When this bit is set, the locked
registers become read only and cannot be updated.
‘0’ (default) - all SWL registers can be updated normally.
‘1’ - all SWL registers cannot be updated and a hard-reset is required to unlock them.
5.20 Product ID Register
Table 5.30 Product ID Register
FDh R Product ID 0 0 1 1 0 1 1 0 36h
The Product ID Register contains a unique 8-bit word that identifies the product.
5.21 Manufacturer ID Register
Table 5.31 Manufacturer ID Register
FEh R Manufacturer ID 0 1 0 1 1 1 0 1 5Dh
The Manufacturer ID Register contains an 8-bit word that identifies SMSC.
5.22 Revision Register
Table 5.32 Revision Register
FFh R Revision 1 0 0 0 0 0 0 0 80h
The Revision Register contains an 8-bit word that identifies the die revision.

DATASHEET
Datasheet

DATASHEET
Datasheet
Chapter 6 Typical Operating Curves
The following Typical Operating Curves are included.

Supply Current vs. Temperature
Supply Current vs. Supply Voltage
Fan TACH Accuracy vs. Temperature
Fan TACH Accuracy vs. Supply Voltage
PWM output frequency vs. Supply Voltage
PWM output frequency vs. Temperature
FSC Operation
Supply Current vs. Ambient Temperature Supply Current vs. Supply Voltage
500 500
450 450
(uA)
Current (uA)
(uA)
Current (uA)
SupplyCurrent
400
SupplyCurrent
400
350
Supply
Supply
350
300 300
250 250
-50 0 50 100 150 2.95 3.05 3.15 3.25 3.35 3.45 3.55 3.65
Ambient Temperature
Temperature (C)(°C) Supply Voltage
Supply Voltage(V)(V)
Tachometer Measurement Accuracy vs. Ambient Temperature Tachometer Measurement Accuracy vs. Supply Voltage
1 1
0.8
(%)(%
0.8
(%
Accuracy(%)
Accuracy
0.6 0.6
MeasurementAccuracy
Accuracy
0.4 0.4
0.2 0.2
Measurement
Tach Measurement
0
Measurement
0
-0.2 -0.2
-0.4 -0.4
-0.6
Tach
Tach
-0.6
Tach
-0.8 -0.8
-1
-1
-50 0 50 100 150 2.95 3.05 3.15 3.25 3.35 3.45 3.55 3.65
AmbientTemperautre (C)
Temperature (°C) Supply Voltage (V)

DATASHEET
Datasheet
PWM Frequency vs. Ambient Temperature PWM Frequency vs. Supply Voltage
V DD = 3.3V, Base Frequncy = 26Khz TA = 25C, Base Frequncy = 26Khz
27000
27000
26800
26800
26600
26600
PWM Frequency (Hz)
26400
PWM Frequency (Hz)

26400
26200 26200
26000 26000
25800 25800
25600 25600
25400 25400
25200 25200
25000 25000
-50 0 50 100 150 2.95 3.05 3.15 3.25 3.35 3.45 3.55 3.65
Ambient Temperature (°C)
T emp er at ur e ( C ) Supply Voltage (V)
FSC Algorithm Spin Up Routine FSC Algorithm Spin Up Routine – NoKick

Spin Time = 1.0s; Spin Level = 55%; Updated Time = 200ms; Spin Time = 1.0s; Spin Level = 50%; UpdateTime = 200ms;
RPM Target from 0 RPM -> 8000 RPM @ time t = 0 RPM Target from 0 RPM -> 8000 RPM @ time t = 0
PWM
PWM
Output
Output
10x
10x Zoom on
Zoom on PWM
PWM Output
Output
t=0 Duty Cycle Measured = 53.8% t=0 Duty Cycle Measured = 50%
FSC Algorithm PWM Ramping

Update Time = 200ms; Max Step = 16 PWM counts
RPM Target from 0 RPM -> 8000 RPM @ time t = 0
PWM
Output
10x
Zoom on
PWM
Output
Spin Up Routine Ends – begins normal

operation Duty Cycle
Measured Update Time ends, PWM duty
cycle changed
Update Time ends, PWM duty cycle changed

DATASHEET
Datasheet
Chapter 7 Package Drawing
7.1 EMC2302 Package Information
REVISIO N HISTORY
REVISION DESCRIPTION DATE RELEASED BY

3 5
A INITIAL RELEASE 3/29/05 S. K.ILIEV
D PIN 1 IDENTIFIER
e AREA (D/2 X E1/2) c 4
3 E1 E
4 2 10X b SEE DETAIL "A"
TOP VIEW END VIEW
A2
C A
SEATING PLANE
A1
ccc C
NOTES:
SIDE VIEW 3-D VIEW 1. ALL DI MENSIONS ARE IN MILLIMETER.
2. TOLERANCE ON THE TRUE POSITION OF EACH LEAD IS ± 0.04 mm AT MAXIMUM MATERIAL
CONDITION.
3. PACKAGE BODY DIMENSIONS "D" AND "E1" DO NOT INCLUDE MOLD/INTERLEAD PROTRUSIONS
OR FLASH. MAXIMUM MOLD PROTRUSIONS OR FLASH IS 0.15 mm (0.006 INCHES) PER END AND
SIDE. DIMENSIONS "D" AND "E1" ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE
PLASTIC BODY, INCLUDING ANY MISMATCH BETWEEN TOP AND BOTTOM PLASTIC BODY. THEY
H
ARE DETERMINED AT DATUM PLANE "H".
4. DIMENSIONS "b" AND "c" APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.08 mm AND
C 0.15 mm FROM THE LEAD TIP.
GAUGE PLANE
5. DETAILS OF THE PIN 1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE
0.25 INDICATED.
SEATING PLANE
0° - 8° L UNLESS OTHERWISE SPECIFIED THIR D ANG L E PRO J ECTION
DIM ENSI ONS ARE IN MILLIMETERS

AND T OLERANCES ARE: 80 ARKAY DRIV E
HAUPPAUGE, NY 11788
(0.95) DECIM AL
X.X ±0.1
ANGULAR
±1 °
USA
X.XX ±0.05
X.XXX ±0.025
TITLE
N AM E DAT E
DETAIL "A"
DI M AND T OL PER ASME Y14.5M - 1994
PACKAGE OUTLINE
M A TERIAL DRAWN
- S.K.IL IEV 3/29 /0 5 10 PIN TSSO P, 3x3 MM BODY, 0.50 MM PITCH
F N
I ISH CH ECKED DWG NUM BER REV
- S.K.IL IEV 3/29 /0 5 MO-10-TSSOP-3x3 A
APPR OVED SC ALE STD C OM PL IANC E S HEET
PRINT WIT H "SCALE TO FIT"
DO NOT SCALE DRAWING S.K.IL IEV 3/29 /0 5 1:1 JEDEC : MO-187 1 OF 1
Figure 7.1 EMC2302 Package Drawing - 10-Pin MSOP

DATASHEET
Datasheet
7.2 Package Markings
TOP
LINE: 1-T – Device Number 2 3 0 2 2x 1.5pt
LINE: 2-T Version, Revision, Country Code (VRCC) V R C C
e3
PIN 1 PB-FREE/GREEN SYMBOL

(Matte Sn)
ALL TOP LINES CENTER
HORIZONTAL ALIGNMENT
BOTTOM
PIN 1
LINE: 1-B – Date Code (YYWW)

Y Y WW 3x 1.5pt
LINE: 2-B – First 3 Digits of Lot Number 1 2 3
LINE: 3-B – Last 4 Digits of Lot Number 4 5 6 a
Figure 7.2 EMC2302 Package Markings

DATASHEET

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EMC2302

Dual RPM-Based PWM

PRODUCT FEATURES Datasheet

General Description Features

SMSC EMC2302 DATASHEET Revision 1.1 (10-12-09)

ORDERING NUMBER PACKAGE FEATURES

EMC2302-1-AIZL-TR 10-pin MSOP (Lead-free Two RPM-based fan speed control

EMC2302-2-AIZL-TR 10-pin MSOP (Lead-free Two RPM-based fan speed control

80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123

Copyright © 2009 SMSC or its subsidiaries. All rights reserved.

Revision 1.1 (10-12-09) 2 SMSC EMC2302

Chapter 1 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Chapter 2 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Chapter 4 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Chapter 5 Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

SMSC EMC2302 3 Revision 1.1 (10-12-09)

5.5 PWM Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Chapter 6 Typical Operating Curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Chapter 7 Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Revision 1.1 (10-12-09) 4 SMSC EMC2302

SMSC EMC2302 5 Revision 1.1 (10-12-09)

Revision 1.1 (10-12-09) 6 SMSC EMC2302

Chapter 1 Pin Description

Figure 1.1 EMC2302 Pin Diagram (10-Pin MSOP)

Table 1.1 Pin Description for EMC2302

PIN NUMBER PIN NAME PIN FUNCTION PIN TYPE

SMBus data input/output - requires

SMBus clock input - requires external

3 VDD Power Supply Power

4 GND Ground Power

Push-Pull PWM output driver for Fan 1 DO

Open drain tachometer input for Fan 1-

Push-Pull PWM output driver for Fan 2 DO

Open drain tachometer input for Fan 2 -

SMSC EMC2302 7 Revision 1.1 (10-12-09)

Table 1.1 Pin Description for EMC2302 (continued)

PIN NUMBER PIN NAME PIN FUNCTION PIN TYPE

Clock input for tachometer measurement DI (5V)

9 CLK Push Pull Clock output to other fan

Active low interrupt - requires external

Table 1.2 Pin Types

PIN TYPE DESCRIPTION

Power This pin is used to supply power or ground to the device.

Digital Input - this pin is used as a digital input. This pin is

Push / Pull Digital Output - this pin is used as a digital

Digital Input / Open Drain Output this pin is used as a

Open Drain Digital Output - this pin is used as a digital

Revision 1.1 (10-12-09) 8 SMSC EMC2302

Chapter 2 Electrical Specifications

Table 2.1 Absolute Maximum Ratings

Voltage on 5V tolerant pins (V5VT_pin) -0.3 to 5.5 V

Voltage on 5V tolerant pins (|V5VT_pin - VDD|) (see Note 2.1) 0 to 3.6 V

Voltage on VDD pin -0.3 to 4 V

Voltage on any other pin to GND -0.3 to VDD + 0.3 V

Package Thermal Restance - Junction to Ambient (θJA) 132 °C/W

Operating Ambient Temperature Range -40 to 125 °C

Storage Temperature Range -55 to 150 °C

ESD Rating, All Pins, HBM 2000 V

2.1 Electrical Specifications