Digital System Design

Assignment – 1
Submitted By – Muhammad Farhan Ejaz
CMS ID – 371645
Degree – 43
Syndicate – B

NUST College of CEME

Department of Electrical Engineering
Q1: Show block diagrams and compare architectures of the following

–Microcontroller
–Microprocessor
–DSP
–SoC (System on chip)

1. Microcontroller
Definition

A Microcontroller is a compact integrated circuit designed to govern a specific operation in an

embedded system. It typically includes a processor core, memory, and programmable
input/output peripherals.

Block Diagram Components

1. CPU (Central Processing Unit)

a. Executes instructions.
b. Includes ALU (Arithmetic Logic Unit) and control unit.
 2. Memory
a. Flash Memory: Stores the program code.
b. RAM: Temporary data storage.
3. I/O Ports
a. Interfaces for interacting with external devices (e.g., sensors, LEDs).
4. Timers/Counters
a. Manage timing-related tasks.
5. Peripheral Interfaces
a. UART, SPI, I2C: Communication protocols for data exchange.
6. Analog Interfaces
a. ADC (Analog-to-Digital Converter)
b. DAC (Digital-to-Analog Converter)

Typical Use Cases

• Home appliances
• Automotive systems
• Industrial control systems

2. Microprocessor
Definition

A Microprocessor is a general-purpose system integrated onto a single chip. It primarily

consists of the CPU and is designed to perform a wide range of tasks, typically requiring external
components for memory and I/O.
Block Diagram Components

1. CPU (Central Processing Unit)

a. Core processing unit with ALU and control unit.
2. Cache Memory
a. L1, L2, L3 Caches: High-speed memory to speed up processing.
3. Bus Interface Units
a. Address Bus
b. Data Bus
c. Control Bus
4. Memory Management Unit (MMU)
a. Handles virtual memory and memory protection.
5. I/O Interfaces
a. Connects to various peripherals and external devices.
6. Clock Generator
a. Provides timing signals for synchronization.

Typical Use Cases

• Personal computers
 • Servers
• High-performance computing systems

3. Digital Signal Processor (DSP)

Definition

A Digital Signal Processor (DSP) is specialized for processing real-time signal data. It is
optimized for tasks requiring high-speed numerical operations, such as audio, video, and
communications processing.

Block Diagram Components

1. CPU Core
a. Optimized for repetitive mathematical operations.
2. MAC Units (Multiply-Accumulate)
a. Facilitates rapid arithmetic computations.
3. Specialized Memory
a. Program Memory: Stores DSP algorithms.
 b. Data Memory: Dedicated to fast data access.
4. Peripheral Interfaces
a. Designed for high-speed data input/output (e.g., DMA controllers).
5. Interrupt Controllers
a. Manages real-time processing requirements.
6. Timers and Counters
a. Synchronize signal processing tasks.

Typical Use Cases

• Audio signal processing

• Image and video processing
• Telecommunications

4. System on Chip (SoC)

Definition

A System on Chip (SoC) integrates all components of a computer or other electronic system
into a single chip. It combines the CPU, memory, peripherals, and often other functionalities like
GPU (Graphics Processing Unit) and modem.
Block Diagram Components

1. CPU
a. Central processing unit, often multi-core.
2. GPU
a. Handles graphics and parallel processing tasks.
3. Memory Subsystem
a. RAM
b. ROM/Flash Memory
4. Peripheral Interfaces
a. USB, HDMI, Ethernet: Various connectivity options.
5. Integrated Controllers
a. Display Controllers
b. Audio Controllers
6. Power Management Unit (PMU)
a. Manages power distribution across the chip.
7. Connectivity Modules
a. Wi-Fi, Bluetooth, Cellular: Wireless communication components.
8. Security Module
Typical Use Cases

• Smartphones and tablets

• Smart TVs
• IoT devices

Comparative Analysis
Feature Microcontroller Microprocessor DSP SoC
Primary Use Embedded General-purpose Real-time signal Integrated
systems computing processing complete
systems
CPU Type Simple, low Complex, high- Specialized for Multi-
power performance arithmetic functional,
operations often multi-
core
Memory On-chip Flash and External memory Dedicated Integrated
RAM required program and data memory
memory subsystems
Peripherals Built-in I/O, Requires external High-speed I/O Extensive
ADC/DAC peripherals for signal data integrated
peripherals
Power Low Higher Moderate to high Varies,
Consumption typically
optimized for
efficiency
Performance Moderate for High for High for High, with
control tasks computational mathematical and specialized
tasks signal tasks processing
units
Cost Low Higher Moderate Varies,
generally
higher due to
integration
Examples AVR, PIC, ARM Intel Core, AMD Texas Instruments Qualcomm
Cortex-M Ryzen TMS320, Analog Snapdragon,
Devices SHARC Apple A-series

Q2: (PLO-1)
•Write Verilog code for 8-to-3-line simple encoder and priority encoder
•Show both circuits synthesized by Intel Quartus/Xilinx ISE
•Compare and discuss the results

Simple Encoder:

Code:

module simple_encoder_8to3 (
input [7:0] in, // 8-bit input signal
output reg [2:0] out // 3-bit encoded output
);

always @(*) begin

case (in)
8'b00000001: out = 3'b000;
8'b00000010: out = 3'b001;
8'b00000100: out = 3'b010;
8'b00001000: out = 3'b011;
8'b00010000: out = 3'b100;
8'b00100000: out = 3'b101;
8'b01000000: out = 3'b110;
8'b10000000: out = 3'b111;
default: out = 3'b000; // No valid input or multiple inputs
endcase
end

endmodule
module simple_encoder_tb;

reg [7:0] in;

wire [2:0] out;

simple_encoder_8to3 uut (
.in(in),
.out(out)
);

initial begin
// Test case 1: Input 00000001 -> Output 000
in = 8'b00000001;
#10;
$display("Input: %b, Output: %b", in, out);

// Test case 2: Input 00000010 -> Output 001

in = 8'b00000010;
#10;
$display("Input: %b, Output: %b", in, out);

// Test case 3: Input 00000100 -> Output 010

in = 8'b00000100;
#10;
$display("Input: %b, Output: %b", in, out);

// Test case 4: Input 00100000 -> Output 101

in = 8'b00100000;
#10;
$display("Input: %b, Output: %b", in, out);

// Test case 5: Input 10000000 -> Output 111

in = 8'b10000000;
#10;
$display("Input: %b, Output: %b", in, out);

// Test case 6: Multiple inputs active (00100100)

in = 8'b00100100; // Will only recognize the highest priority, which is 010
#10;
$display("Input: %b, Output: %b", in, out);

$finish;
end

Endmodule

Circuit -
Priority Encoder:
Code:
module priority_encoder_8to3 (
input [7:0] in,
output reg [2:0] out
);

always @(*) begin

if (in[7])
out = 3'b111;
else if (in[6])
out = 3'b110;
else if (in[5])
out = 3'b101;
else if (in[4])
out = 3'b100;
else if (in[3])
out = 3'b011;
else if (in[2])
out = 3'b010;
else if (in[1])
out = 3'b001;
else if (in[0])
out = 3'b000;
else
out = 3'b000; // No valid input
end

endmodule

module priority_encoder_tb;
reg [7:0] in;
wire [2:0] out;

priority_encoder_8to3 uut (
.in(in),
.out(out)
);

initial begin
// Test case 1: Input 00000001 -> Output 000
in = 8'b00000001;
#10;
$display("Input: %b, Output: %b", in, out);

// Test case 2: Input 00000010 -> Output 001

in = 8'b00000010;
#10;
$display("Input: %b, Output: %b", in, out);

// Test case 3: Input 00100000 -> Output 101

in = 8'b00100000;
#10;
$display("Input: %b, Output: %b", in, out);

// Test case 4: Multiple inputs active (00100100) -> Should choose the highest priority
in = 8'b00100100; // Will choose the highest active bit (bit 5) -> Output 101
#10;
$display("Input: %b, Output: %b", in, out);

// Test case 5: Highest priority bit (bit 7) active -> Output 111
in = 8'b10000000;
#10;
$display("Input: %b, Output: %b", in, out);

$finish;
end

Endmodule

Circuit -
 • Simple Encoder:
• It converts a one-hot 8-bit input into a 3-bit output.
• It assumes that only one input bit is high at a time.
• If multiple bits are high, it defaults to 3'b000 (invalid case).
• Priority Encoder:
• This encoder gives priority to the highest active bit.
• If multiple bits are high, the highest bit (index 7 down to 0) will determine the 3-bit
output.

Comparison of Results

A) RTL Schematic and Circuit Structure

• Simple Encoder:
o The RTL schematic of a simple encoder will show basic combinational logic with
no conditional statements. The synthesis will result in simple logic gates to map
each input to its corresponding 3-bit output.
• Priority Encoder:
o The RTL schematic of a priority encoder will be more complex, as it needs logic
to decide the highest-priority active bit. This will likely result in conditional
logic (MUX-based or priority logic gates) to select the correct output based on the
priority of the inputs.

B) Resource Usage (LUTs, Flip-Flops)

• Simple Encoder:
 o The simple encoder uses minimal resources, typically just 8-to-3 combinational
logic (AND/OR gates).
o It will likely consume fewer LUTs (Look-Up Tables) and other logic resources,
such as flip-flops, compared to the priority encoder.
• Priority Encoder:
o The priority encoder will consume more resources because it needs priority
determination logic.
o More LUTs will be needed to handle the priority conditions (comparing bits to
find the highest active one).
o However, for an 8-to-3 priority encoder, this difference will not be significant in
small FPGAs but is still important to note.

C) Timing and Critical Path

• Simple Encoder:
o The critical path delay (longest delay from input to output) is minimal, as there is
no complex logic involved. The delay will mostly be due to basic gate
propagation delays.
• Priority Encoder:
o Since the priority encoder requires more decision-making logic, its critical path
will be slightly longer. The synthesis tool will need to generate multiplexing
logic (MUX) or use conditional gates to choose the correct output, leading to a
slight increase in the propagation delay.

D) Power Consumption

• Simple Encoder:
o The simple encoder consumes less power due to its minimal logic complexity.
• Priority Encoder:
o More logic in the priority encoder implies slightly higher power consumption.
The increase will not be dramatic for an 8-bit encoder, but in larger systems, the
power difference becomes more relevant.

4. Comparison Summary

Factor Simple Encoder Priority Encoder

RTL Straightforward, minimal More complex logic to handle priority
Schematic combinational logic. selection.
Resource Fewer LUTs and basic Higher LUT usage for priority checking
Usage combinational logic gates. logic.
Critical Path Shorter, minimal delay due to Slightly longer due to extra priority
Delay simple gate propagation. logic (MUX).
Power Low due to minimal resource Slightly higher power due to more
Consumption usage. complex logic.
Design Easy to implement and More complex, but necessary for
Complexity understand. applications with priorities.

5. Discussion

• When to Use a Simple Encoder:

o A simple encoder is ideal in cases where only one input is active at any given
time (such as a one-hot signal). It is efficient and requires minimal resources,
making it perfect for low-power, resource-constrained designs.
o Example applications include multiplexer selection, address decoding, and
interrupt request identification when only one event occurs at a time.
• When to Use a Priority Encoder:
o The priority encoder is useful when multiple inputs could be active
simultaneously, and you need to select the most important (highest priority)
event. This is essential in systems like interrupt handling in microprocessors,
where multiple events might happen, but only the most urgent one should be
addressed.
o It requires more resources and has a longer delay, but for certain real-time
systems or when dealing with multiple active inputs, this extra complexity is
unavoidable.