ANALOG & DIGITAL CIRCUITS LABORATORY 2024-25

DAYANANDA SAGAR COLLEGE OF ENGINEERING

(An Autonomous Institute Affiliated to VTU, Belagavi)
Accredited by NBA & National Assessment Accreditation Council (NAAC) with ‘A’ grade
Shavige Malleshwara Hills, Kumaraswamy Layout, Bengaluru-560078

DEPARTMENT OF ELECTRICAL & ELECTRONICS ENGINEERING

ANALOG AND DIGITAL CIRCUITS LABORATORY MANUAL

III SEMESTER B.E. (22EE33)

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VISION OF INSTITUTE

To impart quality technical education with a focus on Research and Innovation emphasising on Development of
Sustainable and Inclusive Technology for the benefit of society.

MISSION OF INSTITUTE

● To provide an environment that enhances creativity and Innovation in pursuit of Excellence.

● To nurture teamwork in order to transform individuals as responsible leaders and entrepreneurs.
● To train the students to the changing technical scenario and make them to understand the importance of
Sustainable and Inclusive technologies.
VISION OF THE DEPARTMENT
To meet the challenging needs of society by innovation, problem solving and to develop an exciting and
supportive learning environment that transforms our students and inspires them to make a real difference in
their career and society.

MISSION OF THE DEPARTMENT

● To provide enduring learning environment that facilitates the students to pursue their higher education.
● To train students with diverse skills to work professionally in several fields through innovative teaching and
learning process.
● To provide value based and behavioral training programs that helps students in developing their overall
professional competence and social awareness.

Program Educational Objectives of the UG – Electrical and Electronics Engineering

● PEO1 - Graduates will have the ability to apply the knowledge of Electrical & Electronics Engineering to
excel in their career path.
● PEO2 - Graduates will be confident to work in flexible and diverse professional fields.

● PEO3 - Graduates will have commitment and awareness to thrive in their ethical and social responsibilities.

● PEO4 - Graduates will have the ability to pursue higher education, research and will be engaged in
life-long learning processes.

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PROGRAM OUTCOMES(POS)

Engineering Graduates will be able to:

1. Engineering Knowledge:
2. Problem analysis
3. Design/ development of solutions
4. Conduct investigations of complex problems
5. Modern Tool usage
6. The engineer and society
7. Environment and sustainability
8. Ethics
9. Individual and team work
10. Communication
11. Project management and finance
12. Life-long learning

PROGRAM SPECIFIC OUTCOMES (PSO)

PSO-1: The students will be able to apply the knowledge of mathematics, and applied science principles to
solve diverse problems in the field of power systems and control of Electric Drives catering to Industrial,
Research, Service and allied areas.

PSO-2: The students would be competent in identifying, analysing and exhibiting the skills in providing
solutions to problems related to control electronic systems using various modern tools.

PSO-3: The students will be able to demonstrate proficiency in design and development of different
electrical and electronics systems as per specified standards.

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DO’s

​ Adhere and follow timings, proper dress code with appropriate foot wear.

​ Bags, and other personal items must be stored in designated place.

​ Come prepare with the viva, procedure, and other details of the experiment.
​ Do check for the correct ranges/rating and carry one meter/instrument at a time
​ Inspect all equipment/meters for damage prior to use
​ Conduct the experiments accurately as directed by the teacher.
​ Immediately report any sparks/ accidents/ injuries/ any other untoward incident to the
faculty /instructor.
​ Handle the apparatus/meters/computers gently and with care
​ In case of an emergency or accident, follow the safety procedure.
​ Switch OFF the power supply after completion of experiment.

DONT’s
​ The use of mobile/ any other personal electronic gadgets is prohibited in the laboratory.

​ Do not make noise in the Laboratory & do not sit on experiment table.
​ Do not make loose connections and avoid overlapping of wires
​ Don’t switch on power supply without prior permission from the concerned staff.
​ Never point/touch the CRO/Monitor screen with the tip of the open pen/pencil/any
other sharp object.
​ Never leave the experiments while in progress.
​ Do not insert/use pen drive/any other storage devices into the CPU.
​ Do not leave the Laboratory without the signature of the concerned staff in observation book

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Component Circuit Symbol Function of Component

Wire To pass current from one part of a circuit to another.

Wires connected at junctions should be staggered slightly

Wires joined
to form two T-junctions, as shown.

Wires crossing even though they are not

Wires not joined
connected.

The Fuse reacts as safety element to protect circuit

Fuse
against large current and sudden urges of current.
Switch SPST = Single Pole, Single Throw. An on-off switch allows
(SPST) current to flow only when it is in the closed (on) position.

Cell Cell Supplies electrical energy. The larger terminal is

positive (+). A single cell is often called a battery, but
strictly a battery is two or more cells joined together.

Supplies electrical energy. A battery is more than one cell.

Battery
The larger terminal is positive (+).

AC Supply This represents AC supply in the circuit.

This represents the DC power supply. It applies DC supply

DC Supply
to the circuit.

It is equivalent to theoretical 0 V and is used as zero

Ground potential reference. It is the potential of perfectly
conducting earth.
Fixed Resistor OR It is a device that opposes the flow of current in a circuit.
These two symbols are used to represent fixed resistor.
It is a two terminal variable resistor. They are generally
OR used to control the current in the circuit. Generally used in
Rheostat
tuning circuits and power control applications like heaters,
ovens etc
Capacitor stores the charge in the form of electrical
Capacitor
energy. It can be used in both AC and DC circuits.

Almost all electrolytic capacitors are polarized and hence

Electrolytic
used in DC circuits. It can also be used as a filter, to block
Capacitor
DC signals but pass AC signals.

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Component Circuit Symbol Function of Component

A coil of wire which creates a magnetic field when current

Iron Core Inductor
passes through it.
Two coils of wire linked by an iron core. Transformers are
used to step up (increase) and step down (decrease) AC
Transformer
voltages. Energy is transferred between the coils by the
magnetic field in the core. There is no electrical
connection between the coils.
A device which only allows current to flow in one
Diode
direction.
Transistor
A transistor amplifies current. It can be used with other
(NPN)
components to make an amplifier or switching circuit.

A voltmeter is used to measure voltage. The proper name

Voltmeter
for voltage is 'potential difference', but most people
prefer to say voltage!

Ammeter An ammeter is used to measure current.

N-channel JFET is made by n-type silicon bars which form

JFET
two PN junctions at the side. Majority charge carriers here
N- Channel
are electrons.

MOSFET
The enhancement MOSFET structure has no channel
P-Channel
formed during its construction. Voltage is applied to the
gate, so as to develop a channel.

An operational amplifier (op-amp) is a DC-coupled high-

OPAMP gain electronic voltage amplifier with a differential input
and, usually, a single-ended output.

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Bread Board Connection Diagram

Internal Wire Connection

External Pin Connection

Standard Resistor Values and Color Coding

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Calculation of Ceramic Capacitance Value from the reading on the Capacitor

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CIE MARKS SCHEME OF EVALUATION

LAB Class Internal Examination (CIE) Marks: 50

1 Lab wise Assessment Marks

a. Record : Write-up / Design
for every experiment
Aim & apparatus -1 M 10M
Circuit diagram and procedure-3 M
Theory -2 M 30M
Design/Calculations and tables - 3 M
Result -1 M
b. Observation /conduction/result 10 M
c. Neatness
02 M
d. In time Submission
03 M
e. Viva-voce
05M
2 Lab Test Assessment
a. Write up 04M
b. Conduction 08M 20M
c. Calculation/ Graphs/Results 04M
d. Viva - 04M
Total: 50M

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GENERAL PROCEDURE TO BE FOLLOWED BY THE STUDENTS

Minimum of 85% to be maintained. [Attendance at your regularly scheduled lab

period is required. An unexpected absence will result in loss of credit for your lab.
Attendance
If for valid reason a student misses a lab, or makes a reasonable request in advance].

Punctuality Late entry to the lab NOT permitted.

Dress Code Should wear formal dress and shoe, No slippers.
No eating or drinking is allowed. Unnecessary roaming around the lab to be avoided.
Conduct Noise level is to be kept to the absolute minimum.

Safety Students are to observe safety regulations at all times.

Equipment All mains and electrical equipment are to be switched off when not in use or when the
lab session ends. Equipment’s need to handle smooth.
Usage
House Keeping Students should keep their work station neat and clean.
Record will be written individually. Please complete the cover Page and certificate
page: Include your name, USN, Subject , subject Code, Semester, Academic year. Fill
Lab records
Inside pages with Experiment No., Date and Page No.

Each laboratory station is equipped with a Power supply, CRO, Function generator,
Hardware
Digital Multi-meter, components and PCBs. Students work in groups of two, but
Laboratory
maintain individual lab Observation books and submit
Usage
individual records.

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ANALOG AND DIGITAL CIRCUITS LAB

2022 SCHEME

Course code: 22EE33 Duration : 2 hrs/week

Course Objective
This course will enable students to:
1. Provide the knowledge for the analysis of transistor circuits.
2. Develop skills to design the electronic circuits using transistor circuits.
3. Illustrate simplification of Algebraic equations using Karnaugh Maps and VEM
technique.
4. Design combinational logic circuits.
5. Describe Latches and Flip-flops, Registers and Counters.
6. Design and development of Mealy and Moore Models for digital circuits.
7. Develop state diagrams for Synchronous Sequential Circuits.

COURSE OUTCOMES:

At the end of the course, the student will be able to:

Mapping of Course outcomes to Program outcomes and Program Specific Outcomes:

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Analog and Digital Circuits Laboratory Course Contents:

List of Experiments
Sl. No. Course Content Hours COs
I CYCLE EXPERIMENTS
1 Testing of Diode clipping (Single/Double ended) circuits for peak clipping, 02 1,2,3
peak detection.(Series & Shunt clippers)
2 Testing of Clamping circuits: positive clamping /negative clamping. 02 1,2,3

3 Testing for the performance of BJT - Crystal Oscillator for f0 > 100 KHz 02 1,2,3
4 Testing for the performance of BJT – Hartley & Colpitts 02 1,2,3
Oscillators for RF range f0 ≤ 100KHz.

5 Wiring and Testing for the performance of BJT-RC Phase 02 1,2,3

shift Oscillator for f0 ≤ 10 KHz.

II CYCLE EXPERIMENTS
Introduction : Basics of Digital Circuits 2,3,4
6 Simplification, realization of Boolean expressions using logic gates/Universal 02 1,2,3,4
gates and realization of Half/Full adder and Half/Full Sub tractors using logic
gates.
7 Realization of parallel adder/Sub tractors using 7483 chip and code converters 02 1,2,3,4

8 MUX/DEMUX – use of 74153, 74139 for arithmetic circuits. 02 1,2,3,4

9 Truth table verification of Flip-Flops: JK Master slave and Realization of 3 bit 02 1,2,3
counters as a sequential circuit using JK flipflops.
10 Shift left, Shift right, SIPO, SISO, PISO, PIPO operations using 74S95 and 02 1,2,3,4
Wiring and testing Ring counter, Johnson counter.

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Aim:
To obtain output & transfer characteristics of different clipping circuits.

Apparatus/Components required:
Resistor 10kΩ, Diodes IN 4007 , VRPS, Function Generator, Multi-meter, CRO, CRO Probes
&Connecting wires.

Procedure:
1. Rig up the circuits as shown in the circuit diagram.
2. Apply a sinusoidal signal of frequency 1 KHz & amplitude 12V (peak-to-peak)
3. Apply DC reference voltage =2.4 Volts to the circuit using VRPS.
4. Observe i/p & o/p waveforms on CRO.
5. Also observe transfer characteristics by putting CRO in XY mode.
6. Compare the waveforms obtained with the expected waveforms.

CIRCUIT DIAGRAM :
Set the Input : Vin = 5V Amplitude, 1KHz Frequency , RL =10KΩ , D=IN4007 , VB =2.4 V

1. SHUNT CLIPPERS:
(a) Positive clipping circuit

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(b) Negative Clipping circuit

2. SERIES CLIPPERS :
(a) Positive clipping circuit

(b) Negative Clipping circuit

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3. Double ended clipping circuit : Set VB1 =3.4 Volts , VB2 =1.4 Volts

Transfer Characteristics :

Positive clipping circuit Negative clipping circuit Double ended clipping

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Applications :
● Used for the generation and shaping of waveforms
● Used for the protection of circuits from spikes
● Used for amplitude restorers
● Used as voltage limiters
● Used in television circuits
● Used in FM transmitters

Result :

The output and transfer characteristics of different clipping circuits are studied and performed.

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Aim : To observe the waveforms of Positive and Negative clamping circuits.

Apparatus/Components required:

Resistor 10kΩ, Capacitor 1μF& Diode IN 4007, VRPS, Function Generator, Multi-meter, CRO,
CRO Probes & Connecting wires.
Procedure:
1. Rig up the circuits as shown in the circuit diagram.
2. Apply a sinusoidal signal of frequency 1 KHz & amplitude 12V (peak-to-peak)
3. Apply DC reference voltage to the circuit using VRPS.
4. Observe i/p & o/p waveforms on CRO.
5. Compare the waveforms obtained with the expected waveforms and note down the
clamping voltage from CRO.

CIRCUIT DIAGRAM:
Set the Input : Vin = 6V Amplitude, 1KHz Frequency
RL =10KΩ ,C= 1µF, D=IN4007 , Vr =2Volts

1)Positive Clamper with Positive Vr

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2) Negative Clamper with Negative Vr

Model Graphs:
1)Positive clamper: 2) Negative clamper:

Observations & Calculations :

Vo (max) = Vγ + Vref (positive clamping)
Vo(min) = Vγ - Vref (negative clamping) Where Vγ≈ 0.6V

To clamp positive peak at +3V , Choose Vref = Vo(max) - Vγ = 3V - 0.6V = 2.4V

To clamp negative peak at -3V , Choose Vref = Vo(min) +Vγ = -3V + 0.6V = -2.4V

Applications :
● Used as direct current restorers
● Used to remove distortions
● Used as voltage multipliers
● Used for the protection of amplifiers
● Used as test equipment
Result : The clamper circuit output waveforms have been studied and the required parameters have
been compared.

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EXPERIMENT: 03

Aim: Design and set-up the crystal oscillator and determine the frequency of oscillation.
Apparatus/Components required:
Transistor SL 100, Crystal – 2MHz, Resistors 22KΩ, 1KΩ , 4.7 KΩ , 1K Pot and 330 Ω, Capacitors 47 µf
Power supply, CRO, Connecting wires

Procedure:
1. Rig up the circuit as shown.
2. Adjust DC voltage to 12 V in VRPS & Check for DC conditions.
DC Condition:
Apply 12 V DC to the transistor circuit. Measure the voltage between collector to emitter using
multi-meter.
Multi-meter selector switch must be in DC voltage mode. The multi-meter reading should be
approximately 6 V or slightly more (VCE = ). This indicates that transistor is properly biased.
3. Vary 1K pot till a sine wave o/p is observed on CRO By connecting CRO probe between Vo
& ground.
4. Measure the time taken to complete one full cycle on X -axis of CRO. Calculate
frequency of oscillations using the expression 1/T.
CIRCUIT DIAGRAM

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MODEL GRAPH

APPLICATIONS:
● Most are used for consumer devices such as wristwatches, clocks, radios, computers, and
cellphones.
● However in applications where small size and weight is needed crystals can be replaced by
thin-film bulk acoustic resonators, specifically if high frequency (more than roughly 1.5
GHz) resonance is needed.

RESULT :

Performance of BJT - Crystal Oscillator for f0 > 100 KHz tested practically .
Theoretical frequency f0 = 2MHz

Practical frequency f0 = 1/T = -----------------------

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Aim: To test the performance of BJT Hartley and Colpitts Oscillator for RF range f0<100KHz

Apparatus/Components required:
Resistors, BJT (SL 100), Capacitors & Inductors, VRPS, Multi-meter, CRO, CRO Probes, Connecting wires.

Procedure:
1. Rig up the circuit as shown.
2. Adjust DC voltage to 12 V in VRPS & Check for DC conditions.

DC Condition:
Apply 12 V DC to the transistor circuit. Measure the voltage between collector to emitter using
multi-meter.
Multi-meter selector switch must be in DC voltage mode. The multi-meter reading should be
approximately 6 V or slightly more (VCE = ). This indicates that transistor is properly biased.
3. Vary 1K pot till a sine wave o/p is observed on CRO By connecting CRO probe between Vo
& ground.
4. Measure the time taken to complete one full cycle on X -axis of CRO. Calculate
frequency of oscillations using the expression 1/T.

Hartley Oscillator:

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Colpitt’s Oscillator:

NATURE OF GRAPH:

Observations & Calculations

fo = 1/(2π√LT C) Hartley Oscillator

Colpitts Oscillator

Where Ceq = C1 * C2 Colpitts Oscillator

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C1 + C2
LT= L1 + L2 Hartley Oscillator
Applications :
● The Hartley oscillator is to produce a sine wave with the desired frequency.
● Hartley oscillators are mainly used as radio receivers.
● The Hartley oscillator is suitable for oscillations in RF (Radio-Frequency) range, up to 30MHZ.
● Colpitts oscillators are used for high frequency range and high frequency stability
● Colpitts oscillators are used for a surface acoustical wave (SAW) resonator
● Colpitts oscillators are used for Microwave applications
● Colpitts oscillators are used for Mobile and communication systems
● These are used in chaotic circuits which are capable to generate oscillations from audio frequency
range to the optical band. These application areas include broadband communications, spectrum
spreading, signal masking, etc.

Result : Performance of Hartley & Colpitt’s Oscillators are tested.

Theoretical frequency fo (Hartley ) = 11.25 KHz
fo (Colpitts ) = 71.11 KHz

Practical frequency : fo (Practical) =1/T Hz

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Aim: To rig up the RC phase shift oscillator circuit & test its performance for f0 < 10KHz
Apparatus/Components required:
Resistors, BJT (SL 100) & Capacitors,VRPS, Multi-meter, CRO, CRO Probes & Connecting
wires.

Procedure:
1. Rig up the circuit as shown.
2. Adjust DC voltage to 12 V in VRPS & Check for DC conditions.

DC Condition:
Apply 12 V DC to the transistor circuit. Measure the voltage between collector to emitter
using multimeter. Multimeter selector switch must be in DC voltage mode. The multimeter
reading should be approximately 6V or slightly more (VCE= ). This indicates that
transistor is properly biased.

3. Vary 10K pot till a sine wave o/p is observed on CRO By connecting CRO probe between
V0& ground..
4. Measure the time taken to complete one full cycle on X -axis of CRO. Calculate
frequency of oscillations using the expression 1\T.
5. Observe the phase shift by connecting CRO probes at points A, B & C
6. Compare the practical value of frequency obtained with the theoretical value given by the
following expression.

CIRCUIT DIAGRAM

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Observations & Calculations

fo =

Where K = (Rc is the resistor connected from collector to Vcc)

K =0.4545

fo (theoretical) = 2.587 KHz

Practical frequency : fo (Practical) =1/T Hz

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Applications :
● RC phase shift oscillators can be used for low-frequency applications, such as devices which
produce radio and audio frequencies.
● To be more specific, they are used for musical instruments, voice synthesis, and GPS units,
or any other device that uses an oscillator but has a cost pressure.

RESULT:

Observed the waveform and measured the frequency of oscillations.

Frequency of output waveform = kHz

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PART - B
DIGITAL ELECTRONICS EXPERIMENTS

Introduction : Basics of Digital Circuit

6. Simplification, realization of Boolean expressions using Universal gates and realization of Half/Full
adder and Half/Full Sub tractors using logic gates.

7. Realization of parallel adder/Subtractors using 7483 chip and code convertors.

8. MUX/DEMUX – use of 74153, 74139 for arithmetic circuits

Truth table verification of Flip-Flops: JK Master slave and Realization of 3 bit counters as a sequential
9. circuit using JK flip-flops.

10. Shift left, Shift right, SIPO, SISO, PISO, PIPO operations using 74S95 and Wiring and testing Ring
counter, Johnson counter.

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BASICS OF DIGITAL CIRCUITS:

Verification of truth tables of logic gates using Integrated Circuits
COMPONENTS REQUIRED:

1 AND gate IC 7408

2 NOT gate IC 7404
3 OR gate IC 7432
4 NAND gate IC 7400
5 NOR gate IC 7402
6 X-OR gate IC 7486

Components required: Power supply, Digital IC trainer kit, connecting wires.

BOOLEAN EXPRESSIONS

Pin Identification

Note:

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The chip must be inserted in the bread board in such a way that the identification mark should be on
our left side. In this position, pin numbers are counted as marked in the picture above. Pin
identification is the same for all chips that are mentioned below.

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PROCEDURE

● To verify the truth table of a logic gate, the suitable IC is taken and the connections are
given using the circuit diagram.

● For all the ICs, 5V is applied to the pin 14 while the pin 7 is connected to the ground.

● The logical inputs of the truth table are applied and the corresponding output is noted.

● Similarly the output is noted for all other combinations of inputs.

● In this way, the truth table of a logic gate is verified.

RESULT

The truth table of logic gates AND, OR, NOT, Ex-OR, NAND and NOR using integrated circuits is
verified.

Precautions

(i) VCC and ground pins must not be interchanged while making connections. Otherwise the
chip will be damaged.

(ii) The pin configuration for NOR gate is different from other gates

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AIM: Simplification, realization of Boolean expressions using Universal gates and realization
of Half/Full adder and Half/Full Subtractors using logic gates.
a) Simplification & realization of logical expressions using Universal gates.
(i) SOP form (ii) POS form
Components required:-

NAME OF THE
Sl.No IC NUMBER
COMPONENT
1 AND gate 7408
2 OR gate 7432
3 Not gate 7404
4 EXOR gate 7486
5 NAND gate 7400
6 NOR gate 7402
7 Patch chords
8 Trainer Kit

THEORY: To minimise a boolean expression we can employ any one of the

following techniques:
i) Boolean Algebra
ii) Karnaugh maps.
Before we proceed to simplification techniques, two forms of the Boolean expression must be noted.

a) Sum of product (SOP): Ex: ABC+AB+AC

b) Product of Sum (POS)
Ex:(A+B+C)(A+B)+(A+C)

a) SUM OF PRODUCT (SOP): F(A,B,C,D) = ∑(5,7,9,11,13,15)

Simplification- SOP form Using Basic Gates

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Using NAND gates Using NOR Gates

b) PRODUCT OF SUM : F(A,B,C,D) = ∏(0,1,2,3,4,6,8,10,12,14)

Simplification- POS form Using Basic Gates

Using NAND gates Using NOR gates

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TRUTH TABLE:
A B C D Y=(A+B)D
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 1
0 1 1 0 0
0 1 1 1 1
1 0 0 0 0
1 0 0 1 1
1 0 1 0 0
1 0 1 1 1
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1

PROCEDURE:
i) Place the IC in the socket of the trainer kit.

ii) Make the connections as shown in the circuit diagram.

iii) Apply diff combinations of inputs according to the truth table and verify the output.
iv) Repeat the above procedure for all the circuit diagrams.

*NOTE: The Truth Table is common for Both SOP and POS form.

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b) To realize and verify

i. Half adder and Full adder
ii. Half subtractor and Full subtractor using basic gates.

COMPONENTS REQUIRED:

IC 7400, IC 7408, IC 7486, and IC 7432,

Patch cards and IC Trainer Kit

THEORY :
Half-Adder: A combinational logic circuit that performs the addition of two data bits, A and
B, is called a half- adder. Addition will result in two output bits; one of which is the sum bit,
S, and the other is the carry bit, C. The Boolean functions describing the half-adder are:
S =A ⊕ B C = A B

Full-Adder: The half-adder does not take the carry bit from its previous stage into account.
This carry bit from its previous stage is called carry-in bit. A combinational logic circuit that
adds two data bits, A and B, and a carry-in bit, Cin, is called a full-adder. The
Boolean functions describing the full-adder are:
S = (x ⊕ y) ⊕ Cin C = xy + Cin (x ⊕ y)

Half Subtractor: Subtracting a single-bit binary value B from another A (i.e. A –B)
produces a difference bit D and a borrow out bit B-out. This operation is called half subtraction
and the circuit to realize it is called a half subtractor. The Boolean functions describing the half
Subtractor are:
D =A ⊕ B Br = A’ B

Full Subtractor: Subtracting two single-bit binary values, B, Cin from a single-bit value A
produces a difference bit D and a borrow out Br bit. This is called full subtraction. The
Boolean functions describing the full-subtractor are:
D = (x ⊕ y) ⊕ Cin Br = A’B + A’ (Cin) + B (Cin)

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HALF ADDER USING BASIC GATES

TRUTH TABLE

Inputs Outputs
A B Sum(S) Carry©

0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

FULL ADDER CIRCUIT USING BASIC GATES

Inputs Outputs
A B Cin Sum (S) Carry (Cout)
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0

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1 0 1 0 1
TRUTH TABLE
1 1 0 0 1
1 1 1 1 1

HALF SUBTRACTOR USING BASIC GATES TRUTH TABLE

Inputs Outputs
A B Differenc Borro
e w
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

FULL SUBTRACTOR CIRCUIT using basic gates

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Truth Table

The K-map of this Subtractor can be determined based on 1’s generated for the applied inputs. The
expression derived for the Difference can be obtained based on the 1’s presence in the Kmap is:

Difference (D)= A ⊕B⊕C

The K-map for the Borrow outcome generated for the applied input signal is

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The equation obtained for the Borrow analysed from the k-map is:

PROCEDURE
1. Verify the all gates according to respective truth tables.
2. Make the connections as per the circuit diagram.
3. Switch on VCC and apply various combinations of input according to the truth table.
4. Note down the output readings for half and full adder sum and the
carry bit for different combinations of inputs.

Applications :
1.These are generally employed for ALU in computers to subtract as CPU and GPU for applications
of graphics to decrease the circuit difficulty.
2. Subtractors are mostly used for performing arithmetical functions like subtraction in electronic
calculators and digital devices.
3.These are also applicable for different microcontrollers for arithmetic subtraction, timers and
program counter (PC)
4. Subtractors are used in processors to compute tables, address, etc. By using any full subtractor
logic circuit, full subtractor using NAND gates and full subtractor using NOR gates can be
implemented since both the NAND and NOR gates are treated as universal gates.

RESULT: Half adder, Full adder, Half subtractor and Full subtractor using basic gates are
verified.

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AIM: (i) Realization of Parallel adder/subtractor using 7483 chip.

Components required :-

Sl.No NAME OF THE IC NUMBER

COMPONENTS
1 EXOR gate 7486
2 4 bit parallel adder / subtractor 7483
3 Trainer Kit
4 Patch chords

THEORY:
The IC 7483 is a 4- bit parallel adder IC that contains four inter connected FAs high speed
operation.The inputs to this IC are two 4-bit numbers A3,A2,A1,A0 & B3,B2,B1,B0 and the carry
Cin in to the LSB position.The outputs are the sum bits ∑3, ∑2,∑1,∑0. and the Cout of the b
position.

Pin diagram:

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REALISATION of Parallel adder/subtractor using 7483chip

Block Diagram

TRUTH TABLE FOR PARALLEL ADDER

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PARALLEL SUBTRACTOR

Working of Parallel Subtractor –

1. As shown in the figure, the parallel binary subtractor is formed by combination of all full adders
with subtrahend complement input.
2. This operation considers that the addition of minuend along with the 2’s complement of the
subtrahend is equal to their subtraction.
3. Firstly the 1’s complement of B is obtained by the NOT gate and 1 can be added through the
carry to find out the 2’s complement of B. This is further added to A to carry out the arithmetic
subtraction.
4. The process continues till the last full adder FAn uses the carry bit Cn to add with its input An
and 2’s complement of Bn to generate the last bit of the output along last carry bit Cout.

TRUTH TABLE :

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Procedure:

1) Make the connections as shown .

2) For addition, make Cin=0 and apply the 4 bits as i/p for A and apply another set of 4 bits to
B. Observe the o/p at S3, S2 S1 S0 and carry generated at Cout.
Repeat the above steps for different inputs and tabulate the result.

3) For subtraction make Cin=1 and A-B format is used. By Xoring the i/p bits of ‘B’ by 1,
complement of ‘B’ is obtained. Further Cin which is 1 is added to the LSB of the Xored
bits. This generates 2’s complement of B.

4) Verify the difference and polarity of differences at S0, S1, S2, and S3 and Cout. If Cout is
0 , diff is –ve and diff is in 2’s complement form. If Cout is 1, diff is +ve . Repeat the
above steps for different inputs and tabulate the result.
Advantages of parallel Adder/Subtractor –

1. The parallel adder/subtractor performs the addition operation faster as compared to serial
adder/subtractor.
2. Time required for addition does not depend on the number of bits.
3. The output is in parallel form i.e all the bits are added/subtracted at the same time.
4. It is less costly.
Disadvantages of parallel Adder/Subtractor –
1. Each adder has to wait for the carry which is to be generated from the previous adder in chain.
2. The propagation delay( delay associated with the travelling of carry bit) is found to increase
with the increase in the number of bits to be added.
The applications of Parallel Adder include:

● BCD to excess- 1 code converter.

● They are used in the analysis of Multiplication Algorithms. Parallel Cellular Automata Machines
(CAMs) are incorporated with Parallel Adder Circuits for Parallel Computing.
● They are also used in VLSI implementation for low power applications.
● Parallel Adders are used in ALU for heavy computing environment.

Result : Realization of Parallel adder & Subtractor using IC 7483 is verified.

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(ii) To realize BCD to Excess-3 code conversion and vice versa using IC 7483

COMPONENTS REQUIRED:

Digital Trainer Kit

EXOR Gate IC 7486
4-bit binary full adder IC 7483
Patch chords / Connecting wires
THEORY
Code converter is a combinational circuit that translates the input code word into a new
corresponding word. In this code each decimal digit is represented by a 4 -bit binary number. BCD
is a way to express each of the decimal digits with a binary code. In the BCD, with four bits we
can represent sixteen numbers (0000 to 1111). But in BCD code only first ten of these are used
(0000 to 1001). The remaining six code combinations i.e. 1010 to 1111 are invalid in BCD.

To Construct a BCD-to-excess-3-code converter with a 4-bit adder feed BCD code to the 4- bit
adder as the first operand and then feed constant 3 (0011) as the second operand. The output is the
corresponding excess-3 code. To make it work as a excess-3 to BCD converter, we feed excess-3
code as the first operand and then feed 2's complement of 3 as the second operand. The output is
the BCD code.
Excess-3 Code - It is non-weighted code used to express decimal numbers. The Excess -3 code
words are derived from the 8421 BCD code words adding (0011) 2 or (3)10 to each code word in
8421.

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CIRCUIT DIAGRAM: BCD to EXCESS -3 / EXCESS -3 to BCD Conversion

PROCEDURE

1) Check all the components for their working.

2) Insert the appropriate IC into the IC base.
3) Make connections as shown in the circuit diagram.
4) Verify the Truth Table and observe the outputs.

ADVANTAGES

▪ These are unweighted binary decimal codes.

▪ These are self-complementary codes.
▪ These use biased representation.
▪ The codes 0000 and 1111 are not used for any digit which is an advantage for memory organization
as these codes can cause fault in transmission line

RESULT: BCD to Excess-3 code conversion and vice versa using IC 7483 are realized.

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AIM: (i) To Realise 4:1 MUX using IC 74153

Components Required :
MUX – IC 74153
Digital Trainer Kit , Patch cords
Theory :
Multiplexer
● Multiplexer means many into one. A multiplexer is a circuit used to select and route any one of the
several input signals to a single output. A simple example of an non-electronic circuit of a
multiplexer is a single pole multi-position switch.
● Multi-position switches are widely used in many electronics circuits. However, circuits that
operate at high speed require the multiplexer to be automatically selected. A mechanical switch
cannot perform this task efficiently. Therefore, multiplexer is used to perform high speed switching
are constructed of electronic components.
● Multiplexers can handle two type of data i.e., analog and digital. For analog application,
multiplexer are built using relays and transistor switches. For digital application, they are built
from standard logic gates.
● The multiplexer used for digital applications, also called digital multiplexer, is a circuit with many
input but only one output. By applying control signals (also known as Select Signals), we can steer
any input to the output. Some of the common types of multiplexer are 2-to-1, 4-to-1, 8-to-1,
16-to-1 multiplexer.
Demultiplexer
● Demultiplexer means one to many. A demultiplexer is a circuit with one input and many outputs.
By applying control signal, we can steer any input to the output. Few types of demultiplexer are
1-to 2, 1-to-4, 1-to-8 and 1-to 16 demultiplexer.

● It is used to send a signal to one of the many devices. The main difference between a multiplexer
and a de-multiplexer is that a multiplexer takes two or more signals and encodes them on a wire,
whereas a de-multiplexer does reverse to what the multiplexer does.

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MUX
Truth table (4:1 MUX) SYMBOL

S1 S0 I0 I1 I2 I3 Y
0 0 I0 X X X I0
0 1 X I1 X X I1
1 0 X X I2 X I2
1 1 X X X I3 I3
PIN DETAILS OF 74153

IC 74153 : IC 74153 is a dual 4-i/p mux that can select 2 bits of data from up to eight sources
under the control of the common select inputs (S0,S1). The two 4- i/p Mux circuits have individual
active low enables (E1,E2) which can be used to strobe the outputs independently outputs (Y1,Y2)
are forced low when the corresponding enables (E1,E2) are high.

TRUTH TABLE FOR MUX 74153(DUAL 4:1 MUX)

E S1 S0 Yn
1 X X 0
0 0 0 An

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0 0 1 Bn
0 1 0 Cn
0 1 1 Dn

When E1 and E2 =1, device is not enabled and outputs are zero
Realization of Full Adder Using IC 74153

Here the outputs sum and carry out are represented in Terms of input Cin

A B SU Cout
M
0 0 Cin 0
0 1 Cin

1 0 Cin

1 1 Cin 1

A B Cin SUM Cout

0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

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(ii)To Realise 1:4 DEMUX using IC 74139

SYMBOL

IC74139 DEMUX/FUNCTIONAL TABLE

B(S1) A(S0) Y3 Y2 Y1 Y0
1 X X 1 1 1 1
0 0 0 1 1 1 0
0 0 1 1 1 0 1
0 1 0 1 0 1 1
0 1 1 0 1 1 1

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IC 74139: The IC 74139 is a high speed dual 1 of 4 decoder/ demultiplexer. this device has two
independent decoders each accepting two binary weighted inputs (a, b) and providing four mutually
exclusive active low output(Y0- Y3).each decoder has an active low enable (E) when E=1 every o/p
is forced high. The enable can be used as the data input for a 1 of 4 DEMUX application.

Procedure:

1) Rig up the circuit using IC 74153 for MUX & using IC 74139 for DEMUX as shown in
figure.
2) Verify the output with the truth table values.
3) The output obtained practically should match the required result.

Applications of Multiplexers

Multiplexers are used in various applications wherein multiple-data need to be transmitted by using
a single line Communication System, Computer Memory, Telephone Network, Transmission from
the Computer System of a Satellite.

Applications of Demultiplexers

Communication System, Arithmetic Logic Unit, Serial to Parallel Converter etc.

Result : Realization of MUX using 74153 & DEMUX using 74139 IC for arithmetic circuits is
verified.

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Aim : Truth table verification of Flip-Flops: JK Master slave and Realization of 3 bit counters as a
sequential circuit using JK flip-flops using IC 7476.

COMPONENTS REQUIRED:

JK FLIP FLOP – IC 7476

Digital Trainer Kit
Patch chords / Connecting wires

THEORY
Flip-Flops are binary cells capable of storing one bit of information. A Flip Flop has two outputs, one for
the normal value and one for complement value of the bit stored in it.

JK FLIP-FLOP : The full form of JK Flip-Flop Jack Kilby flip flop.It is basically an SR flip
flop with feedback which enables only one of its two input terminals, either SET or RESET to
be active at any one time under normal switching thereby eliminating the invalid condition of
SR flip flop. However, if J = K = 1 and clock input is applied the circuit will “toggle” as its
outputs switch and change state complementing each other. This timing problem called “race”.
The master-slave flip- flop eliminates all the timing problems by using two SR
flip-flops connected together in a series configuration. One flip-flop acts as the “Master”
circuit, which triggers on the leading edge of the clock pulse while the other acts as the
“Slave” circuit, which triggers on the falling edge of the clock pulse. This results in the two
sections, the master section and the slave section being enabled during opposite half-cycles of
the clock signal.

D FLIP-FLOP: It has only one data input (D) and clock input (CP). The outputs are labeled Q and Q’.
The data (0 or 1) at the input 0 is delayed one clock pulse from getting to output Q. SD and CD are
active low input (Negative edge trigger) to set and reset the Flip-Flop i.e. these inputs will be effective

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when logic 0 is applied. A D Flip-flop is a bi-stable circuit whose 0 input is transferred to the output after
a clock pulse is received.

T FLIP-FLOP This T Flip-Flop is obtained from a JK type if both inputs are tied together. The
designation T shows ability of Flip-Flop to toggle. Regardless of the present state of the Flip-Flop, it
assumes the complement state when the clock pulse occurs while input T is logic1. When T=0, both
AND gates are disabled and hence there is no change in the previous output. When T=1, (J=K=1) output
toggles.

Pin Details of 7476 Master slave FF

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T- Type FF using MS JK FF

D - Type FF using MS JK FF

PROCEDURE

1) Turn on power to the circuit.

2) For each input combination, note the logic state of the normal (Q) and complementary
(Ǭ) outputs as indicated by the LEDs (ON = 1; OFF = 0), and record the results in a
table.
3) Compare your results with the truth tables.

Applications of JK Flip Flop:

Registers, Counters, Event detectors, Data Synchronizers, Frequency divider etc.

Result : Verification of J K Flip flops using IC 7476 is performed & Truth Table is verified.

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AIM: (i) To realize different types of shift registers Shift left, Shift Right , Serial In Serial Out
[SISO], Serial In Parallel Out [SIPO], Parallel In Parallel Out [PIPO] and Parallel In Serial
Out [PISO] using IC 7495 and to verify function table.

COMPONENTS REQUIRED
Trainer Kit
IC 7495 01
IC 7404 01
Patch chord 20

THEORY

The binary information (data) in a register can be moved within or into or out of the register
upon application of clock pulses. This type of bit movement or shifting is essential for certain
arithmetic and logic operations used in microprocessors. This gives rise to group of registers
called shift registers. They are very important in applications involving the storage and
transfer of data in a digital system.

Types of shift registers:

i) Serial In Serial Out [SISO]:
In this type of register, the output of one flip-flop is connected to the input of the next
flip-flop. Output of the register is obtained from the last flip-flop. Depending on the direction
of the input given shifting takes place in this. Bit by bit loading and shifting takes place with
every clock pulse.

ii)Serial In Parallel Out [SIPO]:

This is similar to SISO except that the output is taken from each flip-flop. Thereby the shifted
value is shown at once.

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iii)Parallel In Parallel Out [PIPO]:

Upon giving clock pulse, data is loaded in parallel in all flip-flops. Output is taken from each of the
flip-flop.

iv) Parallel In Serial Out [PISO]:

Here we use a control input Load/ (Shift) such that if Load/ (Shift) = 1, data is loaded in all
flip-flops in parallel and when the Load/ (Shift) = 0, data is shifted with every clock pulse. Output
is obtained from the last flip-flop.

3 Modes of Operation of IC 7495: Parallel, Shift right and Shift Left

Parallel Shift right Shift Left

Mode control = 1 Mode control = 0 Mode control = 1
Clock-2 = HIGH to LOW Clock-1 = HIGH to LOW Clock-2 = HIGH to LOW

Pin Diagram of IC 7495

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PROCEDURE:

1. Connections are made as per circuit diagram.

2. Apply the data at serial i/p (pin-1)
3. Apply one clock pulse at clock 1 (Right Shift) observe this data at QA.
4. Apply the next data at serial i/p.
5. Apply one clock pulse at clock 2, observe that the data on QA will shift to QB and the
new data applied will appear at QA.
6. Repeat steps 2 and 3 till all the 4 bits data are entered one by one into the shift register.

PROCEDURE

1. Connections are made as per circuit diagram.

2. Load the shift register with 4 bits of data one by one serially.
3. At the end of 4th clock pulse the first data ‘d0’ appears at QD.
4. Apply 5th clock pulse; the second data ‘d1’ appears at QD.
5. Apply 6th clock pulse; the third data appears at QD.
6. Application of next clock pulse will enable the 4th data ‘d3’ to appear at
QD. Thus the data applied serially at the input comes out serially at QD.

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PROCEDURE

1. Connections are made as per circuit diagram.

2. Apply the desired 4-bit data at A, B, C and D.
3. Keeping the mode control =1 apply one clock pulse. The data applied at A,
B, C and D will appear at QA, QB, QC and QD respectively.
4. Now mode control = 0. Apply clock pulses one by one and observe the data
coming out serially at QD.

PROCEDURE

1. Connections are made as per circuit diagram.

2. Apply the 4 bit data at A, B, C and D.
3. Apply one clock pulse at Clock 2 (Note: Mode control =1).
4. The 4 bit data at A, B, C and D appears at QA, QB, QC and QD respectively.
Applications of Shift Registers

Registers are used in digital electronic devices like computers as

● Temporary data storage
● Data transfer
● Data manipulation
● As counters.
Shift registers are used in computers as memory elements. All the digital systems need to store large
amount of data, in an efficient manner; there we use storage elements like RAM and other type of
registers.

Many of the digital system operations like division, multiplication are performed by using registers.
The data is transferred through serial shift registers and other type.

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● Serial in – serial out register are used for time delays.

● Serial in – parallel out registers are used for converting the data from serial form to parallel
form. So these are also called “Serial to parallel converters”.
● Parallel in – serial out registers are used for converting the data from parallel form to serial
form. So these are also called “Parallel to serial converters”.

RESULT: Shift registers using IC 7495 for SIPO/SISO, PISO/PIPO are verified.

AIM: ii) To realize Ring counter and Johnson counter using IC 7495

COMPONENTS REQUIRED

Trainer Kit
IC 7495
IC7404
Patch chords

THEORY

RING COUNTER :
A ring counter is a circular shift register which is initiated such that only one of its flip-flops is
the state one while others are in their zero states. A ring counter is a Shift Register with the
output of the last one connected to the input of the first, that is, in a ring. Typically, a pattern
consisting of a single bit is circulated so the state repeats every n clock cycles if n flip-flops are
used. It can be used as a cycle counter of n states.

JOHNSON COUNTER :
A Johnson counter (or switch tail ring counter, twisted-ring counter) is a modified ring counter,
where the output from the last stage is inverted and fed back as input to the first stage. The
register cycles through a sequence of bit-patterns, whose length is equal to twice the length of
the shift register, continuing indefinitely. These counters find specialist applications, including
those similar to the decade counter, digital-to-analog conversion, etc. They can be implemented
easily using D- or JK-type flip-flops.

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RING COUNTER: FUNCTION TABLE

JOHNSON COUNTER: FUNCTION TABLE

PROCEDURE:
1. Make the connections as shown in the respective circuit diagram.
2. Initial condition is set by setting up the circuit as shown in the figure.
3. Apply clock and observe the output after each clock pulse, record the
observations and verify that they match the expected outputs from the truth table.

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4. Verify the operation of ring counter/Johnson counter circuit as per the function tables

Applications :
● Ring counters are used to count the data in a continuous loop.
● They are also used to detect the various numbers values or various patterns within a set of
information, by connecting AND & OR logic gates to the ring counter circuits.
● Johnson counters are used as frequency dividers and pattern recognizers.
● It is used as a synchronous decade counter and divider circuit.
● It can be used to create complicated finite state machines in hardware logic design.

RESULT: Ring counter and Johnson counter using IC 7495 are verified

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