x1 z1

n input x2 z2 m output
. .
variables . . variables
. .
xn zm

Combinational
circut
y1 Y1
k secondary k excitation
variables y2 Y2 variables
(present . . (next state)
. .
state) . .
yk Yk

Delay

Delay

© 2002 Prentice Hall, Inc. Delay

M. Morris Mano
DIGITAL DESIGN, 3e. Fig. 9-1 Block Diagram of an Asynchronous Sequential Circuit
 y1
x Y1

y2

Y2

Fig. 9-2 Example of an Asynchronous Sequential Circuit

© 2002 Prentice Hall, Inc.

M. Morris Mano
DIGITAL DESIGN, 3e.
 x x x
0 1 0 1 0 1
y1 y2 y1 y2 y1 y2
00 0 0 00 0 1 00 00 01

01 1 0 01 1 1 01 11 01

11 1 1 11 1 0 11 11 10

10 0 1 10 0 0 10 00 10

(a) Map for (b) Map for (c) Transition table

Y 1 = xy 1 + x'y 2 Y 2 = xy' 1 + x'y 2

Fig. 9-3 Maps and Transition Table for the Circuit of Fig. 9-2

© 2002 Prentice Hall, Inc.

M. Morris Mano
DIGITAL DESIGN, 3e.
 x
0 1
x 1 x2
a a b
00 01 11 10

b c b a a ,0 a ,0 a ,0 b ,0

b a ,0 a ,0 b ,1 b ,0
c c d

(b) Two states with two

d a d inputs and one output

(a) Four states with

one input

Fig. 9-4 Examples of Flow Tables

© 2002 Prentice Hall, Inc.

M. Morris Mano
DIGITAL DESIGN, 3e.
 x 1 x2 x1 x2
00 01 11 10 00 01 11 10
y y
0 0 0 0 1 0 0 0 0 0

1 0 0 1 1 1 0 0 1 0

(a) Transition table (b) Map for output

Y = x1x'2 + x1y z = x1x2 y

x1
x2

(c) Logic diagram

Fig. 9-5 Derivation of a Circuit Specified by the Flow Table of Fig. 9-4(b)

© 2002 Prentice Hall, Inc.

M. Morris Mano
DIGITAL DESIGN, 3e.
 x x
0 1 0 1
y1 y2 y1 y2
00 00 11 00 00 11

01 11 01 01

11 11 11 01

10 11 10 11

(a) Possible transitions: (b) Possible transitions:

00 11 00 11 01
00 01 11 00 01
00 10 11 00 10 11 01

Fig. 9-6 Examples of Noncritical Races

© 2002 Prentice Hall, Inc.

M. Morris Mano
DIGITAL DESIGN, 3e.
 x x
0 1 0 1
y1 y2 y1 y2
00 00 11 00 00 11

01 01 01 11

11 11 11 11

10 10 10 10

(a) Possible transitions: (b) Possible transitions:

00 11 00 11
00 01 00 01 11
00 10 00 10

Fig. 9-7 Examples of Critical Races

© 2002 Prentice Hall, Inc.

M. Morris Mano
DIGITAL DESIGN, 3e.
 x x x
0 1 0 1 0 1
y1 y2 y1 y2 y1 y2
00 00 01 00 00 01 00 00 01

01 11 01 11 01 11

11 10 11 11 11 10

10 10 10 10 10 01

(a) State transition: (b) State transition: (c) Unstable

00 → 01 → 11 → 10 00 → 01 → 11 → 01 → 11 → 10

Fig. 9-8 Examples of Cycles

© 2002 Prentice Hall, Inc.

M. Morris Mano
DIGITAL DESIGN, 3e.
 y
x1 Y
x2

(a) Logic diagram

x1 x2
00 01 11 10
y
0 0 1 1 0

1 0 1 0 0

(b) Transition table

Fig. 9-9 Example of an Unstable Circuit

© 2002 Prentice Hall, Inc.

M. Morris Mano
DIGITAL DESIGN, 3e.
 R
1 Q S R Q Q'
1 0 1 0
0 0 1 0 (After SR ⫽ 10)
0 1 0 1
0 0 0 1 (After SR ⫽ 01)
2 Q'
S 1 1 0 0

(a) Crossed-coupled circuit (b) Truth table

SR

00 01 11 10
R y
1 Y=Q
0 0 0 0 1
S
2
1 1 0 0 1
y
Y ⫽ SR' + R'y
Y ⫽ S + R'y when SR ⫽ 0
(c) Circuit showing feedback (d) Transition table

Fig. 9-10 SR Latch with NOR Gates

© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
 S
1 Q S R Q Q⬘
1 0 0 1
1 1 0 1 (After SR ⫽ 10)
0 1 1 0
1 1 1 0 (After SR ⫽ 01)
2 Q⬘
R 0 0 1 1

(a) Crossed-coupled circuit (b) Truth table

SR

S 00 01 11 10
y
1 Y⫽Q
0 1 1 0 0
R
2
1 1 1 1 0
y

Y ⫽ S⬘ + Ry when S⬘R⬘ ⫽ 0

(c) Circuit showing feedback (d) Transition table

Fig. 9-11 SR Latch with NAND Gates

© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
 x1 R1
Y1

S1

y2

y1
R2
Y2

S2
x2

Fig. 9-12 Example of a Circuit with SR Latches

© 2002 Prentice Hall, Inc.

M. Morris Mano
DIGITAL DESIGN, 3e.
 x1 x2
00 01 11 10
y1 y2
00 00 00 01 00

01 01 01 11 11

11 00 11 11 10

10 00 10 11 10

Fig. 9-13 Transition Table for the Circuit of Fig. 9-12

© 2002 Prentice Hall, Inc.

M. Morris Mano
DIGITAL DESIGN, 3e.
 x 1x 2

y 00 01 11 10 y Y S R
0 0 0 X
0 0 0 0 1
0 1 1 0
1 0 0 1
1 0 0 1 1
1 1 X 1
(a) Transition table (b) Latch excitation table
Y = x 1x⬘ 2 + x 1y

x 1x 2 x 1x 2

y 00 01 11 10 y 00 01 11 10
0 0 0 0 1 0 X X X 0

1 0 0 X X 1 1 1 0 0

(c) Map for S = x 1x⬘ 2 (d) Map for R = x⬘ 1

x2
x1 R S
Y Y

x2 x1
S R

(e) Circuit with NOR latch (f) Circuit with NAND latch
© 2002 Prentice Hall, Inc.
M. Morris Mano Fig. 9-14 Derivation of a Latch Circuit from a Transition Table
DIGITAL DESIGN, 3e.
 S
Q
A

B
R Q'
Ground A B A

Fig. 9-15 Debounce Circuit

© 2002 Prentice Hall, Inc.

M. Morris Mano
DIGITAL DESIGN, 3e.
 DG
00 01 11 10

a c,– a ,0 b ,– – ,–

b – ,– a ,– b ,1 e,–

c c ,0 a ,– – ,– d ,–

d c,– – ,– b ,– d ,0

e f,– – ,– b ,– e ,1

f f ,1 a ,– – ,– e ,–

Fig. 9-16 Primitive Flow Table

© 2002 Prentice Hall, Inc.

M. Morris Mano
DIGITAL DESIGN, 3e.
 DG DG
00 01 11 10 00 01 11 10

a c,– a ,0 b ,– – ,– b – ,– a ,– b ,1 e,–

c c ,0 a ,– – ,– d ,– e f,– – ,– b ,– e ,1

d c,– – ,– b ,– d ,0 f f ,1 a ,– – ,– e ,–

(a) States that are candidates for merging

DG DG
00 01 11 10 00 01 11 10

a, c, d c ,0 a ,0 b ,– d ,0 a a ,0 a ,0 b ,– a ,0

b, e, f f ,1 a ,– b ,1 e ,1 b b ,1 a ,– b ,1 b ,1

(b) Reduced table (two alternatives)

Fig. 9-17 Reduction of the Primitive Flow Table

© 2002 Prentice Hall, Inc.

M. Morris Mano
DIGITAL DESIGN, 3e.
 DG DG
00 01 11 10 00 01 11 10
y y
0 0 0 1 0 0 0 0 1 0

1 1 0 1 1 1 1 0 1 1

(a) Y ⫽ DG + G'y (b) Q ⫽ Y

Fig. 9-18 Transition Table and Output Map for Gated Latch

© 2002 Prentice Hall, Inc.

M. Morris Mano
DIGITAL DESIGN, 3e.
 D

Y
Q

Fig. 9-19 Gated-Latch Logic Diagram

© 2002 Prentice Hall, Inc.

M. Morris Mano
DIGITAL DESIGN, 3e.
 DG DG
00 01 11 10 00 01 11 10
y y
0 0 0 1 0 0 X X 0 X

1 X 0 X X 1 0 1 0 0

(a) S
DG R
D'G

(a) Maps for S and R

D S
Q

(b) Logic diagram

© 2002 Prentice Hall, Inc.

FIG. 9-20 Circuit with SR Latch
M. Morris Mano
DIGITAL DESIGN, 3e.
 a a ,0 b ,– 0 0

b c ,– b ,0 X 0

c c ,1 d ,– 1 1

d a,– d ,1 X 1

(a) Flow table (b) Output assignment

Fig. 9-21 Assigning Output Values to Unstable States

© 2002 Prentice Hall, Inc.

M. Morris Mano
DIGITAL DESIGN, 3e.
 b d,e

f c,e
c,d
a,b

g d,e d,e

a b c d e f

Fig. 9-22 Implication Table

© 2002 Prentice Hall, Inc.

M. Morris Mano
DIGITAL DESIGN, 3e.
 00 01 11 10

a c,– a ,0 b ,– – ,–
b
b – ,– a ,– b ,1 e,–

c d,e
c c ,0 a ,– – ,– d ,–
d d,e
d c,– – ,– b ,– d ,0
c,f d,e
e
c,f
e f,– – ,– b ,– e ,1
d,e
f c,f
c,f
f f ,1 a ,– – ,– e ,–
a b c d e

(a) Primitive flow table (b) Implication table

Fig. 9-23 Flow and Implication Tables

© 2002 Prentice Hall, Inc.

M. Morris Mano
DIGITAL DESIGN, 3e.
 a a

h b
f b

g c

e c
f d

d e
(a) Maximal compatible: (b) Maximal compatible:
(a, b,) (a, c, d) (b, e, f) (a, b, e, f) (b, c, h) (c, d) (g)

Fig. 9-24 Merger Diagrams

© 2002 Prentice Hall, Inc.

M. Morris Mano
DIGITAL DESIGN, 3e.
 a

b b,c
b

c d,e e

d b,c a,d

e b,c c
d
a b c d

(a) Implication table (b) Merger diagram

Compatibles (a, b) (a, d) (b, c) (c, d, e)

Implied states (b, c) (b, c) (d, e) (a, d,)

(b, c,)

(c) Closure table

Fig. 9-25 Choosing a Set of Compatibles
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
 x1 x2
a
00 b
01
00 01 11 10

a a b c a

b a b b c

c a c c c c
11

(a) Flow table (b) Transition diagram

Fig. 9-26 Three-Row Flow-Table Example

© 2002 Prentice Hall, Inc.

M. Morris Mano
DIGITAL DESIGN, 3e.
 x 1x 2
00 01 11 10

a a b d a a = 00 b = 01

b a b b c

c d c c c

d a – c – d = 10 c = 11

(a) Flow table (b) Transition diagram

Fig. 9-27 Flow Table with an Extra Row

© 2002 Prentice Hall, Inc.

M. Morris Mano
DIGITAL DESIGN, 3e.
 x 1x 2
00 01 11 10

a = 00 00 01 10 00

b = 01 00 01 01 11

c = 11 10 11 11 11

d = 10 00 – 11 –

Fig. 9-28 Transition Table

© 2002 Prentice Hall, Inc.

M. Morris Mano
DIGITAL DESIGN, 3e.
 00 01 11 10

a b a d a a b

b b d b a

c c a b c

d c d d c d c

(a) Flow table (b) Transition diagram

Fig. 9-29 Four-Row Flow-Table Example

© 2002 Prentice Hall, Inc.

M. Morris Mano
DIGITAL DESIGN, 3e.
 a =000 b =001
y1 y2

00 01 11 10 e =100
y3
g =010
0 a b c g

1 e d f d =101 f =111 c = 011

(a) Binary assignment (b) Transition diagram

Fig. 9-30 Choosing Extra Rows for the Flow Table

© 2002 Prentice Hall, Inc.

M. Morris Mano
DIGITAL DESIGN, 3e.
 00 01 11 10

000 = a b a e a

001 = b b d b a

011 = c c g b c

010 = g – a – –

110 – – – – –

111 = f c – – c

101 = d f d d f

100 = e – – d –

Fig. 9-31 State Assignment to Modified Flow Table

© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
 00 01 11 10

000
a 1 b1 a1 d1 a1

111
a 2 b2 a2 d2 a2

001
b 1 b1 d2 b1 a1

110
b 2 b2 d1 b2 a2

y2 y3 011
c 1 c1 a2 b1 c1
00 01 11 10
y1
100
c 2 c2 a1 b2 c2
0 a1 b1 c1 d1

010
d 1 c1 d1 d1 c1
1 c2 d2 a2 b2

101
d 2 c2 d2 d2 c2
(a) Binary assignment
(b) Flow table

© 2002 Prentice Hall, Inc. Fig. 9-32 Multiple-Row Assignment

M. Morris Mano
DIGITAL DESIGN, 3e.
 x1
1 x1
1
1 1 0 1 0 1
x2 1 0 x2 1 0
1 1
3 Y 3 Y
0 1 0 1

2 0 1 2 1 0

x3
1 x3
1

(a) AND-OR circuit (b) NAND circuit

Fig. 9-33 Circuits with Hazards

© 2002 Prentice Hall, Inc.

M. Morris Mano
DIGITAL DESIGN, 3e.
 1 1 1

0 0 0

(a) Static 1-hazard (b) Static 0-hazard (c) Dynamic hazard

Fig. 9-34 Types of Hazards

© 2002 Prentice Hall, Inc.

M. Morris Mano
DIGITAL DESIGN, 3e.
 x2x3 x2x3
00 01 11 10 00 01 11 10
x1 x1
0 1 0 1

1 1 1 1 1 1 1 1

(a) Y ⫽ x1 x 2 ⫹ x⬘2 x 3 (b) Y ⫽ x1 x 2 ⫹ x⬘2 x 3 + x 1 x 3

Fig. 9-35 Maps Demonstrating a Hazard and its Removal

© 2002 Prentice Hall, Inc.

M. Morris Mano
DIGITAL DESIGN, 3e.
 x1
x2

Y
x3

Fig. 9-36 Hazard-Free Circuit

© 2002 Prentice Hall, Inc.

M. Morris Mano
DIGITAL DESIGN, 3e.
 x1
1

3 Y ⫽ x 1 x 2 ⫹ x⬘2 y
x2
2
y

(a) Logic diagram

x1 x2 x1 x2
00 01 11 10 00 01 11 10
y y
0 0 0 1 0 0 1

1 1 0 1 1 1 1 1 1

(b) Transition table (c) Map for Y

Fig. 9-37 Hazard in an Asynchronous Sequential Circuit

© 2002 Prentice Hall, Inc.

M. Morris Mano
DIGITAL DESIGN, 3e.
 A
B
S
Q
C
D

A⬘ Q⬘
C

(a)

A
B

Q
C
D

A' Q⬘
C

(b)

© 2002 Prentice Hall, Inc. Fig. 9-38 Latch Implementation

M. Morris Mano
DIGITAL DESIGN, 3e.
 TC
00 01 11 10

a – ,– f ,– a ,0 b ,–

b g ,– – ,– c ,– b ,1

c – ,– h ,– c ,1 d ,–

d e,– – ,– a ,– d ,0

e e ,0 f ,– – ,– d ,–

f e ,– f ,0 a ,– – ,–

g g ,1 h ,– – ,– b ,–

h g ,– h ,1 c ,– – ,–

Fig. 9-39 Primitive Flow Table

© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
 b a,c

c b,d

d b,d a,c

e e,g
b,d f,h
b,d

f e,g f,h
a,c a,c

f,h e,g e,g

g b,d b,d f,h

f,h d,e e,g

h f,h
a,c c,f

a b c d e f g

Fig. 9-40 Implication Table

© 2002 Prentice Hall, Inc.

M. Morris Mano
DIGITAL DESIGN, 3e.
 a

h b

g c

f d

Fig. 9-41 Merger Diagram

© 2002 Prentice Hall, Inc.

M. Morris Mano
DIGITAL DESIGN, 3e.
 TC TC
00 01 11 10 00 01 11 10

a, f e ,– f ,0 a ,0 b,– a d ,– a ,0 a ,0 b ,–

b, g, h g ,1 h ,1 c ,– b ,1 b b ,1 b ,1 c ,– b ,1

c, h g,1 h ,1 c ,1 d ,– c b,– c ,1 c ,1 d ,–

d, e, f e ,0 f ,0 a,– d ,0 d d ,0 d ,0 a,– d ,0

(a) (b)

Fig. 9-42 Reduced Flow Table

© 2002 Prentice Hall, Inc.

M. Morris Mano
DIGITAL DESIGN, 3e.
 a
00 b
01

d
10 c
11

Fig. 9-43 Transition Diagram

© 2002 Prentice Hall, Inc.

M. Morris Mano
DIGITAL DESIGN, 3e.
 TC TC
00 01 11 10 00 01 11 10
y1 y2 y1 y2
a
00 10 00 00 01 00 0 0 0 X

b
01 01 01 11 01 01 1 1 1 1

c
11 01 11 11 10 11 1 1 1 X

d
10 10 10 00 10 10 0 0 0 0

(a) Transition table (b) Output map Q
y 2

Fig. 9-44 Transition Table and Output Map

© 2002 Prentice Hall, Inc.

M. Morris Mano
DIGITAL DESIGN, 3e.
 TC TC
y 1y 2 00 01 11 10 y 1y 2 00 01 11 10

00 1 0 0 0 00 0 X X X

01 0 0 1 0 01 X X 0 X

11 0 X X X 11 1 0 0 0

10 X X 0 X 10 0 0 1 0

(a) S1
y2 TC  y2 TC (b) R1
y2 TC  y2 TC

TC TC
y 1y 2 00 01 11 10 y 1y 2 00 01 11 10

00 0 0 0 1 00 X X X 0

01 X X X X 01 0 0 0 0

11 X X X 0 11 0 0 0 1

10 0 0 0 0 10 X X X X

© 2002 Prentice Hall, Inc. (c) S2
y1 TC (d) R2
y1 TC

M. Morris Mano Fig. 9-45 Maps for Latch Inputs
DIGITAL DESIGN, 3e.
 T

Y1

Y' 1

Q
Y2

Y' 2

© 2002 Prentice Hall, Inc.

M. Morris Mano
DIGITAL DESIGN, 3e. Fig. 9-46 Logic Diagram of Negative-Edge-Triggered T Flip-Flop
 x1

Y1

x2

Y2

Fig. P9-2

© 2002 Prentice Hall, Inc.

M. Morris Mano
DIGITAL DESIGN, 3e.
 x 1x 2
00 01 11 10

a a ,0 b ,– c ,– a ,1

b a ,– b ,0 b ,0 c,–

c a ,– b ,– c ,1 c ,0

Fig. P9-5

© 2002 Prentice Hall, Inc.

M. Morris Mano
DIGITAL DESIGN, 3e.
 x 1x 2
00 01 11 10
y1y2
00 10 00 11 10

01 01 00 10 10

11 01 00 11 11

10 11 00 10 10

Fig. P9-6

© 2002 Prentice Hall, Inc.

M. Morris Mano
DIGITAL DESIGN, 3e.
 x1
Y2
Y1 Q

x2

Fig. P9-9

© 2002 Prentice Hall, Inc.

M. Morris Mano
DIGITAL DESIGN, 3e.
 00 01 11 10

a a ,0 a ,1 b ,– a ,1

b a ,– b ,0 b ,0 b ,0

Fig. P9-14

© 2002 Prentice Hall, Inc.

M. Morris Mano
DIGITAL DESIGN, 3e.
 00 01 11 10 00 01 11 10

a a ,0 b ,– – ,– d ,– a a ,0 b ,– b ,– a ,0

b a ,– b ,1 b ,1 c,– b a ,– b ,0 b ,1 c,–

c b ,– – ,– b ,– c ,0 c b ,– d ,– c ,1 c ,1

d c,– d ,1 c ,– d ,1 d d ,0 d ,1 c ,– a,–

(a) (b)

Fig. P9-15

© 2002 Prentice Hall, Inc.

M. Morris Mano
DIGITAL DESIGN, 3e.
 00 01 11 10

a a ,1 f , – – ,– e ,–
00 01 11 10

a a ,0 b , – – ,– e ,– b c ,– – ,– j ,– b ,0

b a ,– b ,0 c ,– – ,– c c ,0 d , – – ,– b ,–

c – ,– d ,– c ,0 h , – d c ,– d ,0 g ,– – ,–

d a ,– d ,1 – ,– – ,– e a ,– – ,– g ,– e ,1

e a ,– – ,– f ,– e ,0 f a ,– f ,1 g ,– – ,–

f – ,– g ,– f ,0 h , – g – ,– d ,– g ,0 k ,–

g a ,– g ,0 – , – – ,– h h ,0 d , – – ,– k ,–

h a ,– – ,– – ,– h ,0 j – ,– f ,– j ,1 b ,–

(a) k a ,– – ,– j ,1 k ,0

(b)
© 2002 Prentice Hall, Inc.
M. Morris Mano Fig. P9-18
DIGITAL DESIGN, 3e.
 x1x2
00 01 11 10

a a ,0 a ,1 b ,– d ,–

b a ,– b ,0 b ,0 c,–

c a ,– – ,– d ,– c ,0

d a,– a ,– d ,1 d ,1

Fig. P9-19

© 2002 Prentice Hall, Inc.

M. Morris Mano
DIGITAL DESIGN, 3e.
 00 01 11 10

a a d a c

b a b b d

c d c b c

d d d e d

e f c e c

f f b a f

Fig. P9-20

© 2002 Prentice Hall, Inc.

M. Morris Mano
DIGITAL DESIGN, 3e.
 00 01 11 10

a a c a d

b a b c b

c c c c d

d d b a d

Fig. P9-21

© 2002 Prentice Hall, Inc.

M. Morris Mano
DIGITAL DESIGN, 3e.