ĐẠI HỌC QUỐC GIA TP.

HỒ CHÍ MINH
TRƯỜNG ĐẠI HỌC BÁCH KHOA
KHOA KHOA HỌC VÀ KỸ THUẬT MÁY TÍNH

EXPERIMENT 3
Digital System
Group: 03

Member:
Name ID
Lê Minh Gia Bảo 2052396
Quách Gia Bảo 2452141
Nguyễn Hoài Phong 2452960
Thoại Hào 2452305
EXERCISES:
1.Exercise 2.3.1
Design, simulate and implement a D Flip-flop using J-K Flip-flops
(allowed to use other logic gates if necessary)
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Truth Table for D Flip-flop

D CLK Q

0 PGT/NGT 0

1 PGT/NGT 1

SET RESET CLK D Q

0 0 Don’t Care Don’t Care Unstable (Q = Q’ = 1)

1 0 Don’t Care Don’t Care 1

0 1 Don’t Care Don’t Care 0

1 1 PGT/NGT D D
(else: no change)

Truth Table for clocked JK Flip-flop(s)

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J K CLK Q

0 0 PGT/NGT Q0 (no change)

1 0 PGT/NGT 1

0 1 PGT/NGT 0

1 1 PGT/NGT [Q0]’ (toggles)

Reset J K CLK Q

0 Don’t Care Don’t Care Don’t Care 0

1 0 0 PGT/NGT No change

1 1 0 PGT/NGT 1

1 0 1 PGT/NGT 0

1 1 1 PGT/NGT Toggle

Now we design the D Flip-flop using JK Flip-flop.

We use K-map method for easy designing:
- When D = 1, the JK should set the output.
- When D = 0, the JK should reset the output.

D Q0 J K Q

0 0 0 x 0

0 1 x 1 0

1 0 1 x 1

1 1 x 0 1

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K-map method:
For J:

D/Q0 0 1

0 0 x

1 1 x

=> J = D
For K:

D/Q0 0 1

0 x 1

1 x 0

=> K = D’
So it should look like this:

Using IC 7473 (Negative Edge Trigger):

Reset CLK D Q Q0

0 X X 0 1

1 NGT 1 1 0

1 NGT 0 0 1

1 0 X No change

1 1 X No change

1 PGT X No change

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 Netlist:

Start End

5V (IC 7473):4 , (IC 7404):14

GND (IC 7473):11 , (IC 7404):7

FREQ, BUT1 or BUT2 (CLK) (IC 7473):1

SW1 (CLR) (IC 7473):2

SW0 (D) (IC 7473):14 , (IC 7404):13

(IC 7404):12 (IC 7473):3

(IC 7473):12 LED 1 (Q)

(IC 7473):13 LED 1 (Q’)

2.Exercise 2.3.2:
Design, simulate and implement the following logic circuit.

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a. Assume that QA, QB, QC are connected to the LEDs. What is the
phenomenon of the LEDs? What is the difference among LEDs?
b. How many minimum D Flip-flops required to build a circuit in which
the output frequency is 16 times less than the Clock In frequency?
------------------
We got: QA connect to LEDA, QB connect to LEDB, QC connect to LEDC

U1 U2

Netlist:

5
Start End

5V U1:14, U2:14

GND U1:7, U2:7

FREQ, BUT1 or BUT2 (CLK) U1:3

U1:6 LED1 (LED A), U1:2

U1:5 U1:11

U1:8 LED2 (LED B), U1:12

U1:9 U2:3

U2:6 LED3 (LED C), U2:2

U2:5 Wire

Timing diagram:

(I forgor to draw the timing diagram for QA, QB and QC)

In the circuit, the output is the inverted Q, Q’.
Question A:
This circuit can be known as the counter which counts from 0 to 7,
where QC is the MSB and QA is the LSB.
Lighting pattern in a cycle:

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 CLK 1 2 3 4 5 6 7 8
(*)

QA 0 1 0 1 0 1 0 1

QB 0 0 1 1 0 0 1 1

QC 0 0 0 0 1 1 1 1

(CLK(*) is the current cycle of CLK in 1 cycle of the timing diagram

and CLK is PGT)
After CLK finishes the 8th cycle, it returns to the 1st cycle of new circuit
cycle.
Whenever QA, QB, QC is 1, its LED is turned on.
*We can say:
+ The LEDs are turned on asynchronously, with the pattern follows the
table above
+ The Frequency (Numbers of Cycles under 1 second) of LED A is
the biggest, then B and then C: fA > fB > Fc.

Question B:
finput = foutput x 2N (with N is the number of D Flip-flops)
+ In the circuit above:
foutput = fC = fin / 23 = 1/8 x finput.
+ When frequency of output is 16 less than the input CLK frequency:
2N = 16 = 24 => N = 4.
So the minimum D Flip-flops required is 4.

3.Exercise 2.3.3:
Given the circuit and waveform as follows.

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a. Design and simulate the circuit in Logisim.
b. Complete the timing diagram for A, B, and z based on the given
waveform.
--------------------
a. Logisim circuit:

b. Find A = Q(D flipflop), B = Q(JK flipflop) and z in the given timing

diagram.
The timing diagram looks like it’s NGT.
Truth table for D Flip-flop (Falling Edge Trigger)

SET’ RESET’ CLK D Q Q’

1 1 X X INVALID

1 0 X X 1 0

0 1 X X 0 1

0 0 NGT 0 0 1

0 0 NGT 1 1 0

0 0 ELSE X NO CHANGE

Truth table for JK Flip-flop (Falling Edge Trigger)

SET RESET’ CLK J K Q Q’

1 1 X X X Invalid

1 0 X X X 1 0

0 1 X X X 0 1

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0 0 NGT 0 0 NO CHANGE

0 0 NGT 0 1 0 1

0 0 NGT 1 0 1 0

0 0 NGT 1 1 TOGGLE

0 0 ELSE X X NO CHANGE

Timing Diagram:

We’re sorry because the timing diagram is a little hard to read.