Lab 4

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ĐẠI HỌC QUỐC GIA TP.

HỒ CHÍ MINH
TRƯỜNG ĐẠI HỌC BÁCH KHOA
KHOA KHOA HỌC VÀ KỸ THUẬT MÁY TÍNH

EXPERIMENT 4
DIGITAL SYSTEMS

Group: 03

Members:
Name ID
Thoại Hào 2452305
Quách Gia Bảo 2452141
Nguyễn Hoài Phong 2452960
Lê Minh Gia Bảo 2052396

2024
Exercise 2.3.1: Design and simulate a Full Adder built
from Half Adders in Logisim

Truth table:
Input Output

Cin A B Sum Carry

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

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Exercise 2.3.2: Design, simulate and implement a 4-
bit Ripple Carry Adder using IC 7483

Design of a 4-bit Ripple Carry Adder:

*IC 74283 is also 4-bit binary full adder

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Input 1 Input 2

5V Red line of breadboard (5V)

GND KTN Green line of breadboard (5V)

Red line of breadboard (5V) 5 of U1

Green line of breadboard (5V) 12 of U1

SW0 (B0) 11 of U1

SW4 (A0) 10 of U1

SW1 (B1) 7 of U1

SW5 (A1) 8 of U1

SW2 (B2) 4 of U1

SW6 (A2) 3 of U1

SW3 (B3) 16 of U1

SW7 (A3) 1 of U1

LED0 (S0) 9 of U1

LED1 (S1) 6 of U1

LED2 (S2) 2 of U1

LED3 (S3) 15 of U1

LED4 (OUT) 14 of U1

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Exercise 2.3.3: Design, simulate and implement a MOD-10
Asynchronous UP Counter using J-K Flip Flops (IC 7473)
- Table of changes in bit values:

D C B A Z Status
(CLR)

0 0 0 0 1 0

0 0 0 1 1 1

0 0 1 0 1 2

0 0 1 1 1 3

0 1 0 0 1 4

0 1 0 1 1 5

0 1 1 0 1 6

0 1 1 1 1 7

1 0 0 0 1 8

1 0 0 1 1 9

1 0 1 0 0 Return to 0

1 0 1 1 x Optional

1 1 0 0 x Optional

1 1 0 1 x Optional

1 1 1 0 x Optional

1 1 1 1 x Optional

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K-map:

DC/BA 00 01 11 10

00 1 1 1 1

01 1 1 1 1

11 X=1 X=1 X=0 X=0

10 1 1 X=0 0

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Excerises 2.3.4: What is the difference between asynchronous and
synchronous counter?
Synchronous:
- We use a universal clock that is common to all flip flops through out the
circuit.
- Synchronous Counter is faster in operation
- Does not produce any decoding errors
- Called Parallel Counter
- Will operate in any desired count sequence
- Propagation delay is less

Asynchronous:
- Main clock is only applied to the first flip flop, the rest of flip flops the
output of previous flip flop is taken as a clock
- Is slower
- Produces decoding error
- Called Serial Counter
- Will operate only in fixed count sequence (UP/DOWN)
- High propagation delay

Exercise 2.3.5: What is the procedure to design a synchronous


counter?
- We find the number of flip flops required for the design
of a synchronous counter.
- The number of flip flops can be determined from 2^n ≥
N.
- (Where: N →number of states and n →number of flip
flops)
- Next select the flip flop for the design.
- Then we draw the state diagram of that counter.
- With the help of an excitation table of flip flops we
determine the excitation table of the counter.
- At last we simplify the excitation table using K-map.

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