Lab 4
Lab 4
Lab 4
HỒ CHÍ MINH
TRƯỜNG ĐẠI HỌC BÁCH KHOA
KHOA KHOA HỌC VÀ KỸ THUẬT MÁY TÍNH
EXPERIMENT 4
DIGITAL SYSTEMS
Group: 03
Members:
Name ID
Thoại Hào 2452305
Quách Gia Bảo 2452141
Nguyễn Hoài Phong 2452960
Lê Minh Gia Bảo 2052396
2024
Exercise 2.3.1: Design and simulate a Full Adder built
from Half Adders in Logisim
Truth table:
Input Output
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
1
Exercise 2.3.2: Design, simulate and implement a 4-
bit Ripple Carry Adder using IC 7483
2
Input 1 Input 2
SW0 (B0) 11 of U1
SW4 (A0) 10 of U1
SW1 (B1) 7 of U1
SW5 (A1) 8 of U1
SW2 (B2) 4 of U1
SW6 (A2) 3 of U1
SW3 (B3) 16 of U1
SW7 (A3) 1 of U1
LED0 (S0) 9 of U1
LED1 (S1) 6 of U1
LED2 (S2) 2 of U1
LED3 (S3) 15 of U1
LED4 (OUT) 14 of U1
3
Exercise 2.3.3: Design, simulate and implement a MOD-10
Asynchronous UP Counter using J-K Flip Flops (IC 7473)
- Table of changes in bit values:
D C B A Z Status
(CLR)
0 0 0 0 1 0
0 0 0 1 1 1
0 0 1 0 1 2
0 0 1 1 1 3
0 1 0 0 1 4
0 1 0 1 1 5
0 1 1 0 1 6
0 1 1 1 1 7
1 0 0 0 1 8
1 0 0 1 1 9
1 0 1 0 0 Return to 0
1 0 1 1 x Optional
1 1 0 0 x Optional
1 1 0 1 x Optional
1 1 1 0 x Optional
1 1 1 1 x Optional
4
K-map:
DC/BA 00 01 11 10
00 1 1 1 1
01 1 1 1 1
10 1 1 X=0 0
5
Excerises 2.3.4: What is the difference between asynchronous and
synchronous counter?
Synchronous:
- We use a universal clock that is common to all flip flops through out the
circuit.
- Synchronous Counter is faster in operation
- Does not produce any decoding errors
- Called Parallel Counter
- Will operate in any desired count sequence
- Propagation delay is less
Asynchronous:
- Main clock is only applied to the first flip flop, the rest of flip flops the
output of previous flip flop is taken as a clock
- Is slower
- Produces decoding error
- Called Serial Counter
- Will operate only in fixed count sequence (UP/DOWN)
- High propagation delay