University of Technology

Department of Electrical Engineering

Microprocessor Engineering
Third Class

8086 Microprocessor

Assist. Prof. Dr. Hadeel Nasrat

Abdullah
The main features of 8086 µp are:
 It is a 16-bit Microprocessor (μp). It’s ALU, internal registers works with 16bit
binary word.
 8086 has a 20 bit address bus can access up to 220= 1 MB memory locations.
 8086 has a 16bit data bus. It can read or write data to a memory/port either 16bits
or 8 bit at a time.
 It can support up to 64K I/O ports.
 It provides 14, 16 -bit registers.
 Frequency range of 8086 is 6-10 MHz
 It has multiplexed address and data bus AD0- AD15 and A16 – A19.
 It requires single phase clock with 33% duty cycle to provide internal timing.
 It can prefetch up to 6 instruction bytes from memory and queues them in order to
speed up instruction execution.
 It requires +5V power supply.
 A 40 pin dual in line package.
8086 is designed to operate in two modes, Minimum mode and Maximum mode.
The minimum mode is selected by applying logic 1 to the MN / input pin.
This is a single microprocessor configuration.
The maximum mode is selected by applying logic 0 to the MN / input pin.
This is a multi-microprocessors configuration.
Lecture 2: 8086 Microprocessor
Assist. Prof. Dr. Hadeel N. Abdullah 2
 Architecture or Functional Block
Diagram of 8086
The microarchitecture of a
processor is its internal
architecture-that is, the circuit
building blocks that implement the
software and hardware
architectures of the 8086
microprocessors. The
microarchitecture of the 8086
processing units. Figure (2-
microprocessors
1) employs
shows parallel
the
internal architecture
processing-that is, theytheare8086
of microprocessors.
implemented with conta
several
two
processing
They units: the
simultaneously B usinInterface
operating
Fig. (2.1): Internal architecture
Unit (BID) and the Execution Unit of the 8086
(EU).Assist. Prof. Dr. Hadeel N. Abdullah microprocessor. 3
 BUS INTERFACE
 UNIT:
It provides a full 16 bit bidirectional data bus and 20 bit address
bus.

The bus interface unit connects the microprocessor to
external devices. BIU performs following operations:
 Instruction fetching
 Reading and writing data of data operands for memory
 Inputting/outputting data for input/output peripherals.
 And other functions related to instruction and data acquisition.

To implement above functions, the BIU contains the segment
registers, the instruction pointer, address generation
adder, bus control logic, and an instruction queue.

The BIU uses a mechanism known as an instruction stream
queue to implement
pipeline architecture.
Lecture 2: 8086 Microprocessor
Assist. Prof. Dr. Hadeel N. Abdullah 4
 EXECUTION
UNIT is for decoding executing

The
responsible and
Execution all

unit
The EU consists of arithmetic logic unit (ALU), status and
instructions.
control flags, general-purpose registers, and temporary-
operand registers.

The EU extracts instructions from the top of the queue
in the BIU, decodes them, generates operands if
necessary, passes them to the BIU and requests it to
perform the read or write by cycles to memory or I/O and
perform the operation specified by the instruction on the
operands.
Assist. Prof. Dr. Hadeel N. Abdullah

During the execution of the instruction, the EU tests the5
Software Model of the 8086
Microprocessor
As a programmer of the 8086 you must become familiar
with the various registers in the EU and BIU. The 8086
microprocessor has a total of fourteen registers that are
accessible to the programmer. It is divided into four
groups. They are:

 Four General purpose

registers
 Four Index/Pointer
registers
 Four
Segment
registers.
 Lecture
Two 2: 8086register
other Microprocessor
Assist. Prof. Dr. Hadeel N. Abdullah 6
General Purpose
Registers:
•AX - the accumulator register (divided into AH / AL):
oGenerates shortest
machine code o
Arithmetic, logic and data
transfer o One number
must be in AL or AX o
Multiplication & Division
o Input & Output
•BX - the base address register (divided into BH / BL).
•CX - the count register (divided into CH / CL):
o Iterative code segments using the LOOP Instruction
o Repetitive operations on strings with the REP command
o Count (in CL) of bits to shift and rotate
•DX - the data register (divided into DH / DL):
Lecture 2: 8086 Microprocessor
o Hadeel
Assist. Prof. Dr. DX:AX concatenated
N. Abdullah into 32-bit register for some MUL 7
Index or Pointer Registers
•SI - source index register:
o Can be used for pointer addressing of data
o Used as source in some string processing
instructions
o Offset address relative to DS
o
•DI - destination index register:
o Can be used for pointer addressing of data
o Used as destination in some string
processing instructions
o Offset address relative to ES
o
•BP - base pointer:
o Primarily used to access parameters
passed via the stack
o Offset address relative to SS
o
•SP - stack pointer:
o Always points to top item on the stack
o Offset address relative to SS
Lecture 2: 8086o Microprocessor
Always points to word (byte at even
Assist. Prof. Dr. Hadeel N. Abdullah 8
 Segment Registers

Most of the registers contain data/instruction offsets within 64

KB memory segment. There are four different 64 KB segments for
instructions, stack, data and extra data. To specify where in 1 MB of
processor memory these 4 segments are located the processor uses four
segment registers.
 Code segment (CS) - points at the segment containing the current
program.
 Data segment (DS) - generally points at segment where variables
are defined.
 Extra segment (ES) - extra segment register, it's up to a coder to
define its usage.
 Stack segment (SS) - points at the segment containing the stack.

Code segment (CS) is a 16-bit register containing address of 64

Lecture 2: 8086 Microprocessor
KB
Assist.segment
Prof. Dr. Hadeel with processor
N. Abdullah instructions. The processor uses9 CS
 Segment
Registers
Stack segment (SS) is a 16-bit register containing address of 64KB
segment with program stack. By default, the processor assumes that all
data referenced by the stack pointer (SP) and base pointer (BP) registers is
located in the stack segment. SS register can be changed directly using POP
instruction.
Data segment (DS) is a 16-bit register containing address of 64KB
segment with program data. By default, the processor assumes that all data
referenced by general registers (AX, BX, CX, DX) and index register (SI, DI) is
located in the data segment. DS register can be changed directly using POP
and LDS instructions.
Extra segment (ES) used to hold the starting address of Extra
segment. Extra segment is provided for programs that need to access a
second data
Lecture 2: 8086 segment. Segment registers cannot be used in arithmetic
Microprocessor
Assist. Prof. Dr. Hadeel N. Abdullah 10
 Other Registers of 8086
Instruction Pointer (IP) is a 16-bit register. This is a crucially
important register which is used to control which instruction the CPU
executes. The ip, or program counter, is used to store the memory
location of the next instruction to be executed. The CPU checks the
program counter to ascertain which instruction to carry out next. It
then updates the program counter to point to the next instruction.
Thus the program counter will always point to the next instruction to
be executed.
Flag Register determines the current state of the processor.
They are modified automatically by CPU after mathematical
operations, this allows to determine the type of the result, and to
determine conditions to transfer control to other parts of the
program. 8086 has 9 flags and they are divided into two categories:
Lecture 2: 8086 Microprocessor
Assist. Prof. Dr. Hadeel N. Abdullah 11
1 . Status Flags
Flag Register of 8086

Lecture 2: 8086 Microprocessor

Assist. Prof. Dr. Hadeel N. Abdullah 12
 Status Flags
Status Flags represent result of last arithmetic or
logical instruction executed.
Conditional
 Carry Flag flags are as follows:
This flag indicates an overflow condition for
(CF): It is alsounsigned
arithmet integer
used in multiple-precision
 ic.
Auxiliary Flag arithmetic.
(AF): If an operation performed in ALU generates a
carry/barrow from lower nibble (i.e. D0 D3) to upper nibble (i.e. D4 –
D7), the AF flag is set i.e. carry given by D3 bit to D4 is AF flag. This
is not a general-purpose flag, it is used internally by the processor to
perform Binary to BCD conversion.
 Parity Flag (PF): This flag is used to indicate the parity of result. If
lower order 8-bits of the result contains even number of 1‟s, the
Parity Flag is set and for odd number of 1‟s, the Parity Flag is reset.
 Zero Flag (ZF): It is set; if the result of arithmetic or logical operation
is zero else it is reset.
 Sign Flag (SF): In sign magnitude format the sign of number is
indicated by MSB bit. If the result of operation is negative, sign flag is
set.
 Overflow Flag (OF): It occurs when signed numbers are added or
subtracted.
Lecture 2: An OF indicates that the result has exceeded the
8086 Microprocessor
Assist. Prof. Dr. Hadeel N. Abdullah 13
 Control Flags
1. Trap Flag (TP):
 It is used for single step control.
 It allows user to execute one instruction of a program at a time
for debugging.
 When trap flag is set, program can be run in single step mode.
2. Interrupt Flag (IF):
 It is an interrupt enable/disable flag.
 If it is set, the maskable interrupt of 8086 is enabled and
if it is reset, the interrupt is disabled.
 It can be set by executing instruction sit and can be
cleared by executing CLI instruction.
3. Direction Flag (DF):
 It is used in string operation.
 If it is set, string bytes are accessed from higher memory
address to lower memory address.
 When it is reset, the string bytes are accessed from lower
memory address to higher memory address.
Lecture 2: 8086 Microprocessor
Assist. Prof. Dr. Hadeel N. Abdullah 14
 Memory Segmentation
The total memory size is divided into segments
of various sizes.
A segment is just an area in memory.
The process of dividing memory this way is
called Segmentation.
In memory, data is stored as bytes.
Each byte has a specific address.
Intel 8086 has 20 lines address bus.
With 20 address lines, the memory that can
be addressed is 220bytes = 1,048,576 bytes
(1 MB).
Lecture 2: 8086 Microprocessor

8086 can access memory with address ranging

Assist. Prof. Dr. Hadeel N. Abdullah 15
 8086 Memory Segmentation
In 8086, memory has four different types of
segments. These are:
1 . Code Segment
2 . Data Segment
3 . Stack Segment
4 . Extra Segment
Each of these segments are
addressed by an address stored in
corresponding
 Ea registersegment register.
stores the base address
 These
c (starting address)
registers are 16-bit inofsize. the
corresponding segment.
h
 Because the segment registers cannot store 20 bits,
they only store the upper 16 bits.
Lecture 2: 8086 Microprocessor
Assist. Prof. Dr. Hadeel N. Abdullah 16
 Physical Address Generation
 How is a 20-bit address obtained if there are only 16
bit registers?
 The 20-bit address of a byte is called its Physical Address.
 But, it is specified as a Logical Address.
 Logical address is in the form of:
Base Address : Offset
 To calculate the effective address of the memory, BIU uses
the following formula:
Effective Address = Starting Address of Segment + Offset
 To find the starting address of the segment, BIU appends
the contents of Segment Register with 0H.
 Then, it adds offset to it.
Lecture 2: 8086 Microprocessor
Assist. Prof. Dr. Hadeel N. Abdullah 17
 Physical Address
Generation
Logical Address is specified as
segment: offset

 Physical address is obtained by shifting the segment

address 4 bits to the left and adding the offset
address.


 Thus the physical address of the

logical address A4FB:4872
is:
A4FB0 + 4872 = A9822
Lecture 2: 8086 Microprocessor
Assist. Prof. Dr. Hadeel N. Abdullah 18
 Where to Look for the Offset

Question
The contents of the following registers are:
CS = 1111 H, DS = 3333 H ,
SS = 2526 H , IP = 1232 H ,
SP = 1100 H , DI = 0020 H
Calculate the corresponding physical addresses for the address
bytes in CS, DS and SS.

Lecture 2: 8086 Microprocessor

Assist. Prof. Dr. Hadeel N. Abdullah
19
 Solution
1. CS = 1111 H
The base address of the code segment is 11110 H.

Effective address of memory is given by 11110H +

1232H = 12342H. 2. DS = 3333 H


 The base address of the data segment is 33330
H.
Effective address of memory is given by 33330H +

0020H = 33350H. 3. SS = 2526 H


 The base address of the stack segment is
25260 H.
 Effective address of memory is given by
Lecture 2: 8086 Microprocessor
25260H
Assist. Prof. Dr. Hadeel N. Abdullah + 1100H = 26350H. 20
Review
Questions
What is segmentation? What are its

advantages? How is segmentation

implemented in typical
microprocessors?

Lecture 2: 8086 Microprocessor

Assist. Prof. Dr. Hadeel N. Abdullah 21
 Homew
ork
The contents of the following registers are:
CS = 1234 H
DS = 3122 H
□ SS = 26A1 H
IP = 1002 H
SP = 1552 H
DI = 0130 H
Calculate the corresponding physical addresses for the address
bytes in CS, DS and SS.

Lecture 2: 8086 Microprocessor

Assist. Prof. Dr. Hadeel N. Abdullah 22