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Lecture TEN DATA TRANSFER USING I/O STRUCTURE

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 University of Technology
Department of Electrical Engineering
Microprocessor Engineering
Third Class

Lecture TEN
DATA TRANSFER USING I/O
STRUCTURE

Assist. Prof. D. Hadeel Nasrat Abdullah

 DATA TRANSFER USING I/O STRUCTURE
There are three major types of data transfer between the microprocessor and I/O device.
 Programmed I/O: In programmed I/O the data transfer is accomplished through an I/O port
and controlled by software.
 Interrupt driven I/O : In interrupt driven I/O, the I/O device will interrupt the processor, and
initiate data transfer.
 Direct memory access
(DMA) : In DMA, the data
transfer between
memory and I/O can be
performed by bypassing
the microprocessor.

Lecture 10: Data Transfer using I/O Structure 2

/ Assist. Prof. Dr. Hadeel N. Abdullah
 8255 – Programmable Peripheral Interface (PPI)
 It is an I/O port chip used for interfacing I/O devices with microprocessor.
 The 8255 is a popular interfacing component, that can interface any TTL-compatible I/O device
to a microprocessor.
 It is used to interface to the keyboard and a parallel printer port in PCs.
 PPI consisting of 3 numbers of 8 –bit parallel I/O ports (PORT A, PORT B, PORT C).
 Port C composed of two independent 4-bit ports - PCUpper (PC7-PC4) and PCLower (PC3-PC0).
 These 3 port programmed to function either as an input port or as an output port in different
operating modes.
 PPI operates in mainly two modes.
(1) Bit Set Reset Mode (BSRMode).
(2) I/O Mode

Lecture 10: Data Transfer using I/O Structure /

3
Assist. Prof. Dr. Hadeel N. Abdullah
 8255 PPI Pin Configuration

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Lecture 10: Data Transfer using I/O Structure / Assist. Prof. Dr. Hadeel N. Abdullah
 Function of Pins
 RD (read): this signal enables the read operation. When the signal is low , microprocessor
reads data from a selected I/O port of 8255.
 WR (write): this control signal enables the write operation.
 RESET: It clears the control registers and sets all ports in input mode.
 CS , A0,A1: these are device select signals connected to a decoded address and A0,A1 are
connected to A0,A1 of microprocessor.

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Lecture 10: Data Transfer using I/O Structure / Assist. Prof. Dr. Hadeel N. Abdullah
 Operating Modes Of 8255

There are two main operational modes of 8255:

1. Bit set/Reset (BSR) mode:

The BSR mode is used to set or rest the bits in port C.

2. Input / Output mode: classified into three types

 Mode 0: Simple Input or Output

 Mode 1: Input or Output with Handshake

 Mode 2: port A can be set up for Bidirectional Data Transfer using handshake
signals from port C, and port B can be set up either in mode0 or mode 1.

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Lecture 10: Data Transfer using I/O Structure / Assist. Prof. Dr. Hadeel N. Abdullah
 Control Word Register
1. Bit set/Reset (BSR) mode

2. Input / Output mode:

Lecture 10: Data Transfer using I/O Structure /

Assist. Prof. Dr. Hadeel N. Abdullah 7
 Examples
Example 1: What is the mode and I/O configuration for ports A, B, C of an 82C55 after its control register is loaded
with 82
Solution:
Expressing the control register contents in binary form, we get:

D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 0 0 0 1 0

; port C lower is an output

; port B is an input
; port A is an output port

; then Group A (port A and port C upper) is in mode 0

; then mode set flag is active

Example 2: Write down 82C55 control word that set Port A and Port Cupper as input in mode 1, and set Port Clower
and Port B as output in mode 0.
D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 1 0 0 1 1

Then the control word contain 93H

Lecture 10: Data Transfer using I/O Structure /
Assist. Prof. Dr. Hadeel N. Abdullah 8
 Examples
Example 3: What is the mode and I/O configuration for ports A, B, C of an 82C55 after its control register is loaded
with 65H.
Solution:
D7 D6 D5 D4 D3 D2 D1 D0

0 1 1 0 0 1 0 1

1. Since it is BSR mode, D7 = '0'.

2. PC2 has to be selected, hence, D3 = 0, D2 = 1, D1 = 0.
3. PC2 has to be set, hence, D0 = 1

Example 4: What is the mode and I/O configuration for ports A, B, C of an 82C55 after its control register is loaded
with 72H.
Solution: D7 D6 D5 D4 D3 D2 D1 D0

0 1 1 1 0 0 1 0

1. Since it is BSR mode, D7 = '0'.

2. PC1 has to be selected, hence, D3 = 0, D2 = 0, D1 = 1.
3. PC1 has to be Reset, hence, D0 = 0.

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Lecture 10: Data Transfer using I/O Structure / Assist. Prof. Dr. Hadeel N. Abdullah
Keyboard/Display Interfaces to 82C55A

To communication with peripherals

through the 8255, three steps are
necessary:

Determine the addresses of ports A, B

and C and of the control register
according to the Chip Select logic and
the address lines A0 and A1.

1. Write a control word in the control

register.

2. Write I/O instructions to

communicate with the peripherals
through ports A, B and C.

10
Example 5: In 8086's 8-bit isolated I/O system, an 82C55 PPI is connected so that the address of A, B, C ports, and
Control register are 4D08H, 4D09H, 4D0AH and 4D0BH respectively.
a) Draw the circuit diagram.
b) Write program to set Register A, B as input and Register C as output (all in mode0). Then continuously receive two
unsigned number from Registers A and B, compare them and output the larger to Register C.
The program
MOV AL, 92H
MOV DX, 4D0BH
OUT DX, AL
again: MOV DL, 08H (because DH is the same)
IN AL,DX
MOV BL, AL
INC DL
IN AL, DX
CMP AL, BL
JNC no_exchange
MOV AL, BL
no_exchange: INC DL
OUT DX, AL
MOV CX, FFFFH
delayloop: DEC CX D7 D6 D5 D4 D3 D2 D1 D0
JNZ delayloop 1 0 0 1 0 0 1 1
11
JMP again
 Direct Memory Access (DMA)
 A direct memory access (DMA) is an operation in which data is copied (transported) from one resource to
another resource in a computer system without the involvement of the CPU.
 The task of a DMA-controller (DMAC) is to execute the copy operation of data from one resource location to
another. The copy of data can be performed from:
 I/O-device to memory
 memory to I/O-device
 memory to memory
 I/O-device to I/O-device

Computer System with DMA

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Lecture 10: Data Transfer using I/O Structure / Assist. Prof. Dr. Hadeel N. Abdullah
Basic DMA Operation
 The direct memory access (DMA) I/O technique provides direct access to the memory
while the microprocessor is temporarily disabled.
 A DMA controller temporarily borrows the address bus, data bus, and control bus from
the microprocessor and transfers the data bytes directly between an I/O port and a
series of memory locations.
 The DMA transfer is also used to do high-speed memory-to memory transfers.
 Two control signals are used to request and acknowledge a DMA transfer in the
microprocessor-based system.
 The HOLD signal is a bus request signal which asks the microprocessor to release
control of the buses after the current bus cycle.
 The HLDA signal is a bus grant signal which indicates that the microprocessor has
indeed released control of its buses by placing the buses at their high-impedance
states.
 The HOLD input has a higher priority than the INTR or NMI interrupt inputs.
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Lecture 10: Data Transfer using I/O Structure / Assist. Prof. Dr. Hadeel N. Abdullah
 The 8237 DMA CONTROLLER
 A DMA read causes the and signals to activate simultaneously.
 A DMA write causes the and signals to both activate.
 8086 require a controller or circuit such as shown in figure below for control bus signal
generation
 The DMA controller provides memory with its address, and controller signal ( ) selects the
I/O device during the transfer.
 The 8237 DMA controller supplies the memory
and I/O with control signals and memory
address information during the DMA transfer.
 The 8237 is capable of DMA transfers at rates of
up to 1.6M bytes per second.
 Each channel is capable of addressing a full
64K-byte section of memory and can transfer up
to 64K bytes with a single programming.
Lecture 10: Data Transfer using I/O Structure / Assist. Prof. Dr. Hadeel N. Abdullah 14
SOME IMPORTANT SIGNAL PINS of 8237 DMA Controller
 DREQ3 – DREQ0 (DMA request): Used to request a DMA transfer for a
particular DMA channel.
 DACK3 – DACK0 (DMA channel acknowledge): Acknowledges a channel DMA
request from a device.
 HRQ (Hold request): Requests a DMA transfer.
 HLDA (Hold acknowledge) signals the 8237 that the microprocessor has
relinquished control of the address, data and control buses.
 MEMW (Memory write): Used as an output to cause memory to write data during
a DMA write cycle.
 MEMR (Memory read): Used as an output to cause memory to read data during a
DMA read cycle
 A3 – A0: address pins select an internal register during programming and provide
part of the DMA transfer address during DMA operation.
 A7 – A4: address pins are outputs that provide part of the DMA transfer address during a DMA
operation.
 DB0 – DB7: data bus, connected to microprocessor and are used during the programming DMA
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controller.
DMA Transfer Modes
1. BURST mode
 Sometimes called Block Transfer Mode.
 An entire block of data is transferred in one contiguous sequence. Once the DMA controller is
granted access to the system buses by the CPU, it transfers all bytes of data in the data block
before releasing control of the system buses back to the CPU.
2. CYCLE STEALING Mode
 Viable alternative for systems in which the CPU should not be disabled for the length of time
needed for Burst transfer modes.
3. TRANSPARENT Mode
 This requires the most time to transfer a block of data, yet it is also the most efficient in terms of
overall system performance
Advantages of DMA
 Computer system performance is improved by direct transfer of data between memory and I/O
devices, bypassing the CPU.
 CPU is free to perform operations that do not use system buses.
Disadvantages of DMA
 In case of Burst Mode data transfer, the CPU is rendered inactive for relatively long periods of time.

Lecture 10: Data Transfer using I/O Structure / Assist. Prof. Dr. Hadeel N. Abdullah 16
 8086 Interrupt
 An interrupt is used to cause a temporary halt in the execution of program.
 The meaning of ‘interrupts’ is to break the sequence of operation.
 While the Microprocessor is executing a program, an ‘interrupt’ breaks the normal sequence of
execution of instructions, diverts its execution to some other program called Interrupt Service
Routine (ISR).
 After executing ISR, IRET returns the control back again to the main program. Interrupt
processing is an alternative to polling.

Types of Interrupts
The following figure shows
the types of interrupts we have in
an 8086 microprocessor:

Lecture 10: Data Transfer using I/O Structure / Assist. Prof. Dr. Hadeel N. Abdullah 17
 Sources of Interrupt
An 8086 interrupt can come from any one of the following three sources:
1) An external signal applied to the non-maskable interrupt (NMI 17 pin) pin or to the interrupt
(INTR 18 pin) pin. An interrupt caused by a signal applied to one of these inputs is called
hardware interrupt.
2) The execution of the Interrupt instruction (INT n), where n is the interrupt type that can take
any value between 00H and FFH. This is called software interrupt.
3) Interrupt raised due to some error condition produced in 8086 instruction execution
process. (Divide by zero, overflow errors etc)

Lecture 10: Data Transfer using I/O Structure / Assist. Prof. Dr. Hadeel N. Abdullah 18
8086 Interrupt Processing
If an interrupt has been requested, the 8086 Microprocessor processes it by performing the
following series of steps:
1. Pushes the content of the flag register onto the stack to preserve the status of the interrupt (IF)
and trap flags (TF), by decrementing the stack pointer (SP) by 2
2. Disables the INTR interrupt by clearing IF in the flag register
3. Resets TF in the flag register, to disable the single step or trap interrupt
4. Pushes the content of the code segment (CS) register onto the stack by decrementing SP by 2
5. Pushes the content of the instruction pointer (IP) onto the stack by decrementing SP by 2
6. Performs an indirect far jump to the start of the interrupt service routine (ISR) corresponding to
the received interrupt.

Lecture 10: Data Transfer using I/O Structure / Assist.

Prof. Dr. Hadeel N. Abdullah 19
 Hardware Interrupts
 Hardware interrupt is caused by any peripheral
device by sending a signal through a specified
pin to the microprocessor.

 The primary sources of interrupts, however, are

the PCs timer chip, keyboard, serial ports,
parallel ports, disk drives, CMOS real-time clock,
mouse, sound cards, and other peripheral
devices. These devices connect to an Intel
8259A programmable interrupt controller (PIC)
that prioritizes the interrupts and interfaces with
the 8086 CPU.

Lecture 10: Data Transfer using I/O Structure / Assist. Prof. Dr. Hadeel N. Abdullah 20
Non-Maskable Interrupt (NMI)
There are some interrupts which cannot be masked out or ignored by the processor. These are
associated with highpriority tasks which cannot be ignored (like memory parity or bus faults). In general, most
processors support the Non-Maskable Interrupt (NMI). This interrupt has absolute priority, and when it
occurs, the processor will finish thecurrent memory cycle, then branch to a special routine written to handle
the interrupt request.

INTR
The INTR is a maskable interrupt because the microprocessor will be interrupted only if interrupts are
enabled using set interrupt flag instruction. It should not be enabled using clear interrupt Flag instruction.

The INTR interrupt is activated by an I/O port. If the interrupt is enabled and NMI is disabled, then the
microprocessor first completes the current execution and sends ‘0’ on INTA pin twice. The first ‘0’ means
INTA informs the external device to get ready and during the second ‘0’ the microprocessor receives the 8 bit,
say X, from the programmable interrupt controller.
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Software Interrupts
Some instructions are inserted at the desired position into the program to create interrupts.
These interrupt instructions can be used to test the working of various interrupt handlers. It
includes:

INT- Interrupt instruction with type

number
 It is 2-byte instruction. First byte provides the op-
code and the second byte provides the interrupt
type number. There are 256 interrupt types under
this group.
 The interrupt vector table contains 256 four byte
entries, contain the CS:IP
 Interrupt vectors for each of the 256 possible
interrupts. The table is used to locate the
interrupt service routine addresses for each of
those interrupts.
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