COMPUTER ORGANIZATION

Dr.Mamatha I
Associate Professor & Head
SMVITM, Bantakal

Declaration: Most of the slides are borrowed from the slides prepared by,
Dr.M. C. Hanumantharaju
Professor,Department of Electronics and Communication Engineering 1
BMS Institute of Technology and Management, Bengaluru
MODULE 3
▪ Basic Structure of Computers: Functional Units, Basic Operational Concepts, Bus

structure, Performance –Processor Clock, Basic Performance Equation, Clock Rate,

Performance Measurement.

▪ Machine Instructions and Programs: Memory Location and Addresses, Memory

Operations, Instruction and Instruction sequencing, Addressing Modes.

▪ Text book 2: 1.2, 1.3, 1.4, 1.6, 2.2, 2.3, 2.4, 2.5

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A TYPICAL INSTRUCTION
▪ Add LOCA, R0

▪ Add the operand at memory location LOCA to the operand in a register R0 in the processor.

▪ R0 = R0 + [LOCA]

▪ Assume that the instruction is stored in memory location 1000, the value of R0 is 10 and LOCA is 2000.
LOCA (i.e2000) is transferred to MAR, PC ← 1000, MAR ← PC

▪ READ Signal is issued to memory unit

▪ Instruction is fetched to MDR

▪ Contents of MDR is transferred to IR

▪ The instruction is decoded by control unit, Operand at LOCA is fetched to MDR.

▪ The content of MDR is added to R0 and place the sum into register R0.

▪ The original contents of LOCA are preserved.

▪ The original contents of R0 is overwritten. PC is incremented to point to next instruction

▪ For execution of this instruction two memory read operation is done.

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EXECUTION OF ADD R0, R1
▪ R1 = R1 + R0

▪ Assume that the instruction is stored in memory location 1000, the value of R0 is 10 and R1 is 20

▪ PC ← 1000

▪ MAR ← PC

▪ READ Signal is issued to memory unit

▪ Instruction is fetched to MDR

▪ Contents of MDR is transferred to IR

▪ PC is incremented to point to next instruction

▪ The instruction is decoded by control unit

▪ R1 and R0 is added and result is placed in R1

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SEPARATE MEMORY ACCESS AND ALU

▪ Load LOCA, R1
▪ Add R1, R0
▪ Whose contents will be overwritten?

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TYPICAL OPERATING STEPS

▪ Get operands for ALU

▪ General-purpose register

▪ Memory(address to MAR–Read–MDR to ALU)

▪ Perform operation in ALU

▪ Store the result back

▪ To general-purpose register

▪ To memory(address to MAR, result to MDR–Write)

▪ During the execution, PC is incremented to the next instruction

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INTERRUPT

▪ Normal execution of programs may be pre-empted if some device requires urgent

servicing.

▪ The normal execution of the current program must be interrupted–the device raises an

interrupt signal.

▪ Interrupt-service routine

▪ Current system information back up and restore (PC, general-purpose registers,

control information, specific information)

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BUS STRUCTURE

▪ The different functional modules must be connected in an organized manner to form an

operational system.

▪ Bus refers a group of lines that serve as a connecting path for several devices

▪ Address/data/control

▪ The simplest way to connect the functional unit is to use the single bus architecture

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BUS STRUCTURE
Single bus structure

▪ Single-bus : Bus can be used only for one transfer at a time, only two units can actively
use the bus at any given time.

▪ Low cost and flexible to attach peripheral devices.

▪ Multiple buses are used for better performance because parallelism in data transfer is
allowed

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SPEED ISSUE

▪ Different devices have different transfer/operate speed.

▪ If the speed of bus is bounded by the slowest device connected to it, the efficiency will be
very low.

▪ How to solve this?

▪ A common approach –use buffers.

▪ The Buffer Register when connected with the bus, carries the information during transfer.

▪ The Buffer Register prevents the high speed processor from being locked to a slow I/O device

during a sequence of data transfer

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PERFORMANCE
▪ The most important measure of a computer is how quickly it can execute programs.

▪ Three factors affect performance:

▪ Hardware design

▪ Instruction set

▪ Compiler

▪ Processor time to execute a program depends on the hardware involved in the

execution of individual machine instructions.

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PERFORMANCE
▪ The processor and a relatively small cache memory can be fabricated on a single

integrated circuit chip.

▪ Speed

▪ Cost

▪ Memory management

▪ Processor Clock

▪ Clock, clock cycle (P), and clock rate (R=1/P)

▪ The execution of each instruction is divided in to several steps (Basic Steps),each of which

completes in one clock cycle.

▪ Hertz –cycles per second

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BASIC PERFORMANCE EQUATION
▪ T–processor time required to execute a program that has been prepared in high-level
language

▪ N number of actual machine language instructions needed to complete the execution

(note: loop)

▪ S–average number of basic steps needed to execute one machine instruction. Each step
completes in one clock cycle

▪ R–clock rate

▪ Note: these are not independent to each other

▪ How to improve T?

▪ Reduce N and S, Increase R, but these affect one another

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PIPELINE AND SUPERSCALAR OPERATION
▪ Instructions are not necessarily executed one after another.

▪ The value of S doesn’t have to be the number of clock cycles to execute one

instruction.

▪ Pipelining–overlapping the execution of successive instructions.

▪ Add R1, R2, R3 at the same time processor reads next instruction in memory.

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PIPELINE AND SUPERSCALAR OPERATION

▪ Superscalar operation–multiple instruction pipelines are implemented in the

processor.

▪ Goal–reduce S(could become<1!)

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CLOCK RATE
▪ Increase clock rate

▪ Improve the integrated-circuit(IC) technology to make the circuits faster.

▪ Reduce the amount of processing done in one basic step (however, this may increase the

number of basic steps needed)

▪ Increases in R that are entirely caused by improvements in IC technology affect all

aspects of the processor’s operation equally except the time to access the main
memory.

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CISC AND RISC
▪ Trade off between N and S

▪ A key consideration is the use of pipelining

▪ S is close to 1 even though the number of basic steps per instruction may be considerably

larger

▪ It is much easier to implement efficient pipelining in processor with simple

instruction sets

▪ Reduced Instruction Set Computers (RISC)(Large value N, Small Value of S)

▪ Complex Instruction Set Computers (CISC) (Small value N, Large Value of S)

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CISC AND RISC

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COMPILER
▪ A compiler translates a high-level language program into a sequence of machine

instructions.

▪ To reduce N, we need a suitable machine instruction set and a compiler that makes

good use of it.

▪ Goal–reduce N×S

▪ A compiler may not be designed for a specific processor; however, a high-quality

compiler is usually designed for, and with, a specific processor

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PERFORMANCE MEASUREMENT
▪ Is difficult to compute.
▪ Measure computer performance using benchmark programs.
▪ System Performance Evaluation Corporation(SPEC) selects and publishes representative
application programs for different application domains, together with test results for many
commercially available computers.
▪ Compile and run (no simulation)
▪ Reference computer

▪ N is the number of program in the suite

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MULTIPROCESSOR AND MULTICOMPUTERS
▪ Multiprocessor computer

▪ Execute a number of different application tasks in parallel

▪ Execute subtasks of a single large task in parallel

▪ All processors have access to all of the memory–shared-memory multiprocessor

▪ Cost–processors, memory units, complex interconnection networks

▪ Multicomputers

▪ Each computer only have access to its own memory

▪ Exchange message via a communication network–message-passing multicomputers

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 MACHINE
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INSTRUCTIONS
AND PROGRAMS
OBJECTIVES

▪ Machine instructions and program execution, including branching and subroutine

call and return operations.

▪ Addressing methods for accessing register and memory operands.

▪ Assembly language for representing machine instructions, data, and programs.

▪ Program-controlled Input/Output operations.

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MEMORY LOCATIONS, ADDRESSES, AND
OPERATIONS
▪ Memory consists of many millions of storage cells, each of which can store1bit.
▪ Data is usually accessed in n-bit groups. n is called word length.

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CONTINUED..

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CONTINUED..

▪ To retrieve information from memory, either for one word or one byte (8-bit),

addresses for each location are needed.

▪ A k-bit address memory has 2k memory locations, namely 0 –(2k-1), called memory

space.

▪ 24-bit memory: 224= 16,777, 216 = 16M (1M=220)

▪ 32-bit memory: 232= 4G (1G=230)

▪ 1K(kilo)=210

▪ 1T(tera)=240

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CONTINUED..

▪ It is impractical to assign distinct addresses to individual bit locations in the

memory.

▪ The most practical assignment is to have successive addresses refer to successive

byte locations in the memory–byte-addressable memory.

▪ Byte locations have addresses 0,1,2,…If word length is 32bits,then successive words are

located at addresses 0,4,8,…

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BIG ENDIAN AND LITTLE ENDIAN ASSIGNMENTS
▪ Big-Endian: lower byte addresses are used for the most significant bytes of the word

▪ Little-Endian: opposite ordering. lower byte addresses are used for the less significant

bytes of the word

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MEMORY LOCATION, ADDRESSES, AND OPERATION
▪ Address ordering of bytes: Byte addressing

▪ Word alignment

▪ Words are said to be aligned in memory if they begin at a byte addr. that is a multiple of the

num of bytes in a word.

▪ 16-bitword:word addresses:0,2,4,….

▪ 32-bitword:word addresses:0,4,8,….

▪ 64-bitword:word addresses:0,8,16,….

▪ Access numbers, characters, and character strings

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MEMORY OPERATION

▪ Load (or Read or Fetch)

▪ Copy the content. The memory content doesn’t change.

▪ Address –Load

▪ Registers can be used

▪ Store (or Write)

▪ Overwrite the content in memory

▪ Address and Data –Store

▪ Registers can be used

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 INSTRUCTION
31
AND
INSTRUCTION
SEQUENCING
MUST PERFORM OPERATIONS

▪ A computer must have instructions capable of performing 4 types of operation

▪ Data transfers between the memory and the processor registers

▪ Arithmetic and logic operations on data

▪ Program sequencing and control

▪ I/O transfers

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REGISTER TRANSFER NOTATION

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REGISTER TRANSFER NOTATION

▪ Identify a location by a symbolic name standing for its hardware binary address

(LOC,R0,…)

▪ Contents of a location are denoted by placing square brackets around the name of the

location (R1←[LOC],R3←[R1]+[R2])

▪ Register Transfer Notation(RTN)

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ASSEMBLY LANGUAGE NOTATION

▪ Notation to represent machine instructions and programs.

▪ Move LOC, R1 => R1←[LOC] : Instruction that causes the transfer from memory location LOC to

processor register R1

▪ Add R1, R2, R3 => R3 ←[R1]+[R2] : Adding two numbers contained in processor registers R1

and R2 and placing their sum in R3

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BASIC INSTRUCTION TYPES

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CPU ORGANIZATION

▪ Single Accumulator

▪ Result usually goes to the Accumulator

▪ Accumulator has to be saved to memory quite often

▪ General Register

▪ Registers hold operands thus reduce memory traffic

▪ Register bookkeeping

▪ Stack

▪ Operands and result are always in the stack

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INSTRUCTION FORMATS
▪ Three-Address Instructions

▪ ADD R2, R3, R1 R1 ← [R2] + [R]

▪ Two-Address Instructions

▪ ADD R2, R1 R1 ← [R1] + [R2]

▪ One-Address Instructions

▪ ADD M AC ← [AC] + M[AR]

▪ Zero-Address Instructions

▪ ADD TOS ← [TOS] + [TOS –1]

▪ RISC Instructions

▪ Lots of registers. Memory is restricted to Load & Store

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INSTRUCTION FORMATS
▪ Example: Evaluate (A+B) * (C+D)

▪ Three-Address

▪ 1.ADD A, B, R1 ; R1 ← M[A] + M[B]

▪ 2.ADD C, D, R2; R2 ← M[C] + M[D]

▪ 3.MUL R1, R2, X; M[X] ← [R1] * [R2]

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INSTRUCTION FORMATS
▪ Example: Evaluate (A+B) * (C+D)

▪ One-Address

▪ 1.LOAD A; AC ← M[A]

▪ 2.ADD B; AC ← [AC] + M[B]

▪ 3.STORE T; M[T] ← [AC]

▪ 4.LOAD C; AC ← M[C]

▪ 5.ADD D; AC ← [AC] + M[D]

▪ 6.MUL T; AC ← [AC] * M[T]

▪ 7.STORE X; M[X] ← [AC]

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INSTRUCTION FORMATS
▪ Example: Evaluate (A+B) * (C+D)

▪ Zero-Address

▪ 1.PUSH A; TOS ← [A]

▪ 2.PUSH B ; TOS ← [B]

▪ 3.ADD; TOS ← [A + B]

▪ 4.PUSH C; TOS ← [C]

▪ 5.PUSH D; TOS ← [D]

▪ 6.ADD; TOS ← [C + D]

▪ 7.MUL; TOS ← [C+D]*[A+B]

▪ 8.POP X; M[X] ← [TOS]

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INSTRUCTION FORMATS
▪ Example: Evaluate (A+B) * (C+D)

▪ RISC

▪ 1.LOAD A, R1 ; R1 ← M[A]

▪ 2.LOAD B, R2 ; R2 ← M[B]

▪ 3.LOAD C, R3 ; R3 ← M[C]

▪ 4.LOAD D, R4 ; R4 ← M[D]

▪ 5.ADD R1, R2, R1; R1 ← [R1] + [R2]

▪ 6.ADD R3, R4, R3; R3 ← [R3] + [R4]

▪ 7.MUL R1, R3, R1; R1 ← [R1] * [R3]

▪ 8.STORE X, R1; M[X] ← [R1]

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USING REGISTERS

▪ Registers are faster

▪ Shorter instructions

▪ The number of registers is smaller(e.g.32 registers need 5 bits)

▪ Potential speedup

▪ Minimize the frequency with which data is moved back and forth between the

memory and processor registers.

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USING REGISTERS
▪ Using accumulator (single address)

▪ Using one processor registers for operands

▪ Using two processor registers for operands

▪ Using three processor registers for operands

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DATA TRANSFER INSTRUCTION
▪ Move instruction

equivalent to

▪ Store instruction

▪ In a processor if arithmetic operations are allowed only with the processor registers

then, to perform C=A+B , following instructions are used.

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CONTINUED..
▪ One operand in memory other in register

▪ Speed depend on the speed of the data transfers

▪ Fetching data from memory is slower than that of fetching from registers
▪ No.of memory read and write to be reduced to improve the speed

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INSTRUCTION EXECUTION AND STRAIGHT-LINE
SEQUENCING
▪ Assumptions:
-One memory operand per instruction
-Has many processor registers
-32-bit word length
-Memory is byte addressable
▪ The three instructions of the program are
in successive word locations, starting at
location i. Since each instruction is 4
bytes long, the second, third, and fourth
instructions are at addresses i + 4, i + 8,
▪ Full memory address can be directly
specified in a single-word instruction
▪ Two-phase procedure
▪ -Instruction fetch
▪ -Instruction execute
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STRAIGHT LINE SEQUENCING
▪ The processor contains a register called the program counter (PC), which holds the address of

the next instruction to be executed.

▪ To begin executing a program, the address of its first instruction (i in our example) must be

placed into the PC.

▪ Then, the processor control circuits use the information in the PC to fetch and execute

instructions, one at a time, in the order of increasing addresses.

▪ This is called straight-line sequencing.

▪ During the execution of each instruction, the PC is incremented by 4 to point to the next

instruction. Thus, after the Move instruction at location i + 8 is executed, the PC contains the
value i + 12, which is the address of the first instruction of the next program segment.

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STRAIGHT LINE SEQUENCING
▪ Executing a given instruction is a two-phase procedure.
▪ In the first phase, called instruction fetch, the instruction is fetched from the memory location
whose address is in the PC.
▪ This instruction is placed in the instruction register (IR) in the processor.
▪ At the start of the second phase, called instruction execute, the instruction in IR is examined to
determine which operation is to be performed.
▪ The specified operation is then performed by the processor.
▪ This involves a small number of steps such as fetching operands from the memory or from
processor registers, performing an arithmetic or logic operation, and storing the result in the
destination location.
▪ At some point during this two-phase procedure, the contents of the PC are advanced to point to
the next instruction.
▪ When the execute phase of an instruction is completed, the PC contains the address of the next
instruction, and a new instruction fetch phase can begin.
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BRANCHING

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BRANCHING
▪ Assume that the number of entries in
the list, n, is stored in memory location
N, as shown.
▪ Register R1 is used as a counter to
determine the number of times the
loop is executed.
▪ Hence, the contents of location N are
loaded into register R1 at the
beginning of the program.
▪ Then, within the body of the loop, the
instruction Decrement R1is executed,
reduces the contents of R1 by 1 each
time through the loop.

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CONTINUED..
▪ Execution of the loop is repeated as long as the contents of R1
are greater than zero.
Branch instructions.
▪ This type of instruction loads a new address into the program
counter.
▪ As a result, the processor fetches and executes the instruction at
this new address, called the branch target, instead of the
instruction at the location that follows the branch instruction
in sequential address order.
▪ A conditional branch instruction causes a branch only if a
specified condition is satisfied.
▪ If the condition is not satisfied, the PC is incremented in the
normal way, and the next instruction in sequential address
order is fetched and executed.
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CONTINUED..
▪ Branch>0 LOOP is a conditional branch instruction that causes a branch to location

LOOP if the contents of register R1 are greater than zero.

▪ This means that the loop is repeated as long as there are entries in the list that are

yet to be added to R0.

▪ At the end of the nth pass through the loop, the Decrement instruction produces a

value of zero in R1, and, hence, branching does not occur. Instead, the Move
instruction is fetched and executed.
▪ It moves the final result from R0 into memory location SUM.

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CONDITION CODES
▪ Processor keeps track of information about the results of various operations for use by
subsequent conditional branch instructions
▪ Accomplished by recording the required information in individual bits, called condition code
flags
▪ Flags grouped together in a special purpose register called condition code register or status
register.
▪ Individual condition code flags are set to 1 or cleared to 0 depending on the outcome of the
operation
▪ Condition code flags (bits)

▪ Condition code register / status register

▪ N (negative)
▪ Z (zero)
▪ V (overflow)
▪ C (carry)
▪ Different instructions affect different flags
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CONDITION CODES

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CONDITIONAL BRANCH INSTRUCTIONS

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STATUS BITS

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62
ADDRESSING
MODES
GENERATING MEMORY ADDRESSESS

▪ How to specify the address of branch target?

▪ Can we give the memory operand address directly in a single Add instruction in the

loop?

▪ Use a register to hold the address of NUM1; then increment by 4 on each pass through

the loop.

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ADDRESSING MODES
▪ The different ways in which the location of an operand is specified in an instruction are

referred to as addressing modes.

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EFFECTIVE ADDRESSES

▪ In the addressing modes that follow, the instruction does not give the operand or its

address explicitly. Instead, it provides information from which an effective address(EA)

can be derived by the processor when the instruction is executed.

▪ The effective address is then used to access the operand.

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ADDRESSING MODES
▪ Implied
▪ AC is implied in “ADD M[AR]” in “One-Address” instr.
▪ TOS is implied in “ADD” in “Zero-Address” instr.

▪ Immediate
▪ The use of a constant in “MOV 5, R1”
▪ or “MOV #5, R1”i.e. R1 ← 5

▪ MOV #NUM1, R2 ; to copy the variable memory address

▪ Register
▪ Indicate which register holds the operand

▪ Direct Address
▪ Use the given address to access a memory location
▪ E.g. Move NUM1, R1
Move R0, SUM

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INDIRECT ADDRESSING

▪ Indirection and Pointer

▪ Indirect addressing through a general purpose register.

▪ Indicate the register(e.g.R1)that holds the address of the

variable(e.g.B) that holds the operand

▪ ADD (R1), R0

▪ The register or memory location that contain the address of

an operand is called a pointer

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INDIRECT ADDRESSING
▪ Indirect addressing through a memory addressing.

▪ Indicate the memory variable(e.g.A) that holds the address of the variable(e.g.B) that holds

the operand

▪ ADD(A),R0

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INDIRECT ADDRESSING EXAMPLE

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EXAMPLE

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EXAMPLE

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EXAMPLE

72
EXAMPLE

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EXAMPLE

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EXAMPLE

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ADDRESSING MODES-INDEXING AND ARRAYS

▪ Indexing and Array

▪ The EA of the operand is generated by adding a constant value to the contents of a

register.

▪ X(Ri); EA=X+(Ri) X=Signed number

▪ X defined as offset or displacement

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INDEXING AND ARRAYS

▪ Index mode –the effective address of the operand is generated by adding a constant

value to the contents of a register.

▪ Index register

▪ X(Ri): EA = X + [Ri]

▪ The constant X may be given either as an explicit number or as a symbolic name

representing a numerical value.

▪ If X is shorter than a word, sign-extension is needed.

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INDEXING AND ARRAYS

▪ In general, the Index mode facilitates access to an operand whose location is defined

relative to a reference point within the data structure in which the operand appears.

▪ 2D Array

▪ (Ri, Rj) so EA = [Ri] + [Rj]

▪ Rj is called the base register

▪ 3D Array

▪ X(Ri, Rj) so EA = X + [Ri] + [Rj]

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ADDRESSING MODES-INDEXING AND ARRAYS

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ADDRESSING MODES –INDEXING AND ARRAYS
▪ Array
▪ E.g. List of students marks

▪ Indexed addressing used in accessing test marks from the list

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ADDRESSING MODES
▪ Base Register

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ADDRESSING MODES-INDEXING AND ARRAYS

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ADDRESSING MODES
▪ Indexed

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ADDRESSING MODES-RELATIVE ADDRESSING

▪ Relative mode– the effective address is determined by the Index mode using the

program counter in place of the general-purpose register.

▪ X(PC)–note that X is a signed number

▪ Branch>0 LOOP

▪ This location is computed by specifying it as an offset from the current value of PC.

▪ Branch target may be either before or after the branch instruction, the offset is given as

a singed num.

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RELATIVE ADDRESSING
▪ Relative address

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ADDITIONAL ADDRESSING MODES
▪ Auto increment mode –the effective address of the operand is the contents of a

register specified in the instruction. After accessing the operand, the contents of this
register are automatically incremented to point to the next item in a list.

▪ (Ri)+. The increment is 1 for byte-sized operands, 2 for 16-bit operands, and 4 for 32-bit

operands.

▪ Auto decrement mode: -(Ri) –decrement first

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Thank You

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