Investigation Report on FINFET Technology

XU ZIXIN1*
1
School of Electrical and Electronic Engineering, Nanyang Technological University, 50 Nanyang
Avenue, 639798, Singapore
[email protected]
1. Introduction
In the past two decades, silicon integrated circuits have developed rapidly, especially in
recent years where deep sub-micron CMOS technology has evolved to substrates as large as
12 inch silicon wafers and device feature sizes as small as 0 At the level of 13 microns, we
are advancing towards the technology level of sub-100 nanometers However, the research
results indicate that under the traditional planar MOSFET platform, this development trend
will face insurmountable technical obstacles in the sub-50 nanometer stage. Non-conventional
CMOS devices at the nanometer level, especially dual gate or multi gate electrode devices,
are one of the key solutions to overcome the above difficulties and maintain the effectiveness
of Moore's Law in the next decade So far, various new structures of dual gate or multi gate
electrode devices have been developed and studied, among which FinFET devices built on
SOI substrates are considered to be the most advantageous unconventional MOS device
structures This structure not only has excellent performance similar to ideal dual gate devices,
but also, more importantly, is compatible with traditional bulk silicon VLSI process flow and
has good practical prospects.

2. FinFET Technology
2.1 History of the FinET Technology
Since the 1960s, Moore's Law has predicted that the density of transistors on integrated
circuits will double every two years, driving the rapid development of semiconductor
technology. Early transistors were mostly based on planar design. As the size continued to
shrink, traditional planar transistors (such as CMOS) began to face problems such as short
channel effects, increased leakage current, and decreased performance. When the transistor
size is reduced to below 20nm, the current control capability of planar transistors decreases,
leakage current increases, and power consumption is difficult to further reduce. These issues
have prompted researchers to explore new three-dimensional transistor designs to maintain
performance and energy efficiency.
The concept of FinFET was first proposed by Professor Hu Zhengming and his team at the
University of California, Berkeley in 1999. When researching how to improve the current
control of transistors, they designed a transistor based on a three-dimensional structure, which
uses the protruding "fin like structure" on the silicon wafer as the channel of the transistor,
and surrounds the gate around the top and sides of the fin to enhance the ability to control the
current. The research of Hu Zhengming's team provides a theoretical basis and technical
framework for FinFET.
As semiconductor sizes shrink to 32nm and below, the performance of traditional planar
transistors declines, and the advantages of FinFET gradually become apparent. Intel 、 Major
semiconductor companies such as TSMC and Samsung have begun investing significant
resources in research to explore the commercialization of FinFET. In 2011, Intel launched the
22nm FinFET chip: The large-scale commercial application of FinFET began in 2011, when
Intel first introduced the 22nm FinFET process in its Ivy Bridge processor, marking the

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transition of FinFET from laboratory to practical production applications. Intel claims that its
22nm FinFET transistor has improved performance by 37% and reduced power consumption
by 50% compared to traditional planar transistors.
In 2014, TSMC and Samsung followed suit: TSMC and Samsung successively launched
16nm and 14nm FinFET processes in 2014, further promoting the popularity of FinFET in
global semiconductor manufacturing. These processes are widely used in mobile device
chips, and FinFET has become the mainstream technology.

2.2 Structural characteristics and craftsmanship

The bulk silicon FinFET structure is designed by directly combining the structural advantages
of the original SOI FinFET and planar groove devices on a bulk silicon substrate The
manufacturing process of this structure is also different from that of the original SOI FinFET.
Firstly, an isolation dielectric layer is deposited on the active region and grooves are etched
on it. Then, silicon islands are etched and etched in the lateral direction, followed by the
formation of a gate insulation layer and gate electrode. Finally, the source and drain regions
are prepared The structure of bulk silicon FinFET has the following characteristics:
(1) It is built on a regular bulk silicon substrate, and except for the fabrication process of the
dual gate stereo structure, the other process steps are completely consistent with conventional
deep sub-micron planar CMOS technology;
(2) Belonging to the side gate and side source drain types of ideal dual gate devices, it can
fully demonstrate the advantages of dual gate devices in suppressing SCE and DIBL effects;
(3) In addition to the dual gate structure of the original SOI FinFET, a planar groove
MOSFET is also connected in parallel in the channel direction, which not only fully utilizes
the active area and gate electrode area to provide more current channels, but also combines
the characteristics of both to effectively suppress SCE at the same time;
(4) It is a quasi-planar structure that can be easily fabricated into CMOS devices and circuits,
and can be easily applied to mainstream CMOS planar processes;

(5) Self aligning device structure, forming gate electrode and source drain through self-
alignment, therefore the actual isolation size from source drain to dual gate electrode is
smaller than the original SOI FinFET structure, which has greater efficiency in circuit
integration;
(6) The gate electrode is a sidewall limiting gate structure, which can make the actual gate
length smaller under the actual photolithography resolution, reducing the requirements for
photolithography technology;
(7) Parallel double-sided gate and slot gate structures can increase the saturation current of the
device in the same plane area, thus reducing the requirement for gate insulation layer
thickness;
(8) Relatively elevated source/drain regions are conducive to the formation of ultra shallow
junctions and silicide;
(9) Parallel gate structures are easily formed in the same trench, thereby increasing the
effective gate width;
(10) The channel is uniformly doped, with a passive drain extension region and Compared to
nanoscale planar devices, the requirements for channel engineering are greatly reduced in
terms of structure

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2.3 Advantages of Technology
Since the emergence of the IC industry, the desire to optimize design indicators such as
performance, power consumption, area, cost, and product launch time (opportunity cost) has
never changed.
The design based on FinFET has once again expanded the design window. The operating
voltage continues to decrease, and compared to traditional planar transistors, it has a
significant reduction in leakage current, which is crucial for reducing power consumption,
thereby significantly reducing dynamic and static power consumption. The short channel
effect is also significantly reduced. As the gate can surround the fin like structure from
multiple directions, FinFET can effectively reduce the short channel effect, thereby
improving the reliability of the transistor and reducing the protective band required to handle
variability. In addition, compared with planar FETs with the same process nodes, there is also
an improvement in performance. In fact, due to the excellent channel gate control
characteristics in FinFET, FinFET has faster switching speed at high frequencies and can
achieve higher performance. Compared with planar FET, FinFET has significant performance
advantages.
For memory designers, another advantage of FinFET is that compared to planar FET,
SRAM based on FinFET has much lower requirements for holding voltage.
From the perspective of the new unit power performance metric (Kpoomy's law), a major
design optimization advantage of FinFET compared to planar FET is that it can significantly
improve performance with the same power budget, or achieve the same performance with
much lower power budget. This advantage enables designers to achieve the highest
performance with the lowest power consumption, which is a significant optimization for
battery driven devices.

2.3 Application Market and Development Trends

2.3.1 High Performance Computing (HPC)
Data centers and servers: The increasing demand for high-performance computing and
cloud computing has led to constantly improving performance and energy efficiency
requirements for server chips. FinFET technology is used to manufacture the latest server
processors, such as AMD's EPYC and Intel's Xeon series. With the support of FinFET
technology, these processors can significantly reduce energy consumption while maintaining
high performance. For example, AMD's EPYC processors use 7nm FinFET technology and
are widely used in modern data centers, providing higher core count and computing power.
Supercomputers: FinFET process supported chips are widely used in supercomputer systems,
helping them improve efficiency and speed in high-performance computing tasks such as
scientific research, meteorological simulation, and gene analysis.
2.3.2 Automotive Electronics
Electric vehicles and advanced driver assistance systems (ADAS): The automotive
industry's demand for high-performance computing and low-power processors is constantly
increasing, especially in the fields of electric vehicles and autonomous driving. FinFET
technology chips are widely used in vehicle processors, sensor fusion processors, image
processing units, and communication modules. For example, Tesla and other electric vehicle
manufacturers use AI chips based on FinFET technology for real-time perception and
computing tasks. In car entertainment and information systems: More and more

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entertainment, navigation, and information systems in cars also require powerful computing
power and low power consumption. FinFET technology helps these systems improve
response speed while reducing energy consumption.
2.3.3 5G communication equipment
Base stations and network equipment: The processors of 5G base stations and
communication network core equipment rely on FinFET technology to address the challenges
of high data rates, low latency, and large-scale connections. FinFET technology provides
excellent performance and low power consumption in these devices.
Communication module and modem: The core components of 5G smartphones and
communication devices, such as Qualcomm's Snapdragon X series modems, use FinFET
technology to achieve faster network connections and higher efficiency. Example: 5G chips
from companies such as Huawei and Qualcomm use FinFET technology to support global 5G
network deployment.
3. Conclusion
FinFET device technology is the most promising device technology required to extend
Moore's Law to 5-nanometer processes from various perspectives. It is fully compatible with
CMOS on both bulk silicon and SOI. It provides a very good solution to the problems of sub
threshold leakage, poor short channel electrostatic behavior, and high variability of device
parameters that plague the expansion of planar CMOS to 20 nanometers. Moreover, FinFET
technology can operate at very low power supply voltages and expand the voltage regulation
range, compared to the past
It is difficult to lower the voltage in CMOS devices. It can further save static and dynamic
power consumption. In addition, FinFET technology is fully compatible with the CMOS
backend design process, so there is no need for new FinFET targeted development in this
field.
However, no new technology can completely avoid risks or challenges. FinFET devices
contain a large number of parasitic parameters that require precise modeling and thorough
consideration in all circuit layouts, especially in analog circuits. From the perspective of
circuit design, in addition to considering the influence of parasitic parameters more during the
layout stage, new circuit technologies are also needed in substrate bias and read/write to
replace the technologies that are very effective in planar FET but not very effective for
FinFET. In summary, FinFET technology brings a bright future for device miniaturization
and is an indispensable technology for designing high-performance, power sensitive
applications such as next-generation smartphones, enterprise computing, and networks. This
technology also brings new design challenges. As people's knowledge and experience in
FinFET based design continue to increase, these challenges will be effectively addressed,
ultimately ensuring successful design and unique end products.