Digital Systems

Tutorial 5
March 2024

Tutorial:
1. Questions are prepared by Hitesh. S. and Siddharth. K.

Note:
1. Assume both the normal and complement inputs are available.
2. Assume initial state to be 0 if not mentioned.
3. Use a D-flip flop whenever a specific type of flip-flop is not mentioned.

1. Draw the complete design including state diagram for the state table given below using D-flip
flop.

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2. Draw the complete design for the state diagram given below using D-flip flop. And write the
output sequence for the set of input sequences given below. What relation holds between the
input and output if we consider the input as 8-bit binary value? (Note:- The bit positioned
on the rightmost side is considered first. The state a is the initial state.)
– Input: 00101010, 11110000, 10111001

State Diagram

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3. The sequential circuit oscillates in any of the following cases based on the initial state as long
as the external input X = 0:
Case A 00 - 01 - 00 - 01
Case B 10 - 11 - 10 - 11

If the external input X = 1, if it is in Case (A) it switches to Case (B) and vice versa.While
switching cases 00 will go to 10 and vice versa and 01 will go to 11 and vice versa.
A. Draw the state Diagram.
B. Implement the circuit using two J-K flip flops and external gates.

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4. Draw the state diagram to output a ”1” for one cycle if the sequence ”1001” shows up for
following 2 cases using Moore machine. (Note:- MSB is most commonly refereed as the leading
entry)
A. The leading 1’s cannot be used in more than one sequence.
B. The leading 1’s can be used in more than one sequence.
C. Also mention the number of flip flops required to design such machine.

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5. Design a FSM to detect at least two 1’s in the last 3 samples. (Note:- The bit positioned on
the rightmost side is considered first. And the initial output is 0.)
For Example:-
Input 0 1 0 1 0 1 1 0 0 1
Output 0 1 0 1 1 1 0 0 0 0

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6. The block has one input “IN” which is coming serially and the other is clock “CLK”. It has
4 outputs A, B,C and D . A will be 1 if IN has even number of 1’s and even number of 0’s.
Similarly B will be 1 for even 1’s odd 0’s, C for odd 1’s even 0’s and D for both odd. (Note:-
The even and odd is the cumulative sum of 1’s and 0’s occurred)
A. Give the FSM required to design the block
B. Implement the circuit using D flip flops and external gates.

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7. For the circuit described by the state diagram

A. Determine the state transitions and output sequence that will be generated when an
input sequence of 010110111011110 is applied to the circuit and it is initially in the state
00. (Note:- The bit positioned on the leftmost side is considered first)
B. Find all of the equivalent states in Figure and draw a simpler, but equivalent, state
diagram.
C. Using D flip-flops, design the equivalent machine (including its logic diagram) described
by the state diagram in (B).

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8. You want to design a laser surgery system where a surgeon activates the laser by pressing a
button. The laser should then stay on for exactly 3 cycles, then turn off. Ignore input button
presses when the laser is ”on”.
A. Design FSM and make a state table for the problem described in the question.
B. Draw the circuit implementation using D Flip flop.

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9. The state diagram for a finite state machine with states S0 ,S1 ,S2 , S3 and binary input In is
shown in the figure.
A. Draw the state table and the circuit using D flip flops to implement this circuit.
B. Identify the type of machine and the purpose of FSM.
C. Make the state diagram for the same FSM with the other type of machine.

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10. Design an FSM-finite state machine which detects the alternate 0’s and 1’s in the previous
three samples. (Note:- The bit positioned on the leftmost side is considered first)

Input Sequence 0010101101000

Output Sequence 0001111001100

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11. An electronics engineer has designed an electronic lock with three buttons: ”reset”, ”0” and
”1”. He has provided the following state transition diagram showing how the lock responds
to a sequence of inputs.

A. After pressing the ”reset” button what is the length of the shortest sequence of button
presses that will open the lock?
B. After pressing the ”reset” button what is the length of the longest sequence of button
presses that will cause the lock to open after the last button in the sequence is pressed
but not open any earlier in the sequence?
C. After much use, the ”reset” button breaks. Is it still possible to open the lock using only
the ”0” and ”1” buttons assuming you know nothing about the lock’s state (except that
its locked!) when you start?
D. Suppose the engineer wanted to design a lock that required exactly 10 button presses to
open after pressing ”reset”. Not counting the ”reset” and ”unlock” states, what is the
minimum number of state his FSM would need need?

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 Practice Problems
1. Draw the state diagram to output a ”1” for one cycle if the sequence ”0110” shows up for
following 2 cases using Mealy machine. (Note:- MSB is most commonly refereed as the leading
entry)
A. The leading 0’s cannot be used in more than one sequence.
B. The leading 0’s can be used in more than one sequence.
C. Also mention the number of flip flops required to design such machine.

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2. For the following state table

A. Draw the corresponding state diagram.

B. Tabulate the reduced state table.
C. Draw the state diagram corresponding to the reduced state table.
D. Starting from state a, and the input sequence 01110010011, determine the output se-
quence for state table and the reduced state table. (Note:- The bit positioned on the
leftmost side is considered first)

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3. A sequential circuit has three flip-flops A, B, C; one input xin; and one output yout. The
state diagram is shown in figure. The circuit is to be designed by treating the unused states
as don’t-care conditions. Analyze the circuit obtained from the design to determine the effect
of the unused states.
A. Use D flip-flop in the design
B. Use JK flip-flop in the design

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4. The state transition diagram for a finite state machine with states A, B and C, and binary
inputs X, Y and Z, is shown in the figure. Draw the state table and find out the state in which
state ambiguous transitions are defined. (Note:- In the context of state diagrams, ambiguity
refers to a situation where the transition between states is not clearly defined or is unclear
for all the possible input combinations.)

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5. Draw the state diagram for a circuit that gives output as ’1’ if the aggregate serial binary
input is divisible by 5. (Note:- The bit positioned on the MSB side is considered first)
E.g. If the input stream is 1, 0, 1, we output a ’1’ (since 101 is 5). If we then get a ’0’, the
aggregate total is 10, so we output another ’1’. If we get a ’1’, the aggregate total is 21,
so we output a ’0’.

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6. Design an FSM- finite state machine to check whether the two inputs A and B have the
same value for the previous 4 samples. Use Mealy machine and Moore machine for the

design.

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