Tut 2 (ANS)
Tut 2 (ANS)
Tutorial 2
February 2024
Tutorial:
1. Questions 1 through 10 prepared by Shruthi. R.
2. Questions 11 through 20 prepared by Antonson J.
Note: Assume both the normal and complement inputs are available
With reference to the table above the cells under the dotted box’s can be combined to come-
up with following reduced equation.
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The Boolean expression
F = x′ y ′ (z + z ′ ) + xy(z + z ′ )
simplifies to
F = x′ y ′ + xy
.
(b) The K-map for 3 variables is plotted below:
Following plot will show grouping of adjacent cells to find a minimized logic value.
The two step minimization equation is shown below: The Boolean expression
simplifies to
F = (y ′ + x)
.
(c) 3 variable K– map is plotted below with 1 and 0 values assigned to cells.
2
The Boolean expression
F = x′ y ′ z ′ + x′ y ′ z + x′ yz + x′ yz ′ + xy ′ z ′ + xy ′ z + xyz + xyz ′
simplifies to
F =1
.
2. Using a 4-variable Karnaugh map (K-map), determine the minimal Sum of Products (SOP)
expressions for the given
P Boolean functions.
(a)F (A, B, C, D) = P m(0, 1, 3, 5, 7, 8, 9, 11, 13, 15)
(b)F (W, X, Y, Z) = m(1, 3, 4, 6, 9, 11, 12, 14).
Also,find the Essential Prime Implicants for each of the above given F .
Solution: Given that the Boolean expression involves four variables, we create a 4x4 Karnaugh Map
(K-map). P
2(a) K-map for the boolean function F (A, B, C, D) = m(0, 1, 3, 5, 7, 8, 9, 11, 13, 15) is :
Simplifying, we get
F (A, B, C, D) = D + B̄ C̄.
F (A, B, C, D) = B̄ C̄ + D.
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Essential Prime Implicants: D and B̄ C̄
P
2(b) The K-map for F (W, X, Y, Z) = m(1, 3, 4, 6, 9, 11, 12, 14) is:
Simplifying, we get
F (W, X, Y, Z) = X Z̄ + X̄Z.
F (W, X, Y, Z) = X ⊕ Z.
A and B represent the first and second bits of a Binary number N1 . C and D represent the
first and second bits of a Binary number N2 . The output is to be 1 only if the product N1 N2
is less than or equal to 2. The minimized form of F is: (Note: Here A is MSB and D is LSB)
Solution: From the given data, the truth table is drawn as:
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The K-map for the above expression is drawn as:
Solution: (a) Draw a four variable map using minterms whose values in the function are equal to 1.
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Therefore,
The Boolean expression F = x′ z ′ + yz + w′ y + wy ′ z ′ .
Draw a four variable map using minterms whose values in the function are equalto zero,
Therefore,
The Boolean expression in POS form
F = (w′ + x′ + y ′ + z) · (w + x′ + y) · (y + z ′ )
F = (A′ + C) · (B + C)
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The terms generated by three groups one ‘OR’ operated as follow, The Boolean expression
F = AD′ + AB + AC.
(d) Create K-map for the given Maxterm:
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Number of prime implicants = 5
Quad is redundant group
Number of essential prime implicants = 4
6. (i) Determine the minimum-costP POS expressions for P the function given by:
(a.) f (x1 , x2 , x3 , x4 ) = m(4, 6, 8, 10, 11, 12, 15) + d(3, 5, 7, P 9)
(b.) f (x1 , x2 , x3 , x4 ) = x¯1 x¯3 x¯4 + x3 x4 + x¯1 x¯2 x4 + x1 x2 x¯3 x4 + d(9, 12, 14).
(ii) Find the minimum number of logic gates(AND and OR gate combined) for the imple-
mentation of the four variable function that is equal to 1 if exactly two or exactly three of its
variable are equal to 1 otherwise it is 0(Hint: Find SOP and POS expression from the truth
table).
Solution: (i)
(a) The function can be represented in the form of a Karnaugh map as shown:
In this case, we have to find the sum terms that cover all 0s in the function, the POS expression
is:
f = (x1 + x2 )(x3 + x̄4 )(x̄1 + x̄2 + x̄3 + x4 )
(b) The K-map is derived by placing 1s that correspond to each product term in the expression
used to specify f. The K-map that represents this function is shown:
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The minimum-cost POS expression is,
(ii) Create a truth table that lists all possible combinations of the four variables and the
corresponding output based on the given conditions.
SOP expression:
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POS expression:
Now,
F (A, B, C, D) = (AB + AB̄)C D̄ + (ĀB̄ + AB̄)(C̄ D̄ + C D̄)
F (A, B, C, D) = AC D̄ + B̄ D̄
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Now,
F (A, B, C, D) = (AB + AB̄)(C̄D + CD) + (ĀB̄ + AB̄)(C̄D + CD) + (ĀB̄ + AB̄)(C̄ D̄ + C̄D) +
(ĀB̄ + ĀB)(C̄ D̄ + C D̄
= AD + B̄D + AB̄ C̄ + ĀD̄
Thus, minimized boolean expression is:
F (A, B, C, D) = AD + B̄D + AB̄ C̄ + ĀD̄
8. P
(a) Consider the minterm list form of a Boolean function F given below. F (A, B, C, D) =
(1, 2, 4, 7, 8, 11, 13, 14) where m denotes the minterm. Find the difference between the prime
implicants and the essential prime implicants of the given function F.
(b) Find the total number of Essential prime implicants in the below given K-map.
AB\CD 00 01 11 10
00 1 0 1 1
01 1 0 0 0
11 0 0 0 0
10 1 1 0 1
P
Solution: (a) Plotting K-map for the minterm list form F (A, B, C, D) = (1, 2, 4, 7, 8, 11, 13, 14)
11
Number of prime implicants (n1 ) : 8
Number of Essential prime implicants (n2 ) : 8
Therefore, difference n1 − n2 = 0
(b)
B ′ D′ + A′ C ′ D′ + AB ′ C ′ + A′ B ′ C
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A B C D F (A, B, C, D)
0 0 0 0 X
0 0 0 1 X
0 0 1 0 1
0 0 1 1 1
0 1 0 0 0
0 1 0 1 0
0 1 1 0 X
0 1 1 1 X
1 0 0 0 X
1 0 0 1 X
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 X
1 1 1 1 X
Solving using K-map,
AB\CD 00 01 11 10
00 X X 1 1
01 0 0 X X
11 1 1 X X
10 X X 1 1
Simplified Boolean expression obtained from solving K-map is,
F (A, B, C, D) = A + C
10. Design a logic circuit that controls the elevator door in a three-story building. The circuit
has four inputs. M is a logic signal that indicates when the elevator is moving(M= 1) or
stopped(M=0). F1 , F2 and F3 are floor indicator signals that are normally LOW, and they go
HIGH only when the elevator is positioned at the level of that particular floor. For example,
when the elevator is lined up level with the second floor, F2 = 1 and F1 = F3 = 0. The circuit
output is the OPEN signal, which is normally LOW and will go HIGH when the elevator
door is to be opened. Find the simplified design and draw the diagram of the elevator circuit.
Note: Because the elevator cannot be lined up with more than one floor at a time, the cases
when more than one floor inputs are high can be treated as don’t care condition. When the
elevator reaches at one floor and stops, the door opens. Utilize K map to minimize the output
expression).
Solution: (i) When M = 1, the elevator is moving, and it doesn’t matter that only one of the floor
inputs is high at any given time. The output OPEN must be 0.
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(ii) When M = 0, the elevator is stopped, and only one of the floor inputs is high at any given
time. The output OPEN must be 1.
(iii) When M = 0, the elevator is stopped, and all inputs are 0, indicating that it is not
properly lined up with any floor. The output OPEN must be 0. Form the truth table,
Plot truth table from the above truth table and form the grouping,
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11. With the use of maps, find the simplest SOP form of the function F = f g, where
f = abc′ + c′ d + a′ cd′ + b′ cd′ , and
g = (a + b + c′ + d′ )(b′ + c′ + d)(a′ + c + d′ )
Solution: f =
cd
00 01 11 10
00 0 1 0 1
01 0 1 0 1
ab
11 1 1 0 0
10 0 1 0 1
g=
cd
00 01 11 10
00 1 1 0 1
01 1 1 1 0
ab
11 1 0 1 0
10 1 0 1 1
We multiply the maps of f and g, element by element and the resulting map is as shown
below:
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cd
00 01 11 10
00 0 1 0 1
01 0 1 0 0
ab
11 1 0 0 0
10 0 0 0 1
cd
00 01 11 10
00 0 0 0 0
01 1 1 1 0
ab
11 1 1 1 0
10 1 1 0 0
G(A, B, C, D)
= [G′ (A, B, C, D)]′
= [(AC ′ + BC ′ + BD)′ ]′
= [(AC ′ )′ (BC ′ )′ (BD)′ ]′ =⇒ (DeMorgan’s theorem)
Therefore, we implement this function using a two-level NAND gate circuit as shown below.
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13. Draw a logic diagram using only two-input NOR gates to implement the function:
F (A, B, C, D) = (A ⊕ B)′ (C ⊕ D)
Solution: The given function F can be expressed as
F (A, B, C, D) = (A ⊕ B)′ (C ⊕ D)
= (A′ B ′ + AB)(C ′ D + CD′ )
= A′ B ′ C ′ D + A′ B ′ CD′ + ABC ′ D + ABCD′
First, the 1’s of F are plotted as shown below. Then, from the 0’s,
F ′ = A′ B + AB ′ + CD + C ′ D′
Therefore, the simplified function in the minimum-product-of-sums form is
F = (A + B ′ )(A′ + B)(C + D)(C ′ + D′ )
cd
00 01 11 10
00 0 1 0 1
01 0 0 0 0
ab
11 0 1 0 1
10 0 0 0 0
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It is required to use two-input NOR gates to implement the function FF. Thus,
F = {(A + B ′ )′ + (A′ + B)′ + (C + D)′ + (C ′ + D′ )′ }′
= {(A + B ′ )′ + (A′ + B)′ }′ .{(C + D)′ + (C ′ + D′ )′ }′
= X.Y
where,
X = {(A + B ′ )′ + (A′ + B)′ }′
Y = {(C + D)′ + (C ′ + D′ )′ }′
We replace the AND gate with NOR gate in the expression (F = X.Y ) as
F = X.Y
= [(X.Y )′ ]′
= [X ′ + Y ′ ]′
We implement the given function FF using only two-input NOR gates as shown below.
Note: inverters can be replaced with two-input NOR with its two inputs connected together.
P
14. Implement the Boolean function F (A, B, C, D) = (0, 4, 8, 9, 10, 11, 12, 14), using the two-
level forms of logic:
(a) NAND-AND
(b) AND-NOR
(c) OR-NAND
(b) NOR-OR
Solution: First, the 1’s of the given function:
P
F (A, B, C, D) = (0, 4, 8, 9, 10, 11, 12, 14), are plotted and the remaining squares are filled
with 0’s as shown below.
Then, from the 1’s, as shown below in (a), the simplified function is
F = AB ′ + C ′ D′ + AD′
F ′ = BD + A′ C + A′ D
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(a). Refer to Figure 14 (a)
F = (F ′ )′
= (BD + A′ C + A′ D)′
= (BD)′ (A′ C)′ (A′ D)′
Figure 14 (a)
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Figure 14 (b)
Figure 14 (c)
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The last equation can be implemented using NOR-OR circuit as shown below.
Figure 14 (d)
15. Show that the dual of the exclusive-OR is also its complement.
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Solution: F =
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17. Draw the multiple-level NOR circuit for:
F (A, B, C, D, E) = CD(B + C)A + (B C̄ + DĒ)
Solution: The given function can be expressed as
F = CD(B + C)A + (BC ′ + DE ′ )
= ACD(B + C) + BC ′ + DE ′
But F = (F ′ )′ ; hence,
F = (F ′ )′
= {[ACD(B + C) + BC ′ + DE ′ ]′ }′
= {[ACD(B + C)]′ [BC ′ ]′ [DE ′ ]′ }′
= {[A′ + C ′ + D′ + (B + C)′ ][B ′ + C][D′ + E]}′
= [A′ + C ′ + D′ + (B + C)′ ]′ + [B ′ + C]′ + [D′ + E]′
To represent F using multiple-level NOR circuit:
F = (F ′ )′
= {[[A′ + C ′ + D′ + (B + C)′ ]′ + [B ′ + C]′ + [D′ + E]′ ]′ }′
Based on the last equation, we implement F using multiple-level NOR circuit as shown below.
F = {[[A′ + C ′ + D′ + (B + C)′ ]′ + [B ′ + C]′ + [D′ + E]′ ]′ }′
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G = (G′ )′
= [(w′ + x′ y ′ z ′ )′ ]′
= [w(x′ y ′ z ′ )′ ]′
Substituting Eqn of G in Eqn of F gives:
F = {[w(x′ y ′ z ′ )′ ]′ (xyz ′ }′
Thus, we implement this function using multiple-level NAND circuit as shown below.
F = {[w(x′ y ′ z ′ )′ ]′ (xyz)′ }′
19. Convert the logic diagram of the circuit shown below into a multiple-level NAND circuit.
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Solution: We formulate these functions so that it can be implemented using NAND gates as follows:
First, the function (C + D) can be expressed as
C + D = [(C + D)′ ]′
= [C ′ D′ ]′
Next, for y,
y = (y ′ )′
= {[CD + (C + D)′ ]′ }′
= {[CD + (C ′ D′ )]′ }′
= {(CD)′ .(C ′ D′ )′ }′
For x,
x = (x′ )′
= {[B(C + D)′ + B ′ (C + D)]′ }′
= {[B(C ′ D′ ) + B ′ (C ′ D′ )′ ]′ }′
= {[BC ′ D′ ]′ .[B ′ (C ′ D′ )′ ]′ }′
For w,
w = (w′ )′
= {[A + B(C + D)]′ }′
= {[A + B(C ′ D′ )′ ]′ }′
= {A′ .[B(C ′ D′ )′ ]′ }′
We formulate the output functions of the circuit shown in Qn. so that we can be implemented
using multiple-level NAND circuit:
z = D′
y = {(CD)′ .(C ′ D′ )′ }′
x = {[BC ′ D′ ]′ .[B ′ (C ′ D′ )′ ]′ }′
w = {A′ .[B(C ′ D′ )′ ]′ }′
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20. Simplify the Boolean function F = A + ĀB + ĀB̄C + ĀB̄ C̄D + ...., and obtain both dual and
complement of the simplified function.
Solution: Given F = A + ĀB + ĀB̄C + ĀB̄ C̄D + ....,
Let B + B̄C + B̄ C̄D + .... = G
Therefore, F = A + Ā.G
=⇒ F = A.(1 + G) + Ā.G
= A + A.G + Ā.G
= A + G.(A + Ā)
F =A+G
Thus, recursively we can write that:
F = A + B + C + D + ....
Fd =⇒ A.B.C.D......
F ′ =⇒ Ā.B̄.C̄.D̄.....
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