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Week6 Lab Program Ade Co

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10 views4 pages

Week6 Lab Program Ade Co

Uploaded by

abhinav2349r
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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ADE-CO Lab Programs (BCS302)

Week 2 Lab programs

1. All Gates (NOT, AND,OR,NAND,NOR,EX-OR,EX-NOR )


execute using Pspice and Verilog code.

Logic Gates Verilog Code


1. NOT Gate
//NOT gate using data flow modeling
module not_gate_d(a,y);
input a;
output y;

assign y = ~a;

endmodule

Truth table

Input a Output y

0 1
1 0

2. AND Gate
//AND gate using data flow modeling
module and_gate_d(a,b,y);
input a,b;
output y;

assign y = a & b;

endmodule
Truth table

Input a Input b Output y


0 0 0
0 1 0
1 0 0
1 1 1

3. OR Gate
//OR gate using data flow modeling
module or_gate_d(a,b,y);
input a,b;
output y;

assign y = a | b;

endmodule

Truth table

Input a Input b Output y


0 0 0
0 1 1
1 0 1
1 1 1

4. NAND Gate
//NAND gate using data flow modeling
module nand_gate_d(a,b,y);
input a,b;
output y;
assign y = ~(a & b);

endmodule
Truth table

Input a Input b Output y

0 0 1
0 1 1
1 0 1
1 1 0

5. NOR Gate
//NOR gate using data flow modeling
module nor_gate_d(a,b,y);
input a,b;
output y;

assign y = ~(a | b);

endmodule

Truth table

Input a Input b Output y


0 0 1
0 1 0
1 0 0
1 1 0

6. EX-OR Gate
//EX-OR gate using data flow modeling
module xor_gate_d(a,b,y);
input a,b;
output y;

assign y = a ^ b;

endmodule
Truth table

Input a Input b Output y

0 0 0
0 1 1
1 0 1
1 1 0

7. EX-NOR Gate
//EX-NOR gate using data flow modeling
module xnor_gate_d(a,b,y);
input a,b;
output y;

assign y = ~(a ^ b);

endmodule

Truth table
Input a Input b Output y
0 0 1
0 1 0

1 0 0
1 1 1

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