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15 views

Lab 04

Uploaded by

sam.elise1020
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Computer Systems Engineering Technology

CST 162 – Digital Logic I

Lab 04 - Introduction to Verilog Name : ___________________________


Fall 2024 Due Date: 10/26/2024
Instructor: Ganghee Jang
Possible Points: 100

Objectives
 Learn how to create a Verilog module.
 Apply a Verilog behavioral expressions for logic design.
 Reinforce knowledge and skills to program a MAX 10 FPGA.

Equipment
 DE10-Lite Board
 Quartus Prime
 VGA Monitor (4:3 prefered)

Introduction and Background


In this lab we will be creating pong from last week in another way. In lab 3 you used schematic capture
to add blocks of code and created all the circuitry for the VGA outputs that allow pong to work. This
week you will implement a module to complete pong using Verilog HDL (Hardware Descriptive
Language).

Verilog Basics and Constructs


A Verilog design describes a single system (module) in a sing file. A system can be described from
other modules, so a whole design will have a hierarchical file structure. A module begins with the
keyword module and ends with endmodule. You also need to define a list of input and output signals
for the module. Descriptions for a module will be written between the module and endmodule
statements. Even though most of the syntax for Verilog looks similar to C programming language,
however, the actual meaning can be “very” different. Comments are the same – we can use both //
and /* */. where statements will end with a semicolon, lists of items are separated by commas and
single line comments begin with //. Be careful – Verilog is case sensitive. Also, each Verilog
assignment, definition, or declaration is terminated with a semicolon. Inside () of module header (for
input and output declaration), comma is used to separate each item.
The structure of a Verilog module is shown below.
// Verilog Module Skeleton code
module VerilogModuleExample(
input wire signal1,
input wire signal2,
output output1
);

//Internal declarations
//: signals, constraints, parameters, etc.
wire w1;
wire [10:0] bus1;

//Verilog Behavioral description of logic circuits.


and inst(w1, signal1, signal2);
not inst2 (output1, w1);

endmodule

In this example, the AND gate receives siginal1 and signal2 as inputs. Its output then feeds to w1,
which is also the input to the NOT gate. This connection is created by using the wire w1 as the output
of the AND gate and as the input of the NOT gate. The output of the NOT gate is directly connected to
the output signal output1. Notice on the primitives, the output signal comes before the input signals in
the parameter list.

Structural Verilog is akin to a text-based schematic. This method of design is also sometimes called a
netlist. It specifies how outputs are connected to inputs from one gate to another. One output may
connect to more than one input. In Verilog, individual gates are called primitives. In Lab 3, you used
graphical symbols of schematic gates. Here in Lab 4, you will use text primitives that Verilog
understands. “Wires”, which are just names, are used to connect signals that are not either inputs or
outputs. An example looks like:

This example specifies an AND gate that receives two module input signals signal1 and signal2 as its
input. Its output then feeds the input of an inverter (NOT gate). This connection is specified by placing
the wire name w1 at the AND gate output position and the NOT gate input position. w1 is an internal
connection used to connect a gate output to a gate input/s. The NOT gate output is connected to
module output signal3.

Dataflow Verilog or Behavioral Modeling


Dataflow Verilog uses Boolean expressions with the different signal names and logic operators. The
table below show the equivalent Schematic Capture, Structural, and Dataflow bitwise operators. All
dataflow expressions are continuous assignment statements using the keyword assign. Below the table
is the dataflow version of the two examples above.
Schematic Capture Structural Dataflow

and &

or |

not ~

//Dataflow Example
assign output1 = ~(signal1 & signal2);

Getting Started
You will need to download and use the same template_pong.zip project that you used in lab03. Add and
arrange the modules in the schematic capture, like at the start of lab 3. Do not connect any of the input
or output pins in the schematic capture view. You will create two different blocks to add to the
schematic capture, one for each methodology we have talked about. A refresher of how the modules
should be laid out is below. Remember to connect all of the same name inputs and outputs.
Structural Design
After everything is hooked up, you will need to add a new file to out project for the Verilog code. There
are two ways to add files to our project File->New File and using the new file button in the toolbar.

In the new file wizard, you want to select Verilog HDL File.

You will create your structural design in this file based off of the following inputs and output equations.
The order of the inputs and outputs will determine the order in the symbol we will add to our schematic
capture later. Save this file as VGA_structural.v.
Input signals: ball, border, missed, paddle, paddle2, background, checkerboard
Outputs signals: VGA_B0, VGA_B1, VGA_B2, VGA_B3, VGA_R0, VGA_R1, VGA_R2, VGA_R3,
VGA_G0, VGA_G1, VGA_G2, VGA_G3

You can assign the grounds two different ways. You can do it like we did last week in the schematic
capture, or you can use dataflow assign statements and assign the pins to 1’b0. The “1’” is specifying
that it is one bit wide, the “b” specifies that it is a binary number, and the “0” is logic level low.
Similarly, 1’b1 would be a logic high and 4’b1010 would be binary version of 10 decimal.
assign VGA_B2 = 1'b0;
assign VGA_B0 = 1'b0;
assign VGA_G2 = 1'b0;
assign VGA_G1 = 1'b0;
assign VGA_G0 = 1'b0;
assign VGA_R1 = 1'b0;
assign VGA_R0 = 1'b0;

After entering the code, you will need to generate a block symbol for the module code. This is done by
right-clicking on the VGA_structural.v filename and making the appropriate selection (Create Symbols
Files for Current File).

<Beware the file name difference!>

Add the block symbol you created to your top-level schematic and connect it with the orthogonal node
tool. The block symbol should look like the one in the following image:

Finish your design!

Dataflow Design (behavioral modeling)


Make a new file named VGA_dataflow.v
Implement the same logic part with “dataflow” approach discussed above.
Replace the block from VGA_structural.v with the block from VGA_dataflow.v
Submission instructions
1) Get check-off!
a. One check-off after finish your design with the block from VGA_structural.v
b. Another check-off after replacing with the module from dataflow design.
2) Screen capture the code in your VGA_structual.v, and paste below. Please adjust your screen
well when you perform screen capture so that your instructor can read yours well.

3) Screen capture the code in your VGA_dataflow.v, and paste below.

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