CSE211

Computer Organization and

Design

Lecture : 3 Tutorial: 1 Practical: 0 Credit: 4

1
Unit 1 : Basics of Digital Electronics

Introduction
Logic Gates
Flip Flops
Decoder
Encoder
Multiplexers
Demultiplexer

2
 Basic Terms
• Digital
• Digital Computers
• Storage?
• Base- Decimal, Binary
• Instruction
• Program

9/7/2023
4
 What are the components of
Computers?

9/7/2023
 Basic Organization of a Computer

9/7/2023
7
8
Computer Organization and Architecture lets
you know how exactly each instruction is
executed at the micro level. The data flow,
timing analysis, memory hierarchy, trade offs
between execution cycles, hardware
requirements/costs, software-hardware trade-
offs can be known.

9/7/2023
• Computer Organization : It is concerned with the
way hardware components operate and the way they
are connected together to form a computer system.
• Computer Architecture : It is concerned with the
structure and behavior of the computer as seen by
the user. It includes the information, formats, the
instruction set, and techniques for addressing
memory.
• Computer Design : It is concerned with the hardware
design of the computer. Computer design is
concerned with the determination of what hardware
should be used and how the parts should be
connected.

9/7/2023
 Computer Organization

9/7/2023
 Instruction set architecture
• the instruction set architecture refers to what the
programmer sees as the machine's instruction set.
The instruction set is the boundary between the
hardware and the software, and most of the
decisions concerning the instruction set affect the
hardware, and the converse is also true, many
hardware decisions may beneficially/adversely affect
the instruction set.

9/7/2023
 Structure & Function
• Structure is the way in which components
relate to each other
• Function is the operation of individual
components as part of the structure

9/7/2023
15
16
17
 Question
• The output X of X-OR gate is high when
1. A=1 , B=1
2. A=0 , B=1
3. A=0 , B=0
4. A=1 , B=0
5. 2nd and 4th both
6. None of these

18
Integrated Circuits

An IC is a small silicon semiconductors crystal called chip containing the

electronic components for digital gates.
- Various gates are interconnected inside chip to form required circuit.
- Chip is mounted in ceramic/plastic container connected to external pin

Small scale Integration (SSI) : less than 10 gates

Medium Scale Integration(MSI) : between 10 to 200 gates

(decoders, adders, registers)

Large Scale Integration(LSI) : between 200 and few thousands gates

( Processors, Memory Chips)

Very Large Scale Integration (VLSI) : Thousands of gate within

single package ( Large Memory Arrays, Complex Microcomputer Chips)

19
 Combinational Circuits
• No feedback paths
• No memory
• Combinational circuit is a connected arrangement of logic gates with set of
inputs and outputs.
• Binary values of outputs are a function of binary combination of inputs.
• Output is independent of time and depends only on the present input.
• Examples are half Adder, Full adder, Encoder, Decoder, Multiplexer, De-
multiplexer.

20
 Sequential Circuits
• Feedback paths exist( the key to processing past and present
information of an input sequence.)
• Memory present
• 2 Types- Synchronous and Asynchronous
• Synchronous sequential circuits employ signals that effect
storage elements only at discrete instants of time.
• Synchronization is achieved with help of device called clock.
• Output depends not only on present input but also on the
past output.
• Examples are Flip-flop, register, counter.

21
Sequential Circuits

22
 Question
• Sequential circuits have which of the following
signal?
– Inputs
– Outputs
– Feedback
– All of above

23
 Question
• Combinational circuits don’t have which of the
following signal?
– Inputs
– Outputs
– Feedback
– All of above

24
25
26
27
28
 CSE211

Computer Organization and

Design

Lecture : 3 Tutorial: 1 Practical: 0 Credit: 4

1
Unit 1 : Basics of Digital Electronics

Introduction
Logic Gates
Flip Flops
Decoder
Encoder
Multiplexers
Demultiplexer
Registers

2
 Half Adder
• A combinational circuit that performs the arithmetic addition of two bits is
called a half-adder.
• Two input variables used.
• The output variables are Sum and Carry.
• The variable S represents the least significant bit of the sum.
• The C output is 0 unless both the inputs are 1.

3
Half Adder

4
 Full Adder
• A combinational circuit that performs the arithmetic addition of three bits
is called a full-adder.
• Two half-adders are needed to implement a full-adder.
• Three input variables used.
• The output variables are Sum and Carry.
• The variable S represents the least significant bit of the sum.
• The binary variable C gives the output carry.

5
Full Adder

6
7
8
9
10
11
 Applications of multiplexer

• Data Routing
• Parallel to Serial Conversion
• Logic Function Generation

12
A Demultiplexer, sometimes abbreviated DMUX is a circuit that has
one input and more than one output. It is used when a circuit wishes
to send a signal to one of many devices

13
14
 When the load input is 1 , the
data in the four inputs are
transferred into the register with
the next positive transition of a
clock pulse

When the load input is 0, the

data inputs are inhibited and the D-
output of flip flop are connected to
their inputs.

15
16
17
18
19
Register Transfer and Micro-operations

Overview

➢ Register Transfer Language

➢ Register Transfer

➢ Bus and Memory Transfers

➢ Logic Micro-operations

➢ Shift Micro-operations

➢ Arithmetic Logic Shift Unit

CSE 211
Register Transfer and Micro-operations 2

Register Transfer Language

➢ Combinational and sequential circuits can be used to create simple

digital systems.

➢ These are the low-level building blocks of a digital computer.

➢ Simple digital systems are frequently characterized in terms of

➢ the registers they contain, and
➢ the operations that are performed on data stored in them

➢ The operations executed on the data in registers are called micro-

operations e.g. shift, count, clear and load

CSE 211
Register Transfer and Micro-operations 3

Register Transfer Language

Internal hardware organization of a digital computer :

➢Set of registers and their functions

➢ Sequence of microoperations performed on binary

information stored in registers

➢Control signals that initiate the sequence of micro-

operations (to perform the functions)

CSE 211
Register Transfer and Micro-operations 4

Register Transfer Language

➢ Rather than specifying a digital system in words, a specific notation is
used, Register Transfer Language

➢ The symbolic notation used to describe the micro operation transfer

among register is called a register transfer language

➢ For any function of the computer, the register transfer language can be
used to describe the (sequence of) micro-operations

➢ Register transfer language

➢ A symbolic language
➢ A convenient tool for describing the internal organization of
digital computers in concise/precise manner.

CSE 211
Register Transfer and Micro-operations 5

Register Transfer Language

➢ Registers are designated by capital letters, sometimes followed by
numbers (e.g., A, R13, IR)
➢ Often the names indicate function:
➢ MAR - memory address register
➢ PC - program counter
➢ IR - instruction register

➢ Registers and their contents can be viewed and represented in various

ways
➢ A register can be viewed as a single entity:

MAR

CSE 211
Register Transfer and Micro-operations 6

Register Transfer Language

• Designation of a register

- a register
- portion of a register
- a bit of a register

• Common ways of drawing the block diagram of a register

Register Showing individual bits

R1 7 6 5 4 3 2 1 0

15 0 15 8 7 0
R2 PC(H) PC(L)
Numbering of bits Subfields

CSE 211
Register Transfer and Micro-operations 7

Register Transfer Language

• Copying the contents of one register to another is a register transfer

• A register transfer is indicated as

R2  R1

➢ In this case the contents of register R1 are copied (loaded) into

register R2
➢ A simultaneous transfer of all bits from the source R1 to the
destination register R2, during one clock pulse
➢ Note that this is a non-destructive; i.e. the contents of R1 are not
altered by copying (loading) them to R2

CSE 211
Register Transfer and Micro-operations 8

Register Transfer Language

• A register transfer such as

R3  R5

Implies that the digital system has

– the data lines from the source register (R5) to the destination
register (R3)
– Parallel load in the destination register (R3)
– Control lines to perform the action

CSE 211
Register Transfer and Micro-operations 9

Control Functions

➢ Often actions need to only occur if a certain condition is true

➢ This is similar to an “if” statement in a programming language
➢ In digital systems, this is often done via a control signal, called a control
function
➢ If the signal is 1, the action takes place
➢ This is represented as:

P: R2  R1

Which means “if P = 1, then load the contents of register R1 into

register R2”, i.e., if (P = 1) then (R2  R1)

CSE 211
Register Transfer and Micro-operations 10

Hardware Implementation of Controlled Transfers

Implementation of controlled transfer
P: R2  R1

Block diagram Control P Load

R2 Clock
Circuit
n
R1

Timing diagram t t+1

Clock

Load
Transfer occurs here

➢ The same clock controls the circuits that generate the control function and the
destination register
➢ Registers are assumed to use positive-edge-triggered flip-flops

CSE 211
Register Transfer and Micro-operations 11

Basic Symbols in Register Transfer

Symbols Description Examples

Capital letters Denotes a register MAR, R2
& Numerals
Parentheses () Denotes a part of a register R2(0-7), R2(L)
Arrow  Denotes transfer of information R2  R1
Colon : Denotes termination of control function P:
Comma , Separates two micro-operations A  B, B  A

CSE 211
Register Transfer and Micro-operations 1

Overview

➢ Register Transfer Language

➢ Register Transfer

➢ Bus and Memory Transfers

➢ Logic Micro-operations

➢ Shift Micro-operations

➢ Arithmetic Logic Shift Unit

CSE 211
Register Transfer and Micro-operations 2

Connecting Registers - Bus Transfer

➢ In a digital system with many registers, it is impractical to have data and
control lines to directly allow each register to be loaded with the contents
of every possible other registers

➢ To completely connect n registers → n(n-1) lines

➢ O(n2) cost
➢ This is not a realistic approach to use in a large digital system

➢ Instead, take a different approach

➢ Have one centralized set of circuits for data transfer – the bus

➢ BUS STRUCTURE CONSISTS OF SET OF COMMON LINES, ONE FOR EACH BIT
OF A REGISTER THROUGH WHICH BINARY INFORMATION IS TRANSFERRED
ONE AT A TIME

➢ Have control circuits to select which register is the source, and which is the
destination

CSE 211
Register Transfer and Micro-operations 3

Connecting Registers - Bus Transfer

➢ One way of constructing common bus system is with multiplexers

➢ Multiplexer selects the source register whose binary information is
kept on the bus.

➢ Construction of bus system for 4 register (Next Fig)

➢ 4 bit register X 4
➢ four 4X1 multiplexer
➢ Bus selection S0, S1

CSE 211
Register Transfer and Micro-operations 4

Connecting Registers - Bus Transfer

CSE 211
Register Transfer and Micro-operations 5

Connecting Registers - Bus Transfer

➢ For a bus system to multiplex k registers of n bits each

➢ No. of multiplexer = n = No. of bits

➢ Size of each multiplexer = k x 1, k data lines in each

MUX

➢ Construction of bus system for 8 register with 16 bits

➢ 16 bit register X 8
➢ Sixteen 8X1 multiplexer
➢ Bus selection S0, S1, S2

CSE 211
Register Transfer and Micro-operations 6

Connecting Registers - Bus Transfer

CSE 211
Register Transfer and Micro-operations 7

Connecting Registers - Bus Transfer

CSE 211
Register Transfer and Micro-operations 8

Connecting Registers - Bus Transfer

CSE 211
Register Transfer and Micro-operations 9

Memory - RAM
➢ Memory (RAM) can be thought as a sequential circuits containing
some number of registers
➢ Memory stores binary information in groups of bits called words
➢ These registers hold the words of memory
➢ Each of the r registers is indicated by an address
➢ These addresses range from 0 to r-1
➢ Each register (word) can hold n bits of data
➢ Assume the RAM contains r = 2k words. It needs the following
data input lines
1. n data input lines
2. n data output lines n

3. k address lines address lines

k
4. A Read control line RAM
Read
5. A Write control line unit
Write
n
data output lines
Register Transfer and Micro-operations 10

Memory Transfer
Memory is usually accessed in computer systems by putting the desired
address in a special register, the Memory Address Register (MAR, or AR)

M
Memory Read
AR
unit Write

Data out Data in

CSE 211
Register Transfer and Micro-operations 11

Memory Read

➢ To read a value from a location in memory and load it into a

register, the register transfer language notation looks like this:

R1  M[MAR]

➢ This causes the following to occur

1. The contents of the MAR get sent to the memory address
lines
2. A Read (= 1) gets sent to the memory unit
3. The contents of the specified address are put on the
memory’s output data lines
4. These get sent over the bus to be loaded into register R1

CSE 211
Register Transfer and Micro-operations 12

Memory Write

➢ To write a value from a register to a location in memory looks like

this in register transfer language:

M[MAR]  R1

➢ This causes the following to occur

1. The contents of the MAR get sent to the memory address
lines
2. A Write (= 1) gets sent to the memory unit
3. The values in register R1 get sent over the bus to the data
input lines of the memory
4. The values get loaded into the specified address in the
memory

CSE 211
Register Transfer and Micro-operations 13

MICROOPERATIONS

Computer system microoperations are of four types:

➢ Register transfer microoperations

➢ Arithmetic microoperations
➢ Logic microoperations
➢ Shift microoperations

CSE 211
Register Transfer and Micro-operations 14

SUMMARY OF R. TRANSFER MICROOPERATIONS

A B 1.Transfer content of reg. B into reg. A

A  constant 3.Transfer a binary constant into reg. A

ABUS  R1, R2 ← ABUS 4.Transfer content of R1 into bus A and, at the same time,
transfer content of bus A into R2
AR 5.Address register
DR 6.Data register
M[R] 7.Memory word specified by reg. R
M 8.Equivalent to M[AR]
DR  M 9.Memory read operation: transfers content of
memory word specified by AR into DR
M  DR 10.Memory write operation: transfers content of
DR into memory word specified by AR

CSE 211
Register Transfer and Micro-operations 15

Arithmetic MICROOPERATIONS
• The basic arithmetic microoperations are
– Addition
– Subtraction
– Increment
– Decrement

• The additional arithmetic microoperations are

– Add with carry
– Subtract with borrow
– Transfer/Load
– etc. …

Summary of Typical Arithmetic Micro-Operations

R3  R1 + R2 Contents of R1 plus R2 transferred to R3
R3  R1 - R2 Contents of R1 minus R2 transferred to R3
R2  R2’ Complement the contents of R2
R2  R2’+ 1 2's complement the contents of R2 (negate)
R3  R1 + R2’+ 1 subtraction
R1  R1 + 1 Increment
R1  R1 - 1 Decrement

CSE 211
Register Transfer and Micro-operations 1

Overview

➢ Register Transfer Language

➢ Register Transfer

➢ Bus and Memory Transfers

➢ Arithmetic Micro-operations

➢ Logic Micro-operations

➢ Shift Micro-operations

➢ Arithmetic Logic Shift Unit

CSE 211
Register Transfer and Micro-operations 2

MICROOPERATIONS

Computer system microoperations are of four types:

➢ Register transfer microoperations

➢ Arithmetic microoperations
➢ Logic microoperations
➢ Shift microoperations

CSE 211
Register Transfer and Micro-operations 3

Arithmetic MICROOPERATIONS
• The basic arithmetic microoperations are
– Addition
– Subtraction
– Increment
– Decrement

• The additional arithmetic microoperations are

– Add with carry
– Subtract with borrow
– Transfer/Load
– etc. …

Summary of Typical Arithmetic Micro-Operations

R3  R1 + R2 Contents of R1 plus R2 transferred to R3
R3  R1 - R2 Contents of R1 minus R2 transferred to R3
R2  R2’ Complement the contents of R2
R2  R2’+ 1 2's complement the contents of R2 (negate)
R3  R1 + R2’+ 1 subtraction
R1  R1 + 1 Increment
R1  R1 - 1 Decrement

CSE 211
Register Transfer and Micro-operations 4

Binary Adder

CSE 211
Register Transfer and Micro-operations 5

Binary Adder-Subtractor

Binary Adder-Subtractor

B3 A3 B2 A2 B1 A1 B0 A0

FA C3 FA C2 FA C1 FA C0

C4 S3 S2 S1 S0

➢ Mode input M controls the operation

➢ M=0 ---- adder
➢ M=1 ---- subtractor

CSE 211
Register Transfer and Micro-operations 6

Binary Incrementer

Binary Incrementer

A3 A2 A1 A0 1

x y x y x y x y
HA HA HA HA
C S C S C S C S

C4 S3 S2 S1 S0

CSE 211
Register Transfer and Micro-operations 7

Arithmetic Circuits
Cin
S1
S0

A0 X0 C0

S1 D0
S0
Y0
FAC1
B0 0
1 4x1
2
3
MUX
A1 X1 C1

S1 D1
S0 FA
B1 0 Y1 C2
1 4x1
2
3
MUX
A2 X2 C2

S1 D2
S0 FA
B2 0 Y2 C3
1 4x1
2
3
MUX
A3 X3 C3

S1 D3
S0 FA
B3 0 Y3 C4
1 4x1
2
3
MUX Cout
0 1

CSE 211
Register Transfer and Micro-operations 1

Overview

➢ Register Transfer Language

➢ Register Transfer

➢ Bus and Memory Transfers

➢ Arithmetic Micro-operations

➢ Logic Micro-operations

➢ Shift Micro-operations

➢ Arithmetic Logic Shift Unit

CSE 211
Register Transfer and Micro-operations 2

Logic Micro operations

CSE 211
Register Transfer and Micro-operations 3

Logic Microoperations

CSE 211
Register Transfer and Micro-operations 4

Hardware Implementation
Ai
0
Bi

1
4X1 Fi
MUX
2

3 Select

S1
S0

Function table
S1 S0 Output -operation
0 0 F=AB AND
0 1 F=AB OR
1 0 F=AB XOR
1 1 F = A’ Complement

CSE 211
Register Transfer and Micro-operations 5

Applications of Logic Microoperations

➢ Logic micro operations can be used to manipulate individual bits or a
portions of a word in a register. They can be used to change bit values,
delete a group of bits, or insert new bit values into a register.

➢ Consider the data in a register A. In another register, B, is bit data that

will be used to modify the contents of A

➢ Selective-set AA+B
➢ Selective-complement AAB
➢ Selective-clear A  A • B’
➢ Mask (Delete) AA•B
➢ Clear AAB
➢ Insert A  (A • B) + C
➢ Compare AAB

CSE 211
Register Transfer and Micro-operations 6

Applications of Logic Microoperations

1. In a selective set operation, the bit pattern in B is used to set certain bits in A

1 1 0 0 At
1010 B
1 1 1 0 At+1 (A  A + B)

If a bit in B is set to 1, that same position in A gets set to 1, otherwise that

bit in A keeps its previous value
2. In a selective complement operation, the bit pattern in B is used to
complement certain bits in A
1 1 0 0 At
1010 B

0 1 1 0 At+1 (A  A  B)
If a bit in B is set to 1, that same position in A gets complemented from its
original value, otherwise it is unchanged
CSE 211
Register Transfer and Micro-operations 7

Applications of Logic Microoperations

3. In a selective clear operation, the bit pattern in B is used to clear certain bits
in A
1 1 0 0 At
1010 B

0 1 0 0 At+1 (A  A  B’)
If a bit in B is set to 1, that same position in A gets set to 0, otherwise it is
unchanged
4. In a mask operation, the bit pattern in B is used to clear certain bits in A
1 1 0 0 At
1010 B

1 0 0 0 At+1 (A  A  B)

If a bit in B is set to 0, that same position in A gets set to 0, otherwise it is

unchanged

CSE 211
Register Transfer and Micro-operations 8

Applications of Logic Microoperations

5. In a clear operation, if the bits in the same position in A and B are the same,
they are cleared in A, otherwise they are set in A
1 1 0 0 At
1010 B

0 1 1 0 At+1 (A  A  B)

CSE 211
Register Transfer and Micro-operations 9

Applications of Logic Microoperations

6. An insert operation is used to introduce a specific bit pattern into A register,
leaving the other bit positions unchanged
This is done as
– A mask operation to clear the desired bit positions, followed by
– An OR operation to introduce the new bits into the desired positions
– Example
• Suppose you wanted to introduce 1010 into the low order four bits of A:
• 1101 1000 1011 0001 A (Original)
1101 1000 1011 1010 A (Desired)

• 1101 1000 1011 0001 A (Original)

1111 1111 1111 0000 Mask
1101 1000 1011 0000 A (Intermediate)
0000 0000 0000 1010 Added bits
1101 1000 1011 1010 A (Desired)

CSE 211
 Question
• Register A:1100 Register B:1010 After applying
Selective-Complement on the given data,
value of register A is:
– 1001
– 0111
– 1000
– 0110
Register Transfer and Micro-operations 11

Shift Microoperations
• There are three types of shifts
– Logical shift
– Circular shift
– Arithmetic shift
• What differentiates them is the information that goes into the serial input

• A right shift operation

Serial
input

• A left shift operation

Serial
input

CSE 211
Register Transfer and Micro-operations 12

Logical Shift
• In a logical shift the serial input to the shift is a 0.

• A right logical shift operation:

0

• A left logical shift operation:

0

• In a Register Transfer Language, the following notation is used

– shl for a logical shift left
– shr for a logical shift right
– Examples:
• R2  shr R2
• R3  shl R3
CSE 211
Register Transfer and Micro-operations 13

Circular Shift
• In a circular shift the serial input is the bit that is shifted out of the other
end of the register.

• A right circular shift operation:

• A left circular shift operation:

• In a RTL, the following notation is used

– cil for a circular shift left
– cir for a circular shift right
– Examples:
• R2  cir R2
• R3  cil R3

CSE 211
Register Transfer and Micro-operations 15

Arithmetic Shift
• An arithmetic shift is meant for signed binary numbers (integer)
• An arithmetic left shift multiplies a signed number by two
• An arithmetic right shift divides a signed number by two
• Sign bit : 0 for positive and 1 for negative
• The main distinction of an arithmetic shift is that it must keep the sign of
the number the same as it performs the multiplication or division

• A right arithmetic shift operation:

sign
bit

• A left arithmetic shift operation: 0

sign
bit

CSE 211
Register Transfer and Micro-operations 16

Arithmetic Shift
• An left arithmetic shift operation must be checked for the overflow

0
sign
bit

Before the shift, if the leftmost two

V bits differ, the shift will result in an
overflow

• In a RTL, the following notation is used

– ashl for an arithmetic shift left
– ashr for an arithmetic shift right
– Examples:
» R2  ashr R2
» R3  ashl R3

CSE 211
 Question
• What is the effect on the output if ashr
operation is performed?
– Subtraction by 2
– Multiplication by 2
– Division by 2
– Addition by 2
Register Transfer and Micro-operations 18

Hardware Implementation of Shift Microoperation

CSE 211
Register Transfer and Micro-operations 19

Arithmetic Logic and Shift Unit

S3
S2 C
i
S1
S0 S3 S2 S1 S0 Cin Operation
0 0 0 0 0 F=A
0 0 0 0 1 F=A+1
D 0 0 0 1 0 F=A+B
Arithmetic i
0 0 0 1 1 F=A+B+1
Circuit 0 0 1 0 0 F = A + B’
0 0 1 0 1 F = A + B’+ 1
Select 0 0 1 1 0 F=A-1
0 0 1 1 1 F=A
0 1 0 0 X F=AB
0 4x1 0 1 0 1 X F=AB
C i+1 F 0 1 1 0 X F=AB
1 i
MUX 0 1 1 1 X F = A’
2 1 0 X X X F = shr A
3 1 1 X X X F = shl A

E
Logic i
Bi
Circuit
A
i
shr
A
i-1
shl
A
i+1

CSE 211
Digital Logic Circuits 1 Introduction

DIGITAL LOGIC CIRCUITS

Logic Gates

Boolean Algebra

Map Specification

Combinational Circuits

Flip-Flops

Sequential Circuits

Memory Components

Integrated Circuits

Computer Organization Computer Architectures Lab

Digital Logic Circuits 2 Logic Gates

LOGIC GATES
Digital Computers

- Imply that the computer deals with digital information, i.e., it deals
with the information that is represented by binary digits
- Why BINARY ? instead of Decimal or other number system ?

* Consider electronic signal

1 7
6
5 signal
4
3 range
2
0 1
0
binary octal

0 1 2 3 4 5 6 7 8 9
* Consider the calculation cost - Add 0 0 1 2 3 4 5 6 7 8 9
1 1 2 3 4 5 6 7 8 9 10
0 1 2 2 3 4 5 6 7 8 9 1011
3 3 4 5 6 7 8 9 101112
0 0 1 4 4 5 6 7 8 9 10111213
1 1 10 5
6
5 6 7 8 9 1011121314
6 7 8 9 101112131415
7 7 8 9 10111213141516
8 8 9 1011121314151617
9 9 101112131415161718

Computer Organization Computer Architectures Lab

Digital Logic Circuits 3 Logic Gates

BASIC LOGIC BLOCK - GATE -

Binary Binary
Digital Digital
. Gate Output
Input .
Signal . Signal

Types of Basic Logic Blocks

- Combinational Logic Block

Logic Blocks whose output logic value
depends only on the input logic values

- Sequential Logic Block

Logic Blocks whose output logic value
depends on the input values and the
state (stored information) of the blocks

Functions of Gates can be described by

- Truth Table
- Boolean Function
- Karnaugh Map
Computer Organization Computer Architectures Lab
Digital Logic Circuits 4 Logic Gates

COMBINATIONAL GATES
Name Symbol Function Truth Table
A B X
A X=A•B 0 0 0
AND B
X or
X = AB
0
1
1
0
0
0
1 1 1
A B X
A 0 0 0
OR X X=A+B 0 1 1
B 1 0 1
1 1 1
A X
I A X X = A’ 0
1
1
0
A X
Buffer A X X=A 0 0
1 1
A B X
A 0 0 1
NAND X X = (AB)’ 0
1
1
0
1
1
B 1 1 0
A B X
A 0 0 1
NOR X X = (A + B)’ 0
1
1
0
0
0
B 1 1 0
A B X
A X=AB
XOR X or 0 0 0
Exclusive OR 0 1 1
B X = A’B + AB’ 1 0 1
1 1 0
A B X
A X = (A  B)’
XNOR X or
0
0
0
1
1
0
Exclusive NOR
or Equivalence B X = A’B’+ AB 1 0 0
1 1 1

Computer Organization Computer Architectures Lab

Digital Logic Circuits 5 Boolean Algebra

BOOLEAN ALGEBRA
Boolean Algebra

* Algebra with Binary(Boolean) Variable and Logic Operations

* Boolean Algebra is useful in Analysis and Synthesis of
Digital Logic Circuits

- Input and Output signals can be

represented by Boolean Variables, and
- Function of the Digital Logic Circuits can be represented by
Logic Operations, i.e., Boolean Function(s)
- From a Boolean function, a logic diagram
can be constructed using AND, OR, and I

Truth Table

* The most elementary specification of the function of a Digital Logic

Circuit is the Truth Table

- Table that describes the Output Values for all the combinations
of the Input Values, called MINTERMS
- n input variables → 2n minterms

Computer Organization Computer Architectures Lab

Digital Logic Circuits 6 Boolean Algebra

LOGIC CIRCUIT DESIGN

x y z F
0 0 0 0
Truth 0 0 1 1
Table 0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1

Boolean F = x + y’z
Function

x
F
Logic y
Diagram
z

Computer Organization Computer Architectures Lab

Digital Logic Circuits 7 Boolean Algebra

BASIC IDENTITIES OF BOOLEAN ALGEBRA

[1] x + 0 = x [2] x • 0 = 0
[3] x + 1 = 1 [4] x • 1 = x
[5] x + x = x [6] x • x = x
[7] x + x’ = 1 [8] x • X’ = 0
[9] x + y = y + x [10] xy = yx
[11] x + (y + z) = (x + y) + z [12] x(yz) = (xy)z
[13] x(y + z) = xy +xz [14] x + yz = (x + y)(x + z)
[15] (x + y)’ = x’y’ [16] (xy)’ = x’ + y’
[17] (x’)’ = x
[15] and [16] : De Morgan’s Theorem
Usefulness of this Table
- Simplification of the Boolean function
- Derivation of equivalent Boolean functions
to obtain logic diagrams utilizing different logic gates
-- Ordinarily ANDs, ORs, and Inverters
-- But a certain different form of Boolean function may be convenient
to obtain circuits with NANDs or NORs
→ Applications of De Morgans Theorem

x’y’ = (x + y)’ x’+ y’= (xy)’

I, AND → NOR I, OR → NAND

Computer Organization Computer Architectures Lab

Digital Logic Circuits 8 Boolean Algebra

EQUIVALENT CIRCUITS

Many different logic diagrams are possible for a given Function

F = ABC + ABC’ + A’C .......…… (1)
= AB(C + C’) + A’C [13] ..…. (2)
= AB • 1 + A’C [7]
= AB + A’C [4] ...…. (3)
A
B
(1) C
F

(2) A
B

C F

(3) A
B
F
C

Computer Organization Computer Architectures Lab

Digital Logic Circuits 9 Boolean Algebra

COMPLEMENT OF FUNCTIONS
A Boolean function of a digital logic circuit is represented by only using
logical variables and AND, OR, and Invert operators.

→ Complement of a Boolean function

- Replace all the variables and subexpressions in the parentheses

appearing in the function expression with their respective complements

A,B,...,Z,a,b,...,z  A’,B’,...,Z’,a’,b’,...,z’
(p + q)  (p + q)’

- Replace all the operators with their respective

complementary operators

AND  OR
OR  AND

- Basically, extensive applications of the De Morgan’s theorem

(x1 + x2 + ... + xn )’  x1’x2’... xn’

(x1x2 ... xn)'  x1' + x2' +...+ xn'

Computer Organization Computer Architectures Lab

Digital Logic Circuits 10 Map Simplification

SIMPLIFICATION

Truth Boolean
Table Function
Unique Many different expressions exist
Simplification from Boolean function

- Finding an equivalent expression that is least expensive to implement

- For a simple function, it is possible to obtain
a simple expression for low cost implementation
- But, with complex functions, it is a very difficult task

Karnaugh Map (K-map) is a simple procedure for

simplifying Boolean expressions.

Truth
Table
Simplified
Karnaugh Boolean
Map Function
Boolean
function

Computer Organization Computer Architectures Lab

Digital Logic Circuits 11 Map Simplification

KARNAUGH MAP
Karnaugh Map for an n-input digital logic circuit (n-variable sum-of-products
form of Boolean Function, or Truth Table) is
- Rectangle divided into 2n cells
- Each cell is associated with a Minterm
- An output(function) value for each input value associated with a
mintern is written in the cell representing the minterm
→ 1-cell, 0-cell

Each Minterm is identified by a decimal number whose binary representation

is identical to the binary interpretation of the input values of the minterm.
Karnaugh Map
x Identification x value
x
0
F
1 0 0 of the cell 0 0 of F

1 0 1 1 1 1
F(x) = (1)
1-cell
x
x y F
y 0 1 x
0 0 0 0 0 1 y 0 1
0 1 1 0 0 1
1 0 1 1 2 3
1 1 1 1 1 0
F(x,y) =  (1,2)
Computer Organization Computer Architectures Lab
Digital Logic Circuits 12 Map Simplification

KARNAUGH MAP
x y z F
0 0 0 0
yz y yz
0 0 1 1
0 1 0 1 x 00 01 11 10 x 00 01 11 10
0 1 1 0 0 0 1 3 2 0 0 1 0 1
1 0 0 1 x 1 4 5 7 6
1 0 1 0 1 1 0 0 0
1 1 0 0 z
1 1 1 0 F(x,y,z) =  (1,2,4)

wx w
uv 00 01 11 10
u v w x F
0 0 0 0 0
0 0 0 1 1 00 0 1 3 2 v
0 0 1 0 0
0 0 1 1 1 01 4 5 7 6
0 1 0 0 0
u 11
12 13 15 14
0 1 0 1 0
0 1 1 0 1
0 1 1 1 0 10 8 9 11 10
1
1
0
0
0
0
0
1
1
1
x
1 0 1 0 0 wx
1 0 1 1 1 uv 00 01 11 10
1 1 0 0 0 00 0 1 1 0
1 1 0 1 0
1 1 1 0 1
1 1 1 1 0 01 0 0 0 1
11 0 0 0 1
10 1 1 1 0
F(u,v,w,x) =  (1,3,6,8,9,11,14)
Computer Organization Computer Architectures Lab
Digital Logic Circuits 13 Map Simplification

MAP SIMPLIFICATION - 2 ADJACENT CELLS -

Rule: xy’ +xy = x(y+y’) = x

Adjacent cells

- binary identifications are different in one bit

→ minterms associated with the adjacent
cells have one variable complemented each other

Cells (1,0) and (1,1) are adjacent

Minterms for (1,0) and (1,1) are
x • y’ --> x=1, y=0
x • y --> x=1, y=1

F = xy’+ xy can be reduced to F = x

From the map y
x 0 1
0 0 0 2 adjacent cells xy’ and xy
1 1 1 → merge them to a larger cell x

F(x,y) =  (2,3)
= xy’+ xy
=x

Computer Organization Computer Architectures Lab

Digital Logic Circuits 14 Map Simplification

MAP SIMPLIFICATION - MORE THAN 2 CELLS -

wx u’v’ wx u’x’
u’v’w’x’ + u’v’w’x + u’v’wx + u’v’wx’ w w
= u’v’w’(x’+x) + u’v’w(x+x’) uv uv
= u’v’w’ + u’v’w 1 1 1 1 1 1 1 1
= u’v’(w’+w) vw’ 1 1 1 1
v v
= u’v’ 1 1 1 1
u u
1 1 1 1
uw x
x v’x

u’v’w’x’+u’v’w’x+u’vw’x’+u’vw’x+uvw’x’+uvw’x+uv’w’x’+uv’w’x
= u’v’w’(x’+x) + u’vw’(x’+x) + uvw’(x’+x) + uv’w’(x’+x)
= u’(v’+v)w’ + u(v’+v)w’
= (u’+u)w’ = w’
wx
uv w uv w V’
1 1 1 1 1 1
w’
1 1
v v
1 1 1 1 1 1
u u u
1 1 1 1 1 1
x x

Computer Organization Computer Architectures Lab

Digital Logic Circuits 15 Map Simplification

MAP SIMPLIFICATION
wx
uv 00 01 11 10 w
00 1 1 0 1 1 1 0 1
01 0 0 0 0 0 0 0 0
v
11 0 1 1 0 0 1 1 0
10 0 1 0 0 u
0 1 0 0
x
F(u,v,w,x) =  (0,1,2,9,13,15)
(0,1), (0,2), (0,4), (0,8) Merge (0,1) and (0,2)
Adjacent Cells of 1 --> u’v’w’ + u’v’x’
Adjacent Cells of 0 Merge (1,9)
(1,0), (1,3), (1,5), (1,9) --> v’w’x
... Merge (9,13)
... --> uw’x
Adjacent Cells of 15 Merge (13,15)
(15,7), (15,11), (15,13), (15,14) --> uvx

F = u’v’w’ + u’v’x’ + v’w’x + uw’x + uvx

But (9,13) is covered by (1,9) and (13,15)
F = u’v’w’ + u’v’x’ + v’w’x + uvx

Computer Organization Computer Architectures Lab

Digital Logic Circuits 16 Map Simplification

IMPLEMENTATION OF K-MAPS - Sum-of-Products Form -

Logic function represented by a Karnaugh map

can be implemented in the form of I-AND-OR

A cell or a collection of the adjacent 1-cells can

be realized by an AND gate, with some inversion of the input variables.
y
x’
1 1 y
x’ z’
y’ x’
z’ x 1  y
x z’ 1 1
z y z’
z’ 1
F(x,y,z) =  (0,2,6)

x’
y’ x
z’
x’  z
y F F
z’ y
x
y z
z’
I AND OR

Computer Organization Computer Architectures Lab

Digital Logic Circuits 17 Map Simplification

IMPLEMENTATION OF K-MAPS - Product-of-Sums Form -

Logic function represented by a Karnaugh map

can be implemented in the form of I-OR-AND

If we implement a Karnaugh map using 0-cells,

the complement of F, i.e., F’, can be obtained.
Thus, by complementing F’ using DeMorgan’s
theorem F can be obtained

F(x,y,z) = (0,2,6) y
F’ = xy’ + z
1 0 0 1 z
x 0 0 0 1 F = (xy’)z’
= (x’ + y)z’
x z
y’

x
y
F
z

I OR AND

Computer Organization Computer Architectures Lab

Digital Logic Circuits 18 Map Simplification
IMPLEMENTATION OF K-MAPS
- Don’t-Care Conditions -
In some logic circuits, the output responses
for some input conditions are don’t care
whether they are 1 or 0.

In K-maps, don’t-care conditions are represented

by d’s in the corresponding cells.

Don’t-care conditions are useful in minimizing

the logic functions using K-map.
- Can be considered either 1 or 0
- Thus increases the chances of merging cells into the larger cells
--> Reduce the number of variables in the product terms
y x’
1 d d 1
x d 1
z yz’

x
F
y
z
Computer Organization Computer Architectures Lab
Digital Logic Circuits 19 Combinational Logic Circuits

COMBINATIONAL LOGIC CIRCUITS

y y
Half Adder x y c s x
0 0 0 0 0 0 0 1 c
y
0 1 0 1 x 0 1 x 1 0
1 0 0 1 c = xy s = xy’ + x’y s
1 1 1 0 =x  y
Full Adder
y y
x y cn-1 cn s
0 0 0 0 0 0 0 0 1
0 0 1 0 1 0 1 c 1 0 c
n-1 n-1
0 1 0 0 1 x 1 1 x 0 1
0 1 1 1 0 0 1 1 0
1 0 0 0 1 cn s
1 0 1 1 0
1 1 0 1 0 cn = xy + xcn-1+ ycn-1
1 1 1 1 1 = xy + (x  y)cn-1
s = x’y’cn-1+x’yc’n-1+xy’c’n-1+xycn-1
= x  y  cn-1 = (x  y)  cn-1
x
y S
cn-1
cn

Computer Organization Computer Architectures Lab

Digital Logic Circuits 20 Combinational Logic Circuits

COMBINATIONAL LOGIC CIRCUITS

Other Combinational Circuits

Multiplexer
Encoder
Decoder
Parity Checker
Parity Generator
etc

Computer Organization Computer Architectures Lab

Digital Logic Circuits 21 Combinational Logic Circuits

MULTIPLEXER

4-to-1 Multiplexer
Select Output
S1 S0 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3

I0

I1
Y
I2

I3

S0
S1

Computer Organization Computer Architectures Lab

Digital Logic Circuits 22 Combinational Logic Circuits

ENCODER/DECODER

Octal-to-Binary Encoder
D1 A0
D2
D3 A1
D4
D5 A2
D6
D7

2-to-4 Decoder
D0

E A1 A0 D0 D1 D2 D3 A0 D1
0 0 0 0 1 1 1
0 0 1 1 0 1 1 D2
0 1 0 1 1 0 1
0 1 1 1 1 1 0
1 d d 1 1 1 1 A1 D3
E

Computer Organization Computer Architectures Lab

Digital Logic Circuits 23 Flip Flops

FLIP FLOPS
Characteristics
- 2 stable states
- Memory capability
- Operation is specified by a Characteristic Table
1 0 0 1

0 1 1 0
0-state 1-state
In order to be used in the computer circuits, state of the flip flop should
have input terminals and output terminals so that it can be set to a certain
state, and its state can be read externally.

R S R Q(t+1)
Q 0 0 Q(t)
0 1 0
1 0 1
S Q’ 1 1 indeterminate
(forbidden)

Computer Organization Computer Architectures Lab

Digital Logic Circuits 24 Flip Flops

CLOCKED FLIP FLOPS

In a large digital system with many flip flops, operations of individual flip flops
are required to be synchronized to a clock pulse. Otherwise,
the operations of the system may be unpredictable.
R
Q

c
(clock)
S Q’

Clock pulse allows the flip flop to change state only

when there is a clock pulse appearing at the c terminal.

We call above flip flop a Clocked RS Latch, and symbolically as

S Q S Q
c c
R Q’ R Q’
operates when operates when
clock is high clock is low

Computer Organization Computer Architectures Lab

Digital Logic Circuits 25 Flip Flops

RS-LATCH WITH PRESET AND CLEAR INPUTS

P(preset)
R Q
c
(clock)
S Q’

clr(clear)

S P Q S P Q
c c
R clr Q’ R clr Q’

S P Q S P Q
c c
R clr Q’ R clr Q’

Computer Organization Computer Architectures Lab

Digital Logic Circuits 26 Flip Flops

D-LATCH

D-Latch
Forbidden input values are forced not to occur
by using an inverter between the inputs

D Q
Q

E E Q’
(enable)
Q’ D Q
D(data)

D Q(t+1) E Q’
0 0
1 1

Computer Organization Computer Architectures Lab

Digital Logic Circuits 27 Flip Flops

EDGE-TRIGGERED FLIP FLOPS

Characteristics
- State transition occurs at the rising edge or
falling edge of the clock pulse

Latches

respond to the input only during these periods

Edge-triggered Flip Flops (positive)

respond to the input only at this time

Computer Organization Computer Architectures Lab

Digital Logic Circuits 28 Flip Flops

POSITIVE EDGE-TRIGGERED
D-Flip Flop
D S1 Q1 S2 Q2 Q D Q
SR1 SR2
C1 C2 D-FF
R1 Q1' R2 Q2' Q' C Q'
C

SR1 inactive
SR2 active
SR2 inactive SR2 inactive
SR1 active SR1 active
JK-Flip Flop

J S1 Q1 S2 Q2 Q J Q
SR1 SR2
C1 C2 C
K R1 Q1' R2 Q2' Q' K Q'
C

T-Flip Flop: JK-Flip Flop whose J and K inputs are tied together to make
T input. Toggles whenever there is a pulse on T input.
Computer Organization Computer Architectures Lab
Digital Logic Circuits 29 Flip Flops

CLOCK PERIOD
Clock period determines how fast the digital circuit operates.
How can we determine the clock period ?

Usually, digital circuits are sequential circuits which has some flip flops

FF FF ... FF
C
Combinational .
.
. Logic .
. Circuit .

Combinational
FF Logic FF
Circuit
FF Setup Time
FF Delay Combinational logic Delay FF Hold Time
td
ts,th
clock period T = td + ts + th
Computer Organization Computer Architectures Lab
Digital Logic Circuits 30 Sequential Circuits

DESIGN EXAMPLE
Design Procedure:
Specification  State Diagram  State Table 
Excitation Table  Karnaugh Map  Circuit Diagram
Example: 2-bit Counter -> 2 FF's
x=0 current next
state input state FF inputs
00 A B x A B Ja Ka Jb Kb
x=1 x=1 0 0 0 0 0 0 d 0 d
0 0 1 0 1 0 d 1 d
x=0 01 11 x=0 0 1 0 0 1 0 d d 0
0 1 1 1 0 1 d d 1
x=1 1 0 0 1 0 d 0 0 d
x=1 1 0 1 1 1 d 0 1 d
10 1 1 0 1 1 d 0 d 0
x=0 1 1 1 0 0 d 1 d 1

B B B B
d d d d
1 d d x 1 d x d 1 x
x x
d d 1
A A A 1 d A
d 1 J Q A J Q B
d d d d C C
Ja Ka Jb Kb K Q' K Q'
clock
Ja = Bx Ka = Bx Jb = x Kb = x

Computer Organization Computer Architectures Lab

Digital Logic Circuits 31 Sequential Circuits

SEQUENTIAL CIRCUITS - Registers

A0 A1 A2 A3
Q Q Q Q
D C D C D C D C

Clock
I0 I1 I2 I3
Shift Registers
Serial Serial
D Q D Q D Q D Q Output
Input C C C C
Clock

Bidirectional Shift Register with Parallel Load

A0 A1 A2 A3

Q Q Q Q
D C D C D C D C

4x1 4x1 4x1 4x1

MUX MUX MUX MUX

Clock S0S1 SeriaI I0 I1 I2 Serial I3

Input Input
Computer Organization Computer Architectures Lab
Digital Logic Circuits 32 Sequential Circuits

SEQUENTIUAL CIRCUITS - Counters

A0 A1 A2 A3

Q Q Q Q
J K J K J K J K
Clock

Counter
Enable

Output
Carry

Computer Organization Computer Architectures Lab

Digital Logic Circuits 33 Memory Components

MEMORY COMPONENTS
0
Logical Organization

words
(byte, or n bytes)

N-1
Random Access Memory

- Each word has a unique address

- Access to a word requires the same time
independent of the location of the word
- Organization
n data input lines

k address lines
2k Words
Read (n bits/word)

Write

n data output lines

Computer Organization Computer Architectures Lab

Digital Logic Circuits 34 Memory Components

READ ONLY MEMORY(ROM)

Characteristics
- Perform read operation only, write operation is not possible
- Information stored in a ROM is made permanent
during production, and cannot be changed
- Organization k address input lines

m x n ROM
(m=2k)

n data output lines

Information on the data output line depends only
on the information on the address input lines.
--> Combinational Logic Circuit address Output
X0=A’B’ + B’C ABC X0 X1 X2 X3 X4
X1=A’B’C + A’BC’ 000 1 0 0 0 0
X2=BC + AB’C’
X3=A’BC’ + AB’
001 1 1 0 0 0
X4=AB 010 0 1 0 1 0
011 0 0 1 0 0
X0=A’B’C’ + A’B’C + AB’C 100 0 0 1 1 0
X1=A’B’C + A’BC’ 101 1 0 0 1 0
X2=A’BC + AB’C’ + ABC 110 0 0 0 0 1
Canonical minterms X3=A’BC’ + AB’C’ + AB’C 111 0 0 1 0 1
X4=ABC’ + ABC
Computer Organization Computer Architectures Lab
Digital Logic Circuits 35 Memory Components

TYPES OF ROM

ROM
- Store information (function) during production
- Mask is used in the production process
- Unalterable
- Low cost for large quantity production --> used in the final products

PROM (Programmable ROM)

- Store info electrically using PROM programmer at the user’s site
- Unalterable
- Higher cost than ROM -> used in the system development phase
-> Can be used in small quantity system

EPROM (Erasable PROM)

- Store info electrically using PROM programmer at the user’s site
- Stored info is erasable (alterable) using UV light (electrically in
some devices) and rewriteable
- Higher cost than PROM but reusable --> used in the system
development phase. Not used in the system production
due to eras ability

Computer Organization Computer Architectures Lab

Digital Logic Circuits 36 Memory Components

INTEGRATED CIRCUITS

Classification by the Circuit Density

SSI - several (less than 10) independent gates
MSI - 10 to 200 gates; Perform elementary digital functions;
Decoder, adder, register, parity checker, etc
LSI - 200 to few thousand gates; Digital subsystem
Processor, memory, etc
VLSI - Thousands of gates; Digital system
Microprocessor, memory module
Classification by Technology
TTL - Transistor-Transistor Logic
Bipolar transistors
NAND
ECL - Emitter-coupled Logic
Bipolar transistor
NOR
MOS - Metal-Oxide Semiconductor
Unipolar transistor
High density
CMOS - Complementary MOS
Low power consumption

Computer Organization Computer Architectures Lab