Sequential Circuits

Module –III: Sequential Circuits

Basic Flip-flop & Latch [1L],

Flip-flops -SR, JK, D, T, Master Slave Flip Flops [3L]

Registers (SISO,SIPO,PIPO,PISO) [2L],

Ring counter, Johnson counter [1L],

Basic concept of Synchronous and Asynchronous counters (detail
design of circuits excluded)[2L],

Design of Mod N Counter [2L]

Latch

The circuit just

settles to some
arbitrary state.

There is no
provision to set
some state
Latch
SR Latch using NOR Gate
SR Latch using NOR Gate
0
If S= 1, R=0 then
as one input of NOR gate 2 is 1, the
output Q’ will be 0

Q’= 0 is fed to NOR gate 1.

Now, R = 0 1
as both inputs of NOR Gate are 0,
Output Q will be 1.
SR Latch using NOR Gate
0
If S= 1, R=0 then
as one input of NOR gate 2 is 1, the
output Q’ will be 0

Q’= 0 is fed to NOR gate 1. 0

Now, R = 0 1
as both inputs of NOR Gate are 0,
Output Q will be 1.
SR Latch using NOR Gate
0
If S= 1, R=0 then
as one input of NOR gate 2 is 1, the 0
output Q’ will be 0

Q’= 0 is fed to NOR gate 1. 0

Now, R = 0 1
as both inputs of NOR Gate are 0,
Output Q will be 1.
SR Latch using NOR Gate
0
If S= 1, R=0 then 1
as one input of NOR gate 2 is 1, the 0
output Q’ will be 0

Q’= 0 is fed to NOR gate 1. 0

Now, R = 0 1
as both inputs of NOR Gate are 0,
Output Q will be 1.
SR Latch using NOR Gate
0
If S= 1, R=0 then 1
as one input of NOR gate 2 is 1, the 0
output Q’ will be 0
1
Q’= 0 is fed to NOR gate 1. 0
Now, R = 0 1
as both inputs of NOR Gate are 0,
Output Q will be 1.
SR Latch using NOR Gate

If S= 0, R=1 then
As one input of NOR gate 1 is 1, the
output Q will be 0

Q = 0 is fed to NOR gate 2

Now, S = 0.
As both inputs of NOR Gate 2 are 0,
Output Q’ will be 1.
SR Latch using NOR Gate
If S= 0, R=0 then
Suppose Q= 1 , Q’=0
Q’= 0 will be fed to one input of
NOR gate 1.
So, both inputs of NOR Gate 1 is 0.
Therefore, Q=1;

Q = 1 will be fed to one input of

NOR gate 2
SR Latch using NOR Gate
If S= 1, R=1 then
Suppose Q= 1 , Q’=0
Q’= 0 will be fed to one input of
NOR gate 1.
So, both inputs of NOR Gate 1 is 1.
Therefore, Q=0;

Q = 0 will be fed to one input of

NOR gate 2,
SR Latch using NOR Gate
If S= 1, R=1 then (Continued)

both Q and Q’ will be 0

🡪 Violates rule that Q’ and Q are

complementary to each other.
SR Latch using NAND Gate
SR Latch using NAND Gate

0
SR Latch using NAND Gate

0 1

0 1
SR Latch using NAND Gate

1
SR Latch using NAND Gate

0 1

1 0
SR Latch using NAND Gate

1
0
1
0
1
0
SR Latch using NAND Gate
One can convert an S’R’ latch to an SR latch
by using two NAND gates . 1 and 2
One can convert an S’R’ latch to an SR latch
by using two NAND gates . 1 and 2
State Transition Diagram
 SR Flip Flop

Extra enabling signal

 Clocked NOR Based SR Flip Flop

R and S will pass through only when CLK=1

 NAND Based SR Latch

0
 Clocked NAND Based SR Flip Flop

If CLK=0, both inputs, 9 and

12 become 1

0 So, Action is “No change”

Clocked NAND Based SR Flip Flop
 Clocked NAND Based SR Flip Flop

1
If CLK=0, both inputs, 9 and
12 become 1

0 So, Action is “No change”

1
 Clocked NAND Based SR Flip Flop
1
0 If CLK=1,

3 will be complement of 1 (S)

1 6 will be complement of 5 (R)

1
0
 Clocked NAND Based SR Flip Flop
1
If CLK=1,

3 will be complement of 1 (S)

1 6 will be complement of 5 (R)

1
 Clocked NAND Based SR Flip Flop
1
0 If CLK=1,

3 will be complement of 1 (S)

1 6 will be complement of 5 (R)

FORBIDDEN STATE
0
1
Don’t care
combinations are not
considered because
they correspond to
invalid input
conditions
A B C D E F
A B C D E F G H I
D(Delay) Flip Flop
Output depends only on D, irrespective of
previous state
Similar to S-R Flip-Flop except that indeterminate
condition is allowed in it.

J and K behave same as S and R.

For J =1 , K= 1 the Flip-Flop output toggles.

Case I

J=0, K = 0

0
0
Case I

J=0, K = 0

Output of 1 is 0
Irrespective of Q’ 0 0
i.e., S =0

Output of 2 is 0
Irrespective of Q
0 0
i.e., R=0

🡪 No change
Case II: J=0, K = 1
Consider both cases, i.e., Q=0 and Q=1

0
1
Case II: J=0, K = 1
Consider both cases, i.e., Q=0 and Q=1
Since J=0
Output of 1 is 0
Irrespective of Q’
i.e., S=0
0 0 0
Since K=1
If Q=0 then
Output of 2 is 0 1 0 1
i.e., R =0
🡪 No change
Case II: J=0, K = 1
Consider both cases, i.e., Q=0 and Q=1
Since J=0
Output of 1 is 0
Irrespective of Q’
i.e., S=0
0 0 1
Since K=1
If Q=0 then
Output of 2 is 0 1 1 0
i.e., R =0
🡪 No change

If Q=1 then
Output of 2 is 1
i.e., R =1
🡪 Reset
Case II: J=0, K = 1
Consider both cases, i.e., Q=0 and Q=1
Since J=0
Output of 1 is 0
Irrespective of Q’
i.e., S=0
0 0 0
Since K=1
If Q=0 then
Output of 2 is 0 1 1 1
i.e., R =0
🡪 No change

If Q=1 then
Output of 2 is 1
i.e., R =1
🡪 Reset
Case II: J=0, K = 1
Consider both cases, i.e., Q=0 and Q=1
Since J=0
Output of 1 is 0
Irrespective of Q’
i.e., S=0
0 0 0
Since K=1
If Q=0 then
Output of 2 is 0 1 0 1
i.e., R =0
🡪 No change

If Q=1 then
Output of 2 is 1
i.e., R =1 Now S=0 and R=0; So there output will
🡪 Reset be latched
Case III: J=1, K = 1, Q=1, Q’=0
Set condition Consider both cases, i.e., Q=0 and Q=1

Since J=1, Q’=0

Output of 1 is 0
i.e., S=0
1 0 1
Since K=1, Q=1
Output of 2 is 1 1 0
i.e., R=1 1
🡪 Reset
(Q=0, Q’=1)
Case III: J=1, K = 1, Q=1, Q’=0
Set condition Consider both cases, i.e., Q=0 and Q=1

Since J=1, Q’=0

Output of 1 is 0
i.e., S=0
1 0 0
Since K=1, Q=1
Output of 2 is 1 1 1
i.e., R=1 1
🡪 Reset
(Q=0, Q’=1)
Case III: J=1, K = 1, Q=0, Q’=1
Consider both cases, i.e., Q=0 and Q=1
Reset condition

Since J=1, Q’=1

1 1 0
Output of 1 is 1
i.e., S=1
0 1
Since K=1, Q=0 1
Output of 2 is 0
i.e., R=0

🡪 Set
(Q=1, Q’=0)
Case III: J=1, K = 1, Q=0, Q’=1
Consider both cases, i.e., Q=0 and Q=1
Reset condition

Since J=1, Q’=1

1 1 1
Output of 1 is 1
i.e., S=1
0 0
Since K=1, Q=0 1
Output of 2 is 0
i.e., R=0

🡪 Set
(Q=1, Q’=0)
J-K Flip Flop Toggles when
J=1, K=1
Toggle/Trigger
 Race Around Condition In JK Flip-flop

For J-K flip-flop, if J=K=1, and if clk=1 for a

long period of time, then Q output will toggle
as long as CLK is high, which makes the
output of the flip-flop at the end of the clock
pulse unstable or uncertain.

This problem is called race around condition in

J-K flip-flop.

Section C
Flip-Flops are synchronous bistable devices.

Synchronous: Changes in the output occur at a specified point

on a triggering input called the clock.

Based on specified interval or point, there are two categories:

Goes from 0 to 1
Stays for an interval
Comes down from 1 to 0

Consideration:
The time duration, the interval
of the application of a pulse
until the output transition occurs
Flip-flop changes state when the clock has changed level.

Positive level: Flip-flop changes its state when clock is positive

 0 : negative level: Flip-flop changes its state when
clock is negative

if a NOT gate is introduced in

between the clock and the AND
gate in S-R Flip-flop
Race Around Condition In JK Flip-flop
Avoids race around condition
Avoids race around condition
Avoids race around condition
Negative clock pulse is fed to the Slave
Counters
Counters
 Counters

Q0 toggles with down clock pulse

 Counters

Q1 toggles with down Q0

Counters
 Counters

Q2 toggles with down Q1

Counters
Counters
Asynchronous Counters
(Ripple Counters)
4-bit Binary Ripple Counters
4-bit Binary Ripple Counters
4-bit Binary Ripple Counters
Say, the clock frequency is f0.

QA changes only when the clock makes a transition from 1 to 0

Thus, at the first negative transition of the clock, QA becomes 1.

At the second negative transition of the clock, QA becomes 0.
Hence the frequency of QA is f0/2

The negative transition of QA becomes clock of QB and drives it from 0 to 1

Hence the frequency of QB is f0/4
Like wise, the frequency of QC is f0/8 and the frequency of QD is f16

If n flip-flops are used, the frequency will be divided by 2n.

 By skipping steps

110 means QA = 0, QB=1, QC=1

Synchronous Counter
 Synchronous Counter

Disadvantage
 Synchronous Counter

Simultaneous clock pluses

to all the flip-flops

Vcc is applied to J and K inputs of the left most flip-flop

The J and K inputs of other flip-flops have been taken from the ANDed outputs of the
previous ones.
Synchronous Counter
Truth Table
 Synchronous Counter

Independent of the number of bits

 Synchronous Counter

Disadvantage
This is with parallel carry.

Number of AND gates increases with the number of bits.

The number of inputs to an AND gate also increases.
Number of flip-flops, required is given by the equation

N=number of states. n=number of flip-flops

For Mod-3 counter, N=3. So, n=2

Design with J-K flip-flops will be simplest
Excitation maps
Excitation maps
Using the inverted
outputs of flip-flops
to feed the logic
gates
Registers
 Registers
A type of sequential circuit

Building block used in ALU (add, move, PC, etc.) and

memory.

Has generally no specific sequence of states, unlike a

counter.

A counter gives count, a register does not.

Registers capable of shifting binary information left or right.

Shift-in from one direction

Shift-out from the other direction.

Serial shifting 🡪 one bit at a time with clock pulse transition

Parallel shifting 🡪 all bits simultaneously with clock transition
 Entry of 1101 from the
left.

LSB first

Entry of 1111 from the

left.

LSB first
 Supplementary Questions
How JK Flip Flop can be used to divide frequency.
 Supplementary Questions
Consider the circuit given below with intial state Q0=1, Q1=Q2=0. The state
of the circuit is given by the value 4Q+ 2Q1+Q0. Write the full correct
sequence of the circuit.
 Supplementary Questions
Consider the circuit given below with initial state Q0=1, Q1=Q2=0. The state
of the circuit is given by the value 4Q+ 2Q1+Q0. Write the full correct
sequence of the circuit.
 Supplementary Questions

Ans: 1
 Supplementary Questions

Ans: 1-2
 Supplementary Questions

Ans: 1-2-5
 Supplementary Questions

Ans: 1-2-5-3-7-6-4-1
 Supplementary Questions
Consider the circuit shown below. The output of a 2:1 Mux is given by the function
(ac’+bc). Give the expression for f.
 Supplementary Questions
Consider the circuit shown below. The output of a 2:1 Mux is given by the function
(ac’+bc). Give the expression for f.

g=X1’

f= X2’X1’+X2X1
 Supplementary Questions
Given the following Karnaugh map, find the minimal Sum of Products
 Supplementary Questions
Given the following Karnaugh map, find the minimal Sum of Products
 Supplementary Questions
Given the following Karnaugh map, find the minimal Sum of Products

Y’Z +YX
 Supplementary Questions

How many pulses are needed to change the content of an eight bit up counter
from 10101100 to 00100111 (right most bit is the MSB)
 Supplementary Questions

How many pulses are needed to change the content of an eight bit up counter
from 10101100 to 00100111 (right most bit is the MSB)

(a) 134 (b) 133 (c) 124 (d) 123

 Supplementary Questions

How many pulses are needed to change the content of an eight bit up counter
from 10101100 to 00100111 (right most bit is the LSB)

(a) 134 (b) 133 (c) 124 (d) 123

172 to 255
255 to 0
0 to 39
Supplementary Questions
Supplementary Questions
Supplementary Questions
Supplementary Questions
 Supplementary Questions

What is the value of 0011111000

76543210

2^7+2^6+2^5+2^4+2^3=128+64+32+16+8=
40+80+128=120+128=248

In another way

2^(7+1) – 2^3 = 2^8 – 2^3 = 256-8=248

Supplementary Questions
 Supplementary Questions

Using Booth’s algorithm for multiplication, the multiplier

-57 will be recorded as
 Supplementary Questions

Using Booth’s algorithm for multiplication, the multiplier

-57 will be recorded in 8 bits as

Answer:

57 decimal = 00111001 = 1+8+16+32

1’s complement = 11000110;

2’s complement = 11000111
-57 decimal = 2’s complement = 11000111
Supplementary Questions
Supplementary Questions
Supplementary Questions
 Supplementary Questions

Explain the operation of the following

Latch

The circuit just

settles to some
arbitrary state.

There is no
provision to set
some state
Supplementary Questions
Supplementary Questions
Supplementary Questions
Supplementary Questions

G
Supplementary Questions
Supplementary Questions