Microprocessors and Peripheral

Devices – Module II
Subject Code:CS210A3
Semester: IV; Branch: CSE
Book Reference:

1. Microprocessors and Microcomputer-Based System Design by MOHAMED RAFIQ

QUZZAMAN
2. The 8088 and 8086 Microprocessors: Programming, Interfacing, Software, Hardware, and
Applications, by Walter A. Triebel and Avtar Singh.

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 Module II - 8086 Microprocessor
Introduction The 8086 is a 16-bit microprocessor intended to be used as the CPU in a microcomputer. The
term “16-bit” means that its arithmetic logic unit, internal registers, and most of its instructions are designed
to work 16-bit binary words. It has 16-bit data bus and 20-bit address bus.

Words will be stored in two consecutive memory locations. If the first byte of a word is at an even address,
the 8086 can read the entire word in one operation. If the first byte of the word is at an odd address, the 8086
will read the first byte in one operation, and the second byte in another operation.

Features

➢ 8086 is a 40 pin IC.

➢ It is a 16-bit processor.
➢ Its operating voltage is 5 volts.
➢ Its operating frequency is 5 MHz
➢ The total memory addressing capacity is 1MB (external).
➢ It has 16-bit data bus and 20-bit address bus.
➢ It has fourteen 16-bit registers.
➢ It has around 20000 transistors in its circuitry and it is made in HMOS technology.
➢ Pipelining improves the performance of the processor so that operation is faster.8086 uses two stage
of pipelining.
➢ First is Fetch Stage and the second is Execute Stage.
➢ Fetch stage that prefetch upto 6 bytes of instructions stores them in the queue.
➢ Execute stage that executes these instructions.
➢ Operates in two modes: 8086 operates in two modes:
Minimum Mode: A system with only one microprocessor. Maximum Mode: A system
with multiprocessor.
➢ 8086 uses memory banks: The 8086 uses a memory banking system. It means entire data is
not stored sequentially in a single memory of 1 MB but memory is divided into two banks
of 512KB.
➢ Interrupts:8086 has 256 vectored interrupts.
➢ Multiplication and Division:8086 has a powerful instruction set. So that it supports
Multiply and Divide operation.

Pin Diagram
The 8086 signals can be categorized in three groups. The first are the signals having common
functions in minimum as well as maximum mode, the second are the signals which have special
functions in minimum mode and third are the signals having special functions for maximum mode
The following signal description are common for both the minimum and maximum modes.

AD15-AD0 These are the time multiplexed memory I/O address and data lines. Address remains
on the lines during T1 state, while the data is available on the data bus during T2, T3, TW and T4.
Here T1, T2, T3, T4 and TW are the clock states of a machine cycle. TW is a wait state. These
lines are active high and float to a tristate during interrupt acknowledge and local bus hold
acknowledge cycles.
Fig. Pin Diagram

A19/S6, A18/S5, A17/S4, A16/S3: These are the time multiplexed address and status lines.
During T1, these are the most significant address lines or memory operations. During I/O
operations, these lines are low. During memory or I/O operations, status information is
available on those lines for T2, T3, TW and T4. The status of the interrupt enable flag
bit(displayed on S5) is updated at the beginning of each clock cycle. The S4 and S3
combined, indicate which segment register is presently being used for memory accesses as
shown in the following table. These lines float to tri-state off during the local bus hold
acknowledge. The status line S6 is always low(logical). The address bits are separated
from the status bits using latches controlled by the ALE signal.

Table Segment Register Indication

S4 S3 Indication
0 0 Alternate
data
0 1 Stack
1 0 Code or
none
1 1 Data
BHE/S7-Bus High Enable/Status: The bus high enable signal is used to indicate the transfer of
data over the higher order (D15-D8) data bus as shown in the following table. It goes low for the
data transfers over D15-D8 and is used to derive chip selects of odd address memory bank or
peripherals. BHE is low during T1 for read, write and interrupt acknowledge cycles, when- ever a
byte is to be transferred on the higher byte of the data bus. The status information is available
during T2, T3 and T4. The signal is active low and is high-impedance state during 'hold'. It is low
during T1 for the first pulse of the interrupt acknowledge cycle.

BHE S7 Indication
0 0 Whole word
0 1 Upper byte
from or to
odd address
1 0 Upper byte
from or to
even address
1 1 None

Table Bus High Enable Indication

RD-Read: Read signal, when low, indicates the peripherals that the processor is performing a memory or
I/O read operation. RD is active low and shows the state for T2, T3, TW of any read cycle. The signal
remains in high impedance during the 'hold acknowledge'.

Ready: This is the acknowledgement from the slow devices or memory that they have completed
the data transfer. The signal made available by the devices is synchronized by the 8284A clock
generator to provide ready input to the 8086. The signal is active high.

INTR-interrupt Request: This is a level triggered input. This is sampled during the last clock
cycle of each instruction to determine the availability of the request. If any interrupt request is
pending, the processor enters the interrupt acknowledge cycle. This can be internally masked by
resetting the interrupt enable flag. This signal is active high and internally synchronized.

TEST: This input is examined by a 'WAIT' instruction. If the TEST input goes low, execution will
continue, else, the processor remains in an idle state. The input is synchronized internally during
each clock cycle on leading edge of clock.

NMI-Non-maskable Interrupt: This is an edge-triggered input which causes a Type2 interrupt.

The NMI is not maskable internally by software. A transition from low to high initiates the
interrupt response at the end of the current instruction. This input is internally synchronized.

Reset: This input causes the processor to terminate the current activity and start execution from
FFFF0H. The signal is active high and must be active for at least four clock cycles. It restarts
execution when the RESET returns low. RESET is also internally synchronized.

CLK-Clock Input: The clock input provides the basic timing for processor operation and bus
control activity. It’s an asymmetric square wave with 33% duty cycle. The range of frequency for
different 8086 versions is from 5MHz to 10MHz.

VCC: +5V power supply for the operation of the internal circuit. GND ground for the internal
circuit.
MN/MX: The logic level at this pin decides whether the processor is to operate in either minimum (single
processor) or maximum (multiprocessor) mode.

The following pin functions are for the minimum mode operation of 8086.

M/IO -Memory/IO: This is a status line logically equivalent to S2 in maximum mode. When it is low, it
indicates the CPU is having an I/O operation, and when it is high, it indicates that the CPU is having a
memory operation. This line becomes active in the previous T4 and remains active till final T4 of the current
cycle. It is in high-impedance state during local bus "hold acknowledge".

INTA -Interrupt Acknowledge: This signal is used as a read strobe for interrupt acknowledge cycles. In
other words, when it goes low, it means that the processor has accepted the interrupt. It is active low during
T2, T3 and TW of each interrupt acknowledge cycle.

ALE-Address latch Enable: This output signal indicates the availability of the valid address on the
address/data lines and is connected to latch enable input of latches. This signal is active high and is never in
high-impedance state.

DT /R -Data Transmit/Receive: This output is used to decide the direction of data flow through the
transceivers (bidirectional buffers). When the processor sends out data, this signal is high and when the
processor is receiving data, this signal is low. Logically, this is equivalent to S1 in maximum mode. Its
timing is the same as M/I/O.

DEN-Data Enable This signal indicates the availability of valid data over the address/data lines. It is used
to enable the transceivers (bidirectional buffers) to separate the data from the multiplexed address/data
signal. It is active from the middle of T2 until the middle of T4 DEN is in high-impedance state during 'hold
acknowledge' cycle.

HOLD, HLDA-Hold/Hold Acknowledge: When the HOLD line goes high, it indicates to the processor that
another master is requesting the bus access. The processor, after receiving the HOLD request, issues the
hold acknowledge signal on HLDA pin, in the middle of the next clock cycle after completing the current
bus (instruction) cycle. At the same time, the processor floats the local bus and control lines. When the
processor detects the HOLD line low, it lowers the HLDA signal. HOLD is an asynchronous input, and it
should be externally synchronized. If the DMA request is made while the CPU is performing a memory or
I/O cycle, it will release the local bus during T 4 provided:

1. The request occurs on or before T 2 state of the current cycle.

2. The current cycle is not operating over the lower byte of a word (or operating on an odd address).
3. The current cycle is not the first acknowledge of an interrupt acknowledge sequence.
4. A Lock instruction is not being executed.

The following pin functions are applicable for maximum mode operation of 8086.

S2, S1, S0 -Status Lines: These are the status lines which reflect the type of operation, being carried out by
the processor. These become active during T4 of the previous cycle and remain active during T1 and T2 of
the current bus cycle. The status lines return to passive state during T3 of the current bus cycle so that they
may again become active for the next bus cycle during T4. Any change in these lines during T3 indicates the
starting of a new cycle and return to passive state indicates end of the bus cycle. These status lines are
encoded in the following table.
S2 S1 S0 Indication
0 0 0 Interrupt
acknowledge
0 0 1 Read I/O port
0 1 0 Write I/O port
0 1 1 Halt
1 0 0 Code access
1 0 1 Read memory
1 1 0 Write memory
1 1 1 Passive

Table: Status Line Indication

Lock: This output pin indicates that other system bus masters will be prevented from gaining the system
bus, while the LOCK signal is low. The LOCK signal is activated by the 'LOCK' prefix instruction and
remains active until the completion of the next instruction. This floats to tri-state off during "hold
acknowledge". When the CPU is executing a critical instruction, which requires the system bus, the LOCK
prefix instruction ensures that other processors connected in the system will not gain the control of the bus.
The 8086, while executing the prefixed instruction, asserts the bus lock signal output, which may be
connected to an external bus controller.
QS1, QS0-Queue Status These lines give information about the status of the code prefetch queue.
These are active during the CLK cycle after which the queue operation is performed. These are
encoded as shown in the following table.

Qs1 Qs0 Indication

0 0 No operation
0 1 First byte of
opcode from the
queue
1 0 Empty queue
1 1 Subsequent byte
from the queue
Table Queue Status Indication

RQ/GT0, RQ/GT1-ReQuest/Grant: These pins are used by other local bus masters, in maximum mode, to
force the processor to release the local bus at the end of the processor's current bus cycle. Each of the pins is
bidirectional with RQ/GT0 having higher priority than RQ/ GT1, RQ/GT pins have internal pull-up resistors
and may be left unconnected. The request! grant sequence is as follows:

1. A pulse one clock wide from another bus master requests the bus access to 8086.

2. During T4 (current) or T1 (next) clock cycle, a pulse one clock wide from 8086 to the requesting
master, indicates that the 8086 has allowed the local bus to float and that it will enter the "hold
acknowledge" state at next clock cycle. The CPU's bus interface unit is likely to be disconnected from the
local bus of the system.

3. A one clock wide pulse from another master indicates to 8086 that the 'hold' request is about to end
and the 8086 may regain control of the local bus at the next clock cycle. Thus, each master-to-master
exchange of the local bus is a sequence of 3 pulses. There must be at least one dead clock cycle after each
bus exchange. The request and grant pulses are active low. For the bus requests those are received while
8086 is performing memory or I/O cycle, the granting of the bus is governed by the rules of HOLD, and
HLDA in minimum mode.
Comparison between 8085 and 8086 Microprocessor:
 Internal Block Diagram
The 8086 CPU is divided into two independent functional parts, the bus interface unit or BIU, and the
execution unit or EU.

The Bus Interface Unit

The BIU handles all data and addresses on the buses for the execution unit such as it sends out addresses,
fetches instructions from memory, reads data from ports and memory as well as writes data to ports and
memory. In BIU there are so many functional groups or parts these are as follows.

Instruction Queue To increase the execution speed, BIU fetches as many as six instruction bytes ahead to
time from memory. The prefetched instruction bytes are held for the EU in a first in first out group of
registers called an instruction queue. When the EU is ready for its next instruction, it simply reads the
instruction from this instruction queue. This is much faster than sending out an address to the system
memory and to send back the next instruction byte. Fetching the next instruction while the current
instruction executes is called pipelining.

Fig Block Diagram

Segment Registers: The BIU contains four 16-bit segment registers. They are: the extra segment (ES)
register, the code segment (CS) registers, the data segment (DS) registers, and the stack segment (SS)
registers. These segment registers are used to hold the upper 16 bits of the starting address for each of the
segments. The part of a segment starting address stored in a segment register is often called the segment
base.

1. Code Segment (CS): The CS register is used for addressing a memory location in the Code Segment of
the memory, where the executable program is stored.
2. Data Segment (DS): The DS contains most data used by program. Data are accessed in the Data Segment
by an offset address or the content of other register that holds the offset address.
3. Stack Segment (SS): SS defined a section of memory to store addresses and data while a subprogram
executes.
4. Extra Segment (ES): ES is additional data segment that is used by some of the string to hold the extra
destination data.

Fig Segment Register

Instruction Pointer (IP) In the BIU, the next register, below the segment register is instruction pointer.
The instruction pointer (IP) holds the 16-bit address of the next code byte within this code segment.

The Execution Unit

The execution unit (EU) tells the BIU where to fetch instructions or data from, decodes instructions, and
executes instructions. The functional parts of the execution unit are control circuitry or system, instruction
decoder, and Arithmetic logic unit (ALU). Control circuitry to perform various internal operations. A
decoder in the EU translates instructions fetched from memory to generate different internal or external
control signals that required performing the operation. The EU has a 16-bit ALU, which can perform
arithmetic operations such as add, subtract etc. and logical operations such as AND, OR, XOR, increment,
decrement etc.

Flag Register A 16-bit flag register is a flip-flop which indicates some condition produced by the execution
of an instruction or controls certain operations of the EU. They are modified automatically by CPU after
mathematical operations. It has 9 flags and they are divided into two categories:
1. Conditional Flags
2. Control Flags
Conditional Flags Conditional flags represent result of last arithmetic or logical instructions.

Carry Flag (CF): This flag will be set to one if the arithmetic operation produces the carry in MSB
position. It is also used in multiple-precision arithmetic.
Auxiliary Flag (AF): If an operation performed in ALU generates a carry/barrow from lower nibble
(i.e. D0 – D3) to upper nibble (i.e. D4 – D7), the AF flag is set i.e. carry given by D3 bit to D4 is AF flag.
This is not a general-purpose flag; it is used internally by the processor to perform Binary to BCD
conversion.
Parity Flag (PF): This flag is used to indicate the parity of result. If lower order 8-bits of the result
contains even number of 1’s, the Parity Flag is set to one and for odd number of 1’s, the Parity Flag is reset
i.e. zero.
Zero Flag (ZF): It is set to one; if the result of arithmetic or logical operation is zero else it is reset.
Sign Flag (SF): In sign magnitude format the sign of number is indicated by MSB bit. If the result of
operation is negative, sign flag is set to one.

Overflow Flag (OF): It occurs when signed numbers are added or subtracted. An OF indicates that the
result has exceeded the capacity of machine.

Control Flags

Control flags are intentionally set or reset to control certain operations of the processor with specific
instructions put in the program from the user. Control flags are as follows:

Trap Flag (TF): It is used for single step control. It allows user to execute one instruction of a
program at a time for debugging. When trap flag is set, program can be run in single step mode.
Interrupt Flag (IF): It is an interrupt enable/disable flag, i.e. used to allow/prohibit the interruption
of a program. If it is set, the maskable interrupt is enabled and if it is reset, the interrupt is disabled.
Direction Flag (DF): It is used in string operation. If it is set, string bytes are accessed from higher
memory address to lower memory address. When it is reset, the string bytes are accessed from lower
memory address to higher memory address.

General Purpose Registers: The EU has eight general purpose registers labelled AH, AL, BH, BL,
CH, CL, DH, and DL. These registers can be used individually for temporary storage of 8-bit data. The AL
register is also called the accumulator. Certain pairs of these general-purpose registers can be used together
to store 16-bit data. The valid register pairs are AH and AL, BH and BL, CH and CL and DH and DL. These
register pairs are referred to the AX, BX, CX, and DX resp.

1. AX Register: For 16-bit operations, AX is called the accumulator register that stores operand for
arithmetic operations.
2. BX Register: This register is mainly used as a base register. It holds the starting base location of a
memory region within a data segment.
3. CX Register: It is defined as a counter. It is primarily used in loop instruction to store loop counter.
4. DX Register: DX register is used to contain I/O port address for I/O instruction.

Stack Pointer Register The stack pointer (SP) register contains the 16-bit offset from the start of the
segment to the memory location where a word was most recently stored on the stack. The memory location
where a word was most recently stored is called the top of stack. Other Pointer and Index Registers The
EU also contains a 16-bit source index (SI) register, base pointer (BP) registers, and Destination Index (DI)
registers. These three registers can be mainly used for temporary storage of 16-bit data just like a general-
purpose register.

Logical and Physical Address

Addresses within a segment can range from address 00000h to address 0FFFFh. This corresponds to the
64K-bytelength of the segment. An address within a segment is called an offset or logical address.

A logical address gives the displacement from the base address of the segment to the desired location within
it, as opposed to its "real" address, which maps directly anywhere into the 1 MByte memory space. This
"real" address is called the physical address.

What is the difference between the physical and the logical address?
The physical address is 20 bits long and corresponds to the actual binary code output by the BIU on the
address bus lines. The logical address is an offset from location 0 of a given segment.

You should also be careful when writing addresses on paper to do so clearly. To specify the logical address
XXXX in the stack segment, use the convention SS:XXXX, which is equal to [SS] * 16 + XXXX.

Logical address is in the form of: Base Address: Offset Offset is the displacement of the memory location
from the starting location of the segment. To calculate the physical address of the memory, BIU uses the
following formula:
Physical Address = Base Address of Segment * 16 + Offset

Example:
The value of Data Segment Register (DS) is 2222H. To convert this 16-bit address into 20-bit, the BIU
appends 0H to the LSB (by multiplying with 16) of the address. After appending, the starting address of the
Data Segment becomes 22220H.
Data at any location has a logical address specified as:2222H: 0016H Where 0016H is the offset, 2222 H is
the value of DS Therefore the physical address:22220H + 0016H: 22236 H
The following table describes the default offset values to the corresponding memory segments.

Some of the advantages of memory segmentation in the 8086 are as follows:

• With the help of memory segmentation, a user is able to work with registers having only 16-bits.
• The data and the user’s code can be stored separately allowing for more flexibility.
• Also due to segmentation the logical address range is from 0000H to FFFFH the code can be loaded
at any location in the memory.

Interrupts of 8086

Interrupts of 8086 Definition: An interrupt is a condition that temporarily stops the execution of
microprocessor to carry put a specific task.
When as interrupt occurs, the processor completes the execution of current instruction and calls a special
interrupt service.
ISR (Interrupt service routine): It is a special program to instruct the microprocessor on how to handle the
interrupt.

Sources of Interrupt:
(i) External Signal
(ii) Special instruction
(iii) Condition produced by the Instruction.
 (i) External signal: An 8086 microprocessor can be interrupted from an externa signal applied to
the NMI pin (or) INTR pin in 8086.This is used for hardware interrupt service.
(ii) Special instruction: 8086 processor uses a special instruction “INT” to execute special program.
(iii) Condition produced by Special instruction: An 8086 processor is interrupted by some
condition by the execution of an instruction. Example: Divide by Zero instruction. At the end of
each instruction, the processor checks if there is any interrupt request produced and flag register.

Types of Interrupts:

Hardware Interrupts:

Hardware interrupts caused by any peripheral device by sending a signal through a specified pin to the
microprocessor.
(i) NMI (Non Maskable Interrupt): It is a single pin non-maskable hardware interrupt which cannot
be disabled. It is a highest priority interrupt. IP(Instruction pointer) is loaded from 00008H.CS
(code Segment) is loaded from 0000AH and it is type 2 interrupt.

(ii) INTR (Interrupt request-Maskable Interrupt): INTR provides a single request, and it is activated
by I/O port. This can be masked or delayed (Maskable interrupt). It is a level triggered interrupt
and can receive any interrupt type. Interrupt flag set to this type.

Software Interrupts:

The software interrupts can be generated by inserting the instruction “INT” within a program. There are 256
software interrupts available in 8086 Microprocessor.
Format: INT Type number
Type ranges from 00 to FFH. Starting address rang from 00000H to 003FFH. These are two-byte
instructions.
8086 Interrupt Vector Table:

Important Software Interrupt:

(i) Type 0 Interrupt: It corresponds to divide by zero. When the quotient from division instruction
is too large,8086 will automatically execute Type 0 interrupt.
(ii) Type 1 Interrupt: Single step execution for debugging the program. In this instruction, the
microprocessor will execute one instruction and wait for further direction.
(iii) Type 2 interrupt: It represents NMI and is used in power failure conditions.
(iv) Type 3 interrupt: It is Break-Point Interrupt. It is used for debugging the program.
(v) Type4 Interrupt: It is a overflow interrupt. It is used to check overflow condition after any
signed arithmetic operation of the system.

Interrupt Priorities:

Interrupts Priority
Divide zero, Int 0……..Int n Highest
NMI Higher
INTR Higher
Single step Interrupt Lowest

Instruction Set of 8086 Microprocessor

The 8086 microprocessor supports 8 types of instructions –

• Data Transfer Instructions

• Arithmetic Instructions
• logical Instructions
 • String Instructions
• Program Execution Transfer Instructions (Branch & Loop Instructions)
• Processor Control Instructions
• Iteration Control Instructions
• Interrupt Instructions

1. DATA TRANSFER INSTRUCTIONS

These instructions are used to transfer the data from the source operand to the destination operand.
Following is the list of instructions under this group –

INSTRUCTION TO TRANSFER A WORD

• MOV − Used to copy the byte or word from the provided source to the provided destination.
• PPUSH − Used to put a word at the top of the stack.
• POP − Used to get a word from the top of the stack to the provided location.
• PUSHA − Used to put all the registers into the stack.
• POPA − Used to get words from the stack to all registers.
• XCHG − Used to exchange the data from two locations.
• XLAT − Used to translate a byte in AL using a table in the memory.

INSTRUCTIONS FOR INPUT AND OUTPUT PORT TRANSFER

• IN − Used to read a byte or word from the provided port to the accumulator.
• OUT − Used to send out a byte or word from the accumulator to the provided port.

INSTRUCTIONS TO TRANSFER THE ADDRESS

• LEA − Used to load the address of operand into the provided register.
• LDS − Used to load DS register and other provided register from the memory
• LES − Used to load ES register and other provided register from the memory.
•
INSTRUCTIONS TO TRANSFER FLAG REGISTERS

• LAHF − Used to load AH with the low byte of the flag register.
• SAHF − Used to store AH register to low byte of the flag register.
• PUSHF − Used to copy the flag register at the top of the stack.
• POPF − Used to copy a word at the top of the stack to the flag register.

1. ARITHMETIC INSTRUCTIONS

These instructions are used to perform arithmetic operations like addition, subtraction, multiplication,
division, etc. Following is the list of instructions under this group –

INSTRUCTIONS TO PERFORM ADDITION

• ADD − Used to add the provided byte to byte/word to word.

• ADC − Used to add with carry.
• INC − Used to increment the provided byte/word by 1.
• AAA − Used to adjust ASCII after addition.
• DAA − Used to adjust the decimal after the addition/subtraction operation.
•
INSTRUCTIONS TO PERFORM SUBTRACTION

• SUB − Used to subtract the byte from byte/word from word.

• SBB − Used to perform subtraction with borrow.
 • DEC − Used to decrement the provided byte/word by 1.
• NPG − Used to negate each bit of the provided byte/word and add 1/2’s
• complement.
• CMP − Used to compare 2 provided byte/word.
• AAS − Used to adjust ASCII codes after subtraction.
• DAS − Used to adjust decimal after subtraction.
•
INSTRUCTION TO PERFORM MULTIPLICATION

• MUL − Used to multiply unsigned byte by byte/word by word.

• IMUL − Used to multiply signed byte by byte/word by word.
• AAM − Used to adjust ASCII codes after multiplication.

INSTRUCTIONS TO PERFORM DIVISION

• DIV − Used to divide the unsigned word by byte or unsigned double word by word.
• IDIV − Used to divide the signed word by byte or signed double word by word.
• AAD − Used to adjust ASCII codes after division.
• CBW − Used to fill the upper byte of the word with the copies of sign bit of the lower byte.
• CWD − Used to fill the upper word of the double word with the sign bit of the lower word.

2. LOGICAL INSTRUCTIONS

These instructions are used to perform operations where data bits are involved, i.e. operations like logical,
shift, etc. Following is the list of instructions under this group –

INSTRUCTIONS TO PERFORM LOGICAL OPERATION

• NOT − Used to invert each bit of a byte or word.

• AND − Used for adding each bit in a byte/word with the corresponding bit in another byte/word.
• OR − Used to multiply each bit in a byte/word with the corresponding bit in another byte/word.
• XOR − Used to perform Exclusive-OR operation over each bit in a byte/word with the
corresponding bit in another byte/word.
• TEST − Used to add operands to update flags, without affecting operands.

INSTRUCTIONS TO PERFORM SHIFT OPERATIONS

• SHL/SAL − Used to shift bits of a byte/word towards left and put zero(S) in LSBs.
• SHR − Used to shift bits of a byte/word towards the right and put zero(S) in MSBs.
• SAR − Used to shift bits of a byte/word towards the right and copy the old MSB
into the new MSB.

INSTRUCTIONS TO PERFORM ROTATE OPERATIONS

• ROL − Used to rotate bits of byte/word towards the left, i.e. MSB to LSB and to Carry Flag
[CF].
• ROR − Used to rotate bits of byte/word towards the right, i.e. LSB to MSB and to Carry Flag
[CF].
• RCR − Used to rotate bits of byte/word towards the right, i.e. LSB to CF and CF to MSB.
• RCL − Used to rotate bits of byte/word towards the left, i.e. MSB to CF and CF to LSB.

3. STRING INSTRUCTIONS
String is a group of bytes/words, and their memory is always allocated in a sequential order. Following is the
list of instructions under this group –

• REP − Used to repeat the given instruction till CX ≠ 0.

• REPE/REPZ − Used to repeat the given instruction until CX = 0 or zero flag ZF = 1.
• REPNE/REPNZ − Used to repeat the given instruction until CX = 0 or zero flag ZF = 1.
• MOVS/MOVSB/MOVSW − Used to move the byte/word from one string to another.
• COMS/COMPSB/COMPSW − Used to compare two string bytes/words.
• INS/INSB/INSW − Used as an input string/byte/word from the I/O port to the provided memory
location.
• OUTS/OUTSB/OUTSW − Used as an output string/byte/word from the provided memory location
to the I/O port.
• SCAS/SCASB/SCASW − Used to scan a string and compare its byte with a byte in AL or string
word with a word in AX.
• LODS/LODSB/LODSW − Used to store the string byte into AL or string word into AX.

4. PROGRAM EXECUTION TRANSFER INSTRUCTIONS (BRANCH AND LOOP

INSTRUCTIONS)

These instructions are used to transfer/branch the instructions during an execution. It includes the following
instructions − Instructions to transfer the instruction during an execution without any condition –

• CALL − Used to call a procedure and save their return address to the stack.
• RET − Used to return from the procedure to the main program.
• JMP − Used to jump to the provided address to proceed to the next instruction.

Instructions to transfer the instruction during an execution with some conditions –

• JA/JNBE − Used to jump if above/not below/equal instruction satisfies.

• JAE/JNB − Used to jump if above/not below instruction satisfies.
• JBE/JNA − Used to jump if below/equal/ not above instruction satisfies.
• JC − Used to jump if carry flag CF = 1
• JE/JZ − Used to jump if equal/zero flag ZF = 1
• JG/JNLE − Used to jump if greater/not less than/equal instruction satisfies.
• JGE/JNL − Used to jump if greater than/equal/not less than instruction satisfies.
• JL/JNGE − Used to jump if less than/not greater than/equal instruction satisfies.
• JLE/JNG − Used to jump if less than/equal/if not greater than instruction satisfies.
• JNC − Used to jump if no carry flag (CF = 0)
• JNE/JNZ − Used to jump if not equal/zero flag ZF = 0
• JNO − Used to jump if no overflow flag OF = 0
• JNP/JPO − Used to jump if not parity/parity odd PF = 0
• JNS − Used to jump if not sign SF = 0
• JO − Used to jump if overflow flag OF = 1
• JP/JPE − Used to jump if parity/parity even PF = 1
• JS − Used to jump if sign flag SF = 1

5. PROCESSOR CONTROL INSTRUCTIONS

These instructions are used to control the processor action by setting/resetting the flag values. Following are
the instructions under this group –

• STC − Used to set carry flag CF to 1

• CLC − Used to clear/reset carry flag CF to 0
 • CMC − Used to put complement at the state of carry flag CF.
• STD − Used to set the direction flag DF to 1
• CLD − Used to clear/reset the direction flag DF to 0
• STI − Used to set the interrupt enable flag to 1, i.e., enable INTR input.
• CLI − Used to clear the interrupt enable flag to 0, i.e., disable INTR input.

6. ITERATION CONTROL INSTRUCTIONS

These instructions are used to execute the given instructions for number of times. Following is the list of
instructions under this group −
• LOOP − Used to loop a group of instructions until the condition satisfies, i.e., CX = 0
• LOOPE/LOOPZ − Used to loop a group of instructions till it satisfies ZF = 1 & CX = 0
• LOOPNE/LOOPNZ − Used to loop a group of instructions till it satisfies ZF = 0 & CX = 0
• JCXZ − Used to jump to the provided address if CX = 0

7. INTERRUPT INSTRUCTIONS

These instructions are used to call the interrupt during program execution.

• INT − Used to interrupt the program during execution and calling service specified.
• INTO − Used to interrupt the program during execution if OF = 1
• IRET − Used to return from interrupt service to the main program.

Addressing Modes of 8086

When 8086 executes an instruction, it performs the specified function on data. These data are called its
operands and may be part of the instruction, reside in one of the internal registers of the microprocessor,
stored at an address in memory or held at an I/O port, to access these different types of operands, the 8086 is
provided with various addressing modes (Data Addressing Modes). The 8086 has 12 addressing modes. The
various 8086 addressing modes can be classified into five groups.
A. Addressing modes for accessing immediate and register data (register and immediate modes).
B. Addressing modes for accessing data in memory (memory modes)
C. Addressing modes for accessing I/O ports (I/O modes)
D. Relative addressing mode.
E. Implied addressing mode.

A.1 Immediate addressing mode

The addressing mode in which the data operand is a part of the instruction itself is known as immediate
addressing mode.
Example
MOV DL, 08H

The 8-bit data (08H) given in the instruction is moved to DL.

(DL)  08H

MOV AX, 0A9FH

The 16-bit data (0A9FH) given in the instruction is moved to AX register.
(AX)  0A9FH

A.2 Register addressing mode:

The operand to be accessed is specified as residing in an internal register of 8086. The table below shows
internal registers, one can be used as a source or destination operand, however only the data registers can be
accessed as either a byte or word.

Table Register with Operand Sizes

The instruction will specify the name of the register which holds the data to be operated by the
instruction. All registers except IP may be used in this mode.

Example:
MOV CL, DH
The content of 8-bit register DH is moved to another 8-bit register CL.
(CL)  (DH)

B.1 Direct addressing mode

The addressing mode in which the effective address of the memory location at which the data operand is
stored is given in the instruction. The effective address (Offset) is just a 16-bit number written directly in
the instruction.

Example: MOV BX, [1354H]

MOV BL, [0400H]

The square brackets around the 1354H denote the contents of the memory location. When executed, this
instruction will copy the contents of the memory location into BX register. This addressing mode is called
direct because the displacement of the operand from the segment base is specified directly in the
instruction.

B.2 Register indirect addressing mode.

This addressing mode allows data to be addressed at any memory location through an offset address held
in any of the following registers: BP, BX, DI & SI.

Example
MOV AX, [BX]; suppose the register BX contains 4895H, then the contents; 4895H are moved to AX
ADD CX, {BX}

B.3 Based addressing mode.

when memory is accessed, PA is computed from BX and DS when the stack is accessed PA is
computed from BP and SS.

Example MOV AL, START [BX]

or MOV AL, [START + BX]

EA: [START] + [BX] PA: [DS] + [EA] The 8-bit content of this memory location is moved to AL.

B.4 Indexed addressing mode.

In this addressing mode, the operand’s offset address is found by adding the contents of SI or DI register
and 8-bit/16-bit displacements. DS and ES are the default segments for index registers SI and DI
respectively. This is the special case of the of register indirect addressing mode.

Example
MOV BX, [SI+16], ADD AL, [DI+16]

B.5 Based Indexed addressing mode.

In this addressing mode, the offset address of the operand is computed by summing the base register to
the contents of an Index register. The default segment registers may be ES or DS

Example:

MOV DX, [BX + SI] MOV DX, [BX][SI]

B.6 String addressing mode.

The string instructions automatically assume SI to point to the first byte or word of the source
operand and DI to point to the first byte or word of the destination operand. The contents of SI and
DI are automatically incremented (by clearing DF to 0 by CLD instruction) to point to the next
byte or word.

Example MOV S BYTE

If [DF] = 0, [DS] = 2000 H, [SI] = 0500, [ES] = 4000, [DI] = 0300 Source address: 20500, assume
it contains 38

PA: [DS] + [SI]

Destination address: [ES] + [DI] = 40300, assume it contains 45

After executing MOV S BYTE,
C. I/O modes

C.1 Direct Mode

Port number is an 8-bit immediate operand. Example: OUT 05H, AL Outputs [AL] to 8-bit port 05 H

C.2 Indirect Mode The port number is taken from DX.

Example 1 INAL, DX If [DX] = 5040 8-bit content by port 5040 is moved into AL.

Example 2 IN AX, DX Inputs 8-bit content of ports 5040 and 5041 into AL and AH respectively.

D. Relative addressing mode.

Example: JNC START

If CY=O, then PC is loaded with current PC contents plus 8-bit signed value of START, otherwise the next
instruction is executed.

E. Implied addressing mode.

Instruction using this mode have no operands.

Example: CLC which clears carry flag to zero. & HLT

Assignment 2: Addressing modes of 8086 Microprocessor