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ELC781 Assignment 2

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20 views1 page

ELC781 Assignment 2

Uploaded by

Omar Amer
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Cairo University Fall Semester 2024 – 2025 Department of Electrical Engineering

Faculty of Engineering ELC 781 Parallel Processing


Professor: Mostafa Abd-El-Barr

Assignments-2 (Due date: Noveber 16, 2024)


1. Contemplate on the advantages and disadvantages of message passing architectures and compare those with the
found in shared memory architectures.
2. Discuss the advantages and disadvantages of using the following interconnection networks in the design of a shared
memory system.
▪ Bus
▪ Crossbar switch
▪ Multistage networks

3. Discuss the conditions that lead to the occurrence of the deadlock problems in multi-computer message passing
systems. Suggest ways to avoid the occurrence of such a problem.

4. Consider a bus-based shared memory multiprocessor system. It is constructed using processors with speed of 10 6
instructions/second, and a bus with a peak bandwidth of 10 5 fetches/second. The caches are designed to support a
hit-rate of 90%.
▪ What is the maximum number of processors that can be supported by this system?
▪ What hit-rate is needed to support a 20-processor system

5. Consider the two tasks T0 and T1 that are executed in parallel on processors P1 and P2, respectively in a shared
memory system. Assume that the print statement is uninterruptible, and A, B, C, D are initialized to 0.
T0 T1
A = 1; C = 3;
B = 2; D = 4;
Print A, D; Print B, C;
Show four different possible outputs of the parallel execution of these two tasks

6. Consider a bus-based shared memory system consisting of three processors. The shared memory is divided into four
blocks x, y, z, w. Each processor has a cache that can fit only one block at any given time. Each block can be in one
of two states: valid (V) or invalid (I). Assume that caches are initially flushed (empty) and that the contents of the
memory are as follows:
Memory block X y z w

Contents 10 30 80 20

Consider the following sequence of memory access events given in order:


1) P1: Read(x), 2) P2: Read(x), 3) P3: Read(x), 4) P1: x = x + 25

5) P1: Read(z), 6) P2: Read(x), 7) P3: x = 15, 8) P1: z= z + 1.

You are required to show the contents of the caches and memory and the state of cache blocks after each of the
above operations in the following cases: 1) write-through & write-invalidate and 2) write-back & write-invalidate.

Good Luck
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