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Arrays in Verilog 1690008267

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16 views5 pages

Arrays in Verilog 1690008267

Uploaded by

sricharan
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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ARRAYS IN VERILOG

MEMORIES

1) Memories allocated in compilation time (Verilog)


 PACKED ARRAY
 UNPACKED ARRAY
(Multidimensional array)
2) Memory allocated during Run time (System verilog)
 DYNAMIC ARRAY
 QUEUES
 ASSOCIATIVE ARRAY

PACKED ARRAY:
 Size of packed array will be constant throughout simulation
 Size is determined before the variable name.
 One dimensional packed array called as vector

Ex:
bit [9:0] [8:0] mem
// here [9:0] is no. of groups and [8:0] no. of bits per group
bit [10] [4] mem;
//here 10 no. of groups and [4] is no. of bits per group
UNPACKED ARRAY:
 Size of array will be constant throughout the simulation
 Size is determined after the variable name
 Unpacked array is called array of array or multidimensional array.

Ex:

Bit[3:0][7:0] array [0:3]


// here [3:0] is 4 group per location
[7:0] is 8 bit each group
[0:3] is 4 memory location

Que 1) What is an array in Verilog, and what are its applications in hardware
design?
 Array is a collection of the same data type
 Arrays are used to store multiple values of the same data type and
provide organized way to access and manipulate data.
 They find extensive application in hardware design for tasks such as
representing memories,fifo,buffers.

Que 2) How do you access individual elements of a Verilog array? Provide an


example.
 Individual elements of a verilog array can be accessed using [] bracket.
 Verilog uses zero based indexing

Ex:

Myarray [2] // Third element of myarray.

Que 3) Describe the process of initializing a Verilog array with specific values.

 Verilog arrays can be initialized during declaration using ‘{ }’ syntax.

Ex: int array[3] = ‘{3,4,5] // single dimensional array


Int array [3] [2] = ‘{‘{1,2}, ‘{2,3},’{4,5}}// Two dimensional array

Que 4) Write Verilog code to implement a 2D unpacked array of 4x4 2-bit elements.

reg [1:0] my_array [0:3] [0:3];

Que 5) What is the purpose of using initial and always block with arrays?
 The initial block is used toperform one time initialization of arrays at the
beginning of simulation
 The always block is used to model sequential behavior

Que 6) Describe the use of looping constructs iterate through arrays in verilog

 For looping constructs we used for and foreach loop

Que 7) How can you parameterize the size of an array in verilog?


 We can use parameter or localparameters to make the array size configurable
 Parameters can be defined at the module level
 Localparam are declared within procedural block
--------------------------------------------------------------------------------------------------------------------------------------

Que 8) How can you use verilog arrays for hardware modelling ,like shift registers or
FIFOs?
 Arrays can be used to model shift registers,FIFO.

Que 9) What are the different types of memories you can implement using arrays in
verilog?
 Memories such as RAM,ROM,FIFO,SHIFT REGISTER.

Que 10) How do you use $urandom to initialize a random array in verilog testbenches?
We can us $urandom to initialize random array in verilog testbenches by calling inside initial
and always block
Ex:

initial

begin

for(int i=0;i< my_array.size();i++);

my_array[i] =$urandom;

end

EX:

module tb;
reg [5:0] a; //packed array
reg b [0:4]; //unpacked array

integer c[7:0]; //legal


//integer [31:0] d; //illegal

integer i;
initial

begin
for(i=0;i<8;i++)
begin
b[i] = $urandom;
$display("b[%0d]=%0d",i,b[i]);

end
end
initial
begin
a=6'b101011;

$display("A=%0d",a);
end
initial
begin
for(i=0;i<8;i++)
begin

c[i]=$urandom;
$display("c[%0d]=%0d",i,c[i]);
end
end
endmodule

https://www.edaplayground.com/x/JVBh

Que 11) How do you implement a circular buffer using a verilog array?
 A circular buffer can be implemented using an array along with read and write
pointers.
--------------------------------------------------------------------------------------------------------------------------------------

Que 12) What are the different methods to pass an array as an argument to a verilog
function or module?
 We can pass array as an argument to a verilog function or module using the input
and output keyword followed by the array

Que 13) How do you handle multi-dimensional arrays in verilog testbenches for stimulus
generation?
 For stimulus generation in testbenches,we can use nested loops to iterate though
elements of multidimensional array.

Example of packed array:

module mux(in,sel,out);

input sel;
input [1:0]in;
output out;

assign out= (!sel&in[0])|(sel&in[1]);


endmodule

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