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Experiment 14

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33 views3 pages

Experiment 14

Uploaded by

akgaming20ff
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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EXPERIMENT

OBJECTIVE-

Investigate the operation of Master slave flip-flop.

REQUIREMENTS-

1. Digital Trainer Kit


2. Wires/probes
3. Cutter
4. IC-7400

Theory:

The Master-Slave Flip-Flop is basically two gated SR flip-flops connected together in a series
configuration with the slave having an inverted clock pulse. The outputs from Q and Q from the
“Slave” flip-flop are fed back to the inputs of the “Master” with the outputs of the “Master” flip flop
being connected to the two inputs of the “Slave” flip flop. This feedback configuration from the slave’s
output to the master’s input gives the characteristic toggle of the JK flip flop.

The input signals J and K are connected to the gated “master” SR flip flop which “locks” the input
condition while the clock (Clk) input is “HIGH” at logic level “1”. As the clock input of the “slave” flip
flop is the inverse (complement) of the “master” clock input, the “slave” SR flip flop does not toggle.
The outputs from the “master” flip flop are only “seen” by the gated “slave” flip flop when the clock
input goes “LOW” to logic level “0”.

When the clock is “LOW”, the outputs from the “master” flip flop are latched and any additional
changes to its inputs are ignored. The gated “slave” flip flop now responds to the state of its inputs
passed over by the “master” section.
Then on the “Low-to-High” transition of the clock pulse the inputs of the “master” flip flop are fed
through to the gated inputs of the “slave” flip flop and on the “High-to-Low” transition the same inputs
are reflected on the output of the “slave” making this type of flip flop edge or pulse-triggered.

Then, the circuit accepts input data when the clock signal is “HIGH”, and passes the data to the output
on the falling-edge of the clock signal. In other words, the Master-Slave JK Flip flop is a
“Synchronous” device as it only passes data with the timing of the clock signal.

PROCEDURE:

1. First we took a digital trainer kit ,checked it, and connected it to main
power supply.
2. Then we took IC-7400 along with wires/probes and checked the
operations.
3. Then we made a clean and tidy circuit on the bread-board with the help of
circuit diagram above.
4. Then we provided the inputs and varied them with the help of ports given
for changing the inputs.
5. We observed the outputs by the on/off of LED’s provided for displaying
output.
6. Recorded the values in the truth table.

OBSERVATION:

The truth table for JK Master-Slave has been obtained:

Truth-table for Master-Slave

RESULT:

The designing of Master-Slave flip-flop using NAND Gates has been successfully
made and the desired output has been observed and recorded.

PRECAUTIONS/SOURCES OF ERROR:

1. Check the IC before use.


2. Circuit should be clean and connections should be tight.
3. Observe output carefully.
4. Avoid short-circuit.

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