Unit-3

8085 Assembly Language Programming

(1) Explain instruction format and Opcode format of 8085 μP with example. OR With help of
examples, explain the formation of opcodes of 8085 OR What is an instruction? List type of
instruction based on size.
Ans. Each instruction of 8085 has 1 byte opcode. With 8 bit binary code, we can generate 256
different binary codes. In this, 246 codes have been used for opcodes.

The size of 8085 instructions can be 1 byte, 2 bytes or 3 bytes.

1. One-byte instructions –
In 1-byte instruction, the opcode and the operand of an instruction are represented in one byte.
 Example-1: Task- Copy the contents of accumulator in register B.
Mnemonic- MOV B, A
Opcode- MOV
Operand- B, A
Hex Code- 47H
Binary code- 0100 0111

Note – The length of these instructions is 8-bit; each requires one memory location. The mnemonic
is always followed by a letter (or two letters) representing the registers (such as A, B, C, D, E, H, L
and SP).

2. Two-byte instructions –
Two-byte instruction is the type of instruction in which the first 8 bits indicates the opcode and
the next 8 bits indicates the operand.
 Example-1: Task- Load the hexadecimal data 32H in the accumulator.
Mnemonic- MVI A, 32H
Opcode- MVI
Operand- A, 32H
Hex Code- 3E
32
Binary code- 0011 1110
0011 0010

Note – This type of instructions need two bytes to store the binary codes. The mnemonic is always
followed by 8-bit (byte) data.
 3. Three-byte instructions –

Three-byte instruction is the type of instruction in which the first 8 bits indicates the opcode
and the next two bytes specify the 16-bit address. The low-order address is represented in
second byte and the high-order address is represented in the third byte.
 Example-1: Task- Load contents of memory 2050H in the accumulator.
Mnemonic- LDA 2050H
Opcode- LDA
Operand- 2050H
Hex Code- 3A
50
20
Binary code- 0011 1010
101 0
10 0

(2) Explain the addressing mode of 8085. OR What do you mean by addressing mode? Explain
diff. addressing mode for 8085 with examples.
Ans. The 8085 microprocessor has several addressing modes that are used to access memory
locations. Some of the most commonly used addressing modes in the 8085 microprocessor are:

 The way of specifying data to be operated by an instruction is called addressing mode.

Types of addressing modes –

In 8085 microprocessor there are 5 types of addressing modes:

1. Immediate Addressing Mode –

In immediate addressing mode the source operand is always data. If the data is 8-bit, then the
instruction will be of 2 bytes, if the data is of 16-bit then the instruction will be of 3 bytes.
Examples:
MVI B, 45 (move the data 45H immediately to register B)
LXI H, 3050 (load the H-L pair with the operand 3050H immediately)
JMP address (jump to the operand address immediately)

2. Register Addressing Mode –

In register addressing mode, the data to be operated is available inside the register(s) and
register(s) is(are) operands. Therefore the operation is performed within various registers of the
microprocessor.
Examples:
MOV A, B (move the contents of register B to register A)
ADD B (add contents of registers A and B and store the result in register A)
INR A (increment the contents of register A by one)

3. Direct Addressing Mode –

In direct addressing mode, the data to be operated is available inside a memory location and
 that memory location is directly specified as an operand. The operand is directly available in
the instruction itself.
Examples:
LDA 2050 (load the contents of memory location into accumulator A)
LHLD address (load contents of 16-bit memory location into H-L register pair)
IN 35 (read the data from port whose address is 35)

4. Register Indirect Addressing Mode –

In register indirect addressing mode, the data to be operated is available inside a memory
location and that memory location is indirectly specified by a register pair.
Examples:
MOV A, M (move the contents of the memory location pointed by the H-L pair to the
accumulator)
LDAX B (move contents of B-C register to the accumulator)
STAX B (store accumulator contents in memory pointed by register pair B-C)

5. Implied/Implicit Addressing Mode –

In implied/implicit addressing mode the operand is hidden and the data to be operated is
available in the instruction itself.
Examples:
CMA (finds and stores the 1’s complement of the contents of accumulator A in A)
RRC (rotate accumulator A right by one bit)
RLC (rotate accumulator A left by one bit)

(3)Explain the classification of instructions of 8085 on the basis of their operation OR Give
classification of 8085 instruction set with an example.
Ans. 8085 microprocessor has following types of instructions
 Data Transfer Instructions
 Arithmetic Instructions
 Logical Instructions
 Branching & Looping Instructions
 Stack Instructions
 I/O Instructions
 Machine Control Instructions

Group I - DATA TRANSFER INSTRUCTIONS:

 These instructions move data between registers, or between memory and registers.
These instructions copy data from source to destination. While copying, the contents of
source are not modified.
 Ex: i) MOV A, B ii) LDA 4600 iii) LHLD 4200

Group II - ARITHMETIC INSTRUCTIONS:

 These instructions perform the operations like: Addition, Subtract, Increment, and Decrement.
 Addition:-Any 8-bit number, or the contents of register, or the contents of memory location can
be added to the contents of accumulator. The result (sum) is stored in the accumulator. No two
 other 8-bit registers can be added directly. Example: The contents of register B cannot be added
directly to the contents of register C.
For example, ADD B
 Subtraction: - Any 8-bit number, or the contents of register, or the contents of memory location
can be subtracted from the contents of accumulator. The result is stored in the accumulator.
Subtraction is performed in 2’s complement form. If the result is negative, it is stored in 2’s
complement form. No two other 8-bit registers can be subtracted directly. For example, SUB C
 Increment and Decrement: - The 8-bit contents of a register or a memory location can be
incremented or decremented by 1.The 16-bit contents of a register pair can be incremented or
decremented by 1.Increment or decrement can be performed on any register or a memory
location. Ex: i) INR D ii) INX H

Group III - LOGICAL INSTRUCTIONS:-

 These instructions perform logical operations on data stored in registers, memory and status flags.
The logical operations are: AND, OR, XOR, Rotate, Compare, and Complement
 For example, i) ORA B ii) XRA A iii) RAR

Group IV – BRANCHING & LOOPING INSTRUCTIONS:

 The branching instruction changes the normal sequential flow of the Program. These instructions
alter either unconditionally or conditionally.
 For example, i) JZ 4200 ii) RST 7 iii) CALL 4300

Group V - STACK RELATED INSTRUCTIONS:

 Stack Related instructions are used for accessing the stack.

 For example- PUSH B, POP C

Group VI - I/O INSTRUCTION

 I/O instructions are used for reading or writing the input output port.
 For example- IN 80H, OUT 90H

Group VII - MACHINE CONTROL INSTRUCTIONS:

 The control instruction control the operations of microprocessor.

 For Example- SIM, RIM, HLT

(4) Explain the Data transfer instructions of 8085 with example.

Ans.
Copy from source to destination
This instruction copies the contents of the
Rd, Rs
source register into the destination register,
MOV the contents of Rd, M the source register are
M, Rs not altered. If one of the operands is a
memory location, its location is specified by
the contents of theHL registers.
Rd, M
Example: MOV B, C or MOV B, M

Move immediate 8-bit

 Rd, data The 8-bit data is stored in the destination
MVI
register or memory. If the operand is a
M, data memory location, its location is specified by
the contents of the HL registers.
Example: MVI B, 57H or MVI M, 57H

Load accumulator

LDA 16-bit address The contents of a memory location,

specified by a 16-bit address in the operand,
are copied to the accumulator. The contents
of the source are not altered.
Example: LDA 2034H

Load accumulator indirect

The contents of the designated register pair

LDAX B/D Reg. pair point to a memory location. This instruction
copies the contents of that memory location
into the
Accumulator. The contents of either the
register pair or the memory location are not
altered.
Example: LDAX B

Load register pair immediate

The instruction loads 16-bit data in the
LXI Reg. pair, 16-bit data register pair designated in the operand.
Example: LXI H, 2034H or LXI H, XYZ

Load H and L registers direct

The instruction copies the contents of the
memory location pointed out by the 16- bit
LHLD 16-bit address address into register L and copies the
contents of the next memory location into
register H. The contents of source memory
locations are not altered.
Example: LHLD 2040H
Store accumulator direct
The contents of the accumulator are copied
into the memory location specified by the
STA 16-bit address operand. This is a 3- byte instruction, the
second byte specifies the low-order address
and the third byte specifies the high-order
address.
Example: STA 4350H

Store accumulator Indirect

The contents of the accumulator are copied
STAX Reg. pair into the memory location specified by the
contents of the operand (register pair). The
contents of the accumulator are not altered.
Example: STAX B

Store H and L registers direct

The contents of register L are stored into the
memory location specified by the 16- bit
address in the operand and the contents of H
register are stored into the next memory
SHLD 16-bit address
location by incrementing the operand. The
contents of registers HL are not altered. This
is a 3-byte instruction, the second byte
specifies the low-order address and the third
byte specifies the high-order address.
Example: SHLD 2470H

Exchange H and L with D and E

The contents of register H are exchanged

XCHG None
with the contents of register D, and the
contents of register L are exchanged with the
contents of register E.
Example: XCHG

Copy H and L registers to the stack pointer

The instruction loads the contents of the H
and L registers into the stack pointer
SPHL none register, the contents of the H register
provide the high-order address and the
contents of the L register provide the low-
order address. The contents of the H and L
registers are not altered.
Example: SPHL
 Exchange H and L with top of stack
The contents of the L register are exchanged
with the stack location pointed out by the
contents of the stack pointer register. The
XTHL none contents of the H register are exchanged with
the next stack location (SP+1); however, the
contents of the stack pointer register are not
altered.
Example: XTHL

Push register pair onto stack

The contents of the register pair
designated in the operand are copied onto
the stack in the following sequence. The
stack pointer register is decremented and the
PUSH Reg. pair
contents of the high- order register (B, D, H,
A) are copied into that location. The stack
pointer register is decremented again and the
contents of the low-order register (C, E, L,
flags) are copied to that location.
Example: PUSH B or PUSH A

Pop off stack to register pair

The contents of the memory location pointed
out by the stack pointer register are copied to
the low-order register (C, E, L, status flags)
POP Reg. pair of the operand. The stack pointer is
incremented by 1 and the contents of that
memory location are copied to the high-
order register (B, D, H, A) of the operand.
The stack pointer register is again
incremented by 1.
Example: POP H or POP A

Output data from accumulator to a port with 8-bit address

OUT 8-bit port address The contents of the accumulator are copied
into the I/O port specified by the operand.
Example: OUT F8H
Input data to accumulator from a port with 8-bit address

IN 8-bit port address The contents of the input port designated in

the operand are read and loaded into the
accumulator.
Example: IN 8CH

(5) Explain the Arithmetic instructions of 8085 with example.

Ans.
Following is the table showing the list of Arithmetic instructions with their meanings.

Opcode Operand Meaning Explanation

The contents of the register or memory

Add register or are added to the contents of the
R
ADD memory, to the accumulator and the result is stored in the
M
accumulator accumulator.
Example − ADD K.

The contents of the register or memory &

Add register to the M the Carry flag are added to the contents
R
ADC accumulator with of the accumulator and the result is stored
M
carry in the accumulator.
Example − ADC K

The 8-bit data is added to the contents of

Add the immediate the accumulator and the result is stored in
ADI 8-bit data
to the accumulator the accumulator.
Example − ADI 55K

The 8-bit data and the Carry flag are

Add the immediate
added to the contents of the accumulator
ACI 8-bit data to the accumulator
and the result is stored in the accumulator.
with carry
Example − ACI 55K

The instruction stores 16-bit data into the

Load the register
LXI Reg. pair, 16bit data register pair designated in the operand.
pair immediate
Example − LXI K, 3025M

The 16-bit data of the specified register

Add the register
pair are added to the contents of the HL
DAD Reg. pair pair to H and L
register.
registers
Example − DAD K

The contents of the register or the

Subtract the register memory are subtracted from the contents
R
SUB or the memory from of the accumulator, and the result is stored
M
the accumulator in the accumulator.
Example − SUB K
 The contents of the register or the
memory & M the Borrow flag are
Subtract the source
R subtracted from the contents of the
SBB and borrow from
M accumulator and the result is placed in the
the accumulator
accumulator.
Example − SBB K

The 8-bit data is subtracted from the

Subtract the
contents of the accumulator & the result is
SUI 8-bit data immediate from the
stored in the accumulator.
accumulator
Example − SUI 55K

The contents of register H are exchanged

with the contents of register D, and the
Exchange H and L
XCHG None contents of register L are exchanged with
with D and E
the contents of register E.
Example − XCHG

The contents of the designated register or

Increment the
R the memory are incremented by 1 and
INR register or the
M their result is stored at the same place.
memory by 1
Example − INR K

The contents of the designated register

Increment register pair are incremented by 1 and their result
INX R
pair by 1 is stored at the same place.
Example − INX K

The contents of the designated register or

Decrement the
R memory are decremented by 1 and their
DCR register or the
M result is stored at the same place.
memory by 1
Example − DCR K

The contents of the designated register

Decrement the pair are decremented by 1 and their result
DCX R
register pair by 1 is stored at the same place.
Example − DCX K

The contents of the accumulator are

changed from a binary value to two 4-bit
BCD digits.
If the value of the low-order 4-bits in the
accumulator is greater than 9 or if AC flag
Decimal adjust
DAA None is set, the instruction adds 6 to the low-
accumulator
order four bits.
If the value of the high-order 4-bits in the
accumulator is greater than 9 or if the
Carry flag is set, the instruction adds 6 to
the high-order four bits.
 Example − DAA

(6) Explain the Logical instructions of 8085 with example.

Ans.

Logical instructions in 8085 microprocessor performs the logical operations like AND, OR,
EXCLUSIVE- OR, complement, compare and rotate. The flag conditions are altered after
execution of an instruction in this group.

Explanation of
Opcode Operand Description
Instruction

The contents of the operand (register or

memory) are M compared with the contents
of the accumulator. Both contents are
preserved . The result of the comparison is
shown by setting the flags of the PSW as
R Compare register or
memory with follows:
CMP
M accumulator if (A) < (reg/mem): carry flag is set
if (A) = (reg/mem): zero flag is set
if (A) > (reg/mem): carry and zero flags are
reset
Example: CMP B or CMP M

The second byte (8-bit data) is compared

with the contents of the accumulator. The
values being compared remain unchanged.
The result of the comparison is shown by
Compare immediate setting the flags of the PSW as follows:
CPI 8-bit data
with accumulator
if (A) < data: carry flag is set
if (A) = data: zero flag is set
if (A) > data: carry and zero flags are reset
Example: CPI 89H

The contents of the accumulator are

logically ANDed with M the contents of
the operand (register or memory), and the
Logical AND register result is placed in the accumulator. If the
R
ANA or memory with operand is a memory location, its address is
M accumulator specified by the contents of HL registers. S,
Z, P are modified to reflect the result of the
operation. CY is reset. AC is set.
Example: ANA B or ANA M
 The contents of the accumulator are
logically ANDed with the
8-bit data (operand) and the result is placed
Logical AND in the
ANI 8-bit data immediate with accumulator. S, Z, P are modified to reflect
accumulator the result of the
operation. CY is reset. AC is set.
Example: ANI 86H

The contents of the accumulator are

Exclusive ORed with M the contents of the
operand (register or memory), and the
Exclusive OR register result is placed in the accumulator. If the
R
XRA or memory with operand is a memory location, its address is
M accumulator specified by the contents of HL registers. S,
Z, P are modified to reflect the result of the
operation. CY and AC are reset.
Example: XRA B or XRA M

The contents of the accumulator are

Exclusive ORed with the 8-bit data
Exclusive OR (operand) and the result is placed in the
XRI 8-bit data immediate with accumulator. S, Z, P are modified to reflect
accumulator the result of the operation. CY and AC are
reset.
Example: XRI 86H

The contents of the accumulator are

logically ORed with M the contents of the
operand (register or memory), and the
Logical OR register or result is placed in the accumulator. If the
R
ORA memory with operand is a memory location, its address is
M accumulator specified by the contents of HL registers. S,
Z, P are modified to reflect the result of the
operation. CY and AC are reset.
Example: ORA B or ORA M

The contents of the accumulator are

logically ORed with the 8-bit data
(operand) and the result is placed in the
Logical OR immediate accumulator. S, Z, P are modified to reflect
ORI 8-bit data
with accumulator the result of the operation. CY and AC are
reset.
Example: ORI 86H
 Each binary bit of the accumulator is
rotated left by one position. Bit D7 is
placed in the position of D0 as well as in
RLC None Rotate accumulator left the Carry flag. CY is modified according to
bit D7. S, Z, P, AC are not affected.
Example: RLC

Each binary bit of the accumulator is

rotated right by one position. Bit D0 is
Rotate accumulator placed in the position of D7 as well as in
RRC none the Carry flag. CY is modified according to
right
bit D0. S, Z, P, AC are not affected.
Example: RRC

Each binary bit of the accumulator is

rotated left by one position through the
Carry flag. Bit D7 is placed in the Carry
Rotate accumulator left flag, and the Carry flag is placed in the
RAL none least significant position D0. CY is
through carry
modified according to bit D7. S, Z, P, AC
are not affected.
Example: RAL

Each binary bit of the accumulator is

rotated right by one position through the
Carry flag. Bit D0 is placed in the Carry
Rotate accumulator flag, and the Carry flag is placed in the
RAR none most significant position D7. CY is
right through carry
modified according to bit D0. S, Z, P, AC
are not affected.
Example: RAR

The contents of the accumulator are

Complement
CMA none complemented. No flags are
accumulator
affected. Example: CMA

The Carry flag is complemented. No other

CMC none Complement carry flags are affected.
Example: CMC

Set Carry
STC none Set Carry
Example: STC
(7) Explain Rotate instruction with example.
Ans.
ROTATE Instruction: There are 4 categories of the ROTATE instruction: Rotate accumulator left
(RLC), Rotate accumulator left through carrying (RAL), Rotate accumulator right (RRC), Rotate
accumulator right through carry (RAR). Among these four instructions; two are for rotating left and
two are for rotating right. All of them are explained briefly in the following sections:
1. Rotate accumulator left (RLC) – In this instruction, each bit is shifted to the adjacent left
position. Bit D7 becomes D0. Carry flag CY is modified according to the bit D7.

For example:-
A = D7 D6 D5 D4 D3 D2 D1 D0
//before the instruction
A = 10101010; CY=0
//after 1st RLC
A = 01010101; CY=1
//after 2nd RLC
A = 10101010; CY=0
2. Rotate accumulator left through carry (RAL) – In this instruction, each bit is shifted to the
adjacent left position. Bit D7 becomes the carry bit and the carry bit is shifted into D0. Carry
flag CY is modified according to the bit D7.

For example:
A = D7 D6 D5 D4 D3 D2 D1 D0
//before the instruction
A = 10101010; CY=0
//after 1st RAL
A = 01010100; CY=1
//after 2nd RAL
A = 10101001; CY=0
3. Rotate accumulator right (RRC) – In this instruction, each bit is shifted to the adjacent right
position. Bit D7 becomes D0. Carry flag CY is modified according to the bit D0.
For example:
A = D7 D6 D5 D4 D3 D2 D1 D0
//before the instruction
A = 10000001; CY=0
//after 1st RRC
A = 11000000; CY=1
//after 2nd RRC
A = 01100000; CY=0
4. Rotate accumulator right through carry (RAR) – In this instruction, each bit is shifted to the
adjacent right position. Bit D0 becomes the carry bit and the carry bit is shifted into D7. Carry
flag CY is modified according to the bit D0.

For example:
A = D7 D6 D5 D4 D3 D2 D1 D0
//before the instruction
A = 10000001; CY=0
//after 1st RAR
A = 01000000; CY=1
//after 2nd RAR
A = 10100000; CY=0
Applications of ROTATE Instructions: The ROTATE instructions are primarily used in
arithmetic multiply and divide operations and for serial data transfer. For example:
If A is 0000 1000 = 08H
1. By rotating 08H right : A = 0000 0100 = 04H
This is equivalent to dividing by 2.

2. By rotating 08H left : A = 0001 0000 = 10H

This is equivalent to multiplying by 2.
However, these procedures are invalid when logic 1 is rotated left from D7 to D0 or vice
versa. For example, if 80H is rotated left it becomes 01H.
(8) Explain Branching & Looping Instructions with examples.
Ans.
Branching instructions refer to the act of switching execution to a different instruction sequence as
a result of executing a branch instruction.
The three types of branching instructions are:

1. Jump (unconditional and conditional)

2. Call (unconditional and conditional)

3. Return (unconditional and conditional)

1. Jump Instructions – The jump instruction transfers the program sequence to the memory
address given in the operand based on the specified flag. Jump instructions are 2 types:
Unconditional Jump Instructions and Conditional Jump Instructions.

(a) Unconditional Jump Instructions: Transfers the program sequence to the described memory
address.

OPCODE OPERAND EXPLANATION EXAMPLE

JMP address Jumps to the address JMP 2050

(b) Conditional Jump Instructions: Transfers the program sequence to the described memory
address only if the condition in satisfied.

OPCODE OPERAND EXPLANATION EXAMPLE

JC address Jumps to the address if carry flag is 1 JC 2050

JNC address Jumps to the address if carry flag is 0 JNC 2050

JZ address Jumps to the address if zero flag is 1 JZ 2050

JNZ address Jumps to the address if zero flag is 0 JNZ 2050

JPE address Jumps to the address if parity flag is 1 JPE 2050

JPO address Jumps to the address if parity flag is 0 JPO 2050

JM address Jumps to the address if sign flag is 1 JM 2050

OPCODE OPERAND EXPLANATION EXAMPLE

JP address Jumps to the address if sign flag 0 JP 2050

3. Call Instructions – The call instruction transfers the program sequence to the memory address
given in the operand. Before transferring, the address of the next instruction after CALL is
pushed onto the stack. Call instructions are 2 types: Unconditional Call Instructions and
Conditional Call Instructions.

(a) Unconditional Call Instructions: It transfers the program sequence to the memory address
given in the operand.

OPCODE OPERAND EXPLANATION EXAMPLE

CALL address Unconditionally calls CALL 2050

(b) Conditional Call Instructions: Only if the condition is satisfied, the instructions executes.

OPCODE OPERAND EXPLANATION EXAMPLE

CC address Call if carry flag is 1 CC 2050

CNC address Call if carry flag is 0 CNC 2050

 OPCODE OPERAND EXPLANATION EXAMPLE

CZ address Calls if zero flag is 1 CZ 2050

CNZ address Calls if zero flag is 0 CNZ 2050

CPE address Calls if parity flag is 1 CPE 2050

CPO address Calls if parity flag is 0 CPO 2050

CM address Calls if sign flag is 1 CM 2050

CP address Calls if sign flag is 0 CP 2050

3. Return Instructions – The return instruction transfers the program sequence from the
subroutine to the calling program. Return instructions are 2 types: Unconditional Jump Instructions
and Conditional Jump Instructions.

(a) Unconditional Return Instruction: The program sequence is transferred unconditionally from
the subroutine to the calling program.

OPCODE OPERAND EXPLANATION EXAMPLE

RET none Return from the subroutine unconditionally RET

(b) Conditional Return Instruction: The program sequence is transferred unconditionally from
the subroutine to the calling program only is the condition is satisfied.

OPCODE OPERAND EXPLANATION EXAMPLE

RC none Return from the subroutine if carry flag is 1 RC

RNC none Return from the subroutine if carry flag is 0 RNC

RZ none Return from the subroutine if zero flag is 1 RZ

RNZ none Return from the subroutine if zero flag is 0 RNZ

RPE none Return from the subroutine if parity flag is 1 RPE

RPO none Return from the subroutine if parity flag is 0 RPO

OPCODE OPERAND EXPLANATION EXAMPLE

RM none Returns from the subroutine if sign flag is 1 RM

RP none Returns from the subroutine if sign flag is 0 RP

(9) Explain the Machine Control instructions of 8085 with example.

Ans.
NOP none - No operation is performed:
The instruction is fetched and decoded. However no operation is executed.
Example: NOP
HLT none -Halt and enter wait state:
The CPU finishes executing the current instruction and halts any further execution. An interrupt
or reset is necessary to exit from the halt state.
Example: HLT
DI none - Disable interrupts:
The interrupt enable flip-flop is reset and all the interrupts except the TRAP are disabled. No flags
are affected.
Example: DI
EI none - Enable interrupts:
The interrupt enable flip-flop is set and all interrupts are enabled. No flags are affected. After a
system reset or the acknowledgement of an interrupt, the interrupt enable flip flop is reset, thus
disabling the interrupts. This instruction is necessary to re enable the interrupts (except TRAP).
Example: EI
RIM none - Read interrupt mask:
This is a multipurpose instruction used to read the status of interrupts 7.5, 6.5, 5.5 and read
serial data input bit. The instruction loads eight bits in the accumulator with the following
interpretations.

SIM none -Set interrupt mask:

This is a multipurpose instruction and used to implement the 8085 interrupts 7.5, 6.5, 5.5, and
serial data output. The instruction interprets the accumulator contents as follows.
Example: SIM

(10) What is stack? Explain stack related instruction with example OR Give function of
stack. OR What is stack? Explain the stack operations using examples.
Ans.
The stack is a group of memory location in the R/W memory (RAM) that is used for temporary
storage of data during the execution of a program.
Address of the stack is stored into the stack pointer register.
The 8085 provide two instructions PUSH & POP for storing information on the stack and
reading it back.
a. Data in the register pairs stored on the stack by using the instruction PUSH.
b. Data is read from the stack by using the instruction POP.
c. PUSH & POP both instruction works with register pairs only.
d. The storage and retrieval of the content of registers on the stack fallows the LIFO(Last- In-First-
Out) sequence

Operation of the stack by PUSH and POP Instruction

2000 LXI SP, 2099H ; this instruction define stack

2003 LXI H, 42F2H ; this instruction store 42F2 in to the HL pair
2006 PUSH H ; store HL pair on to the stack
2010 POP H ; store data from top of the stack to HL pair

For PUSH H
The stack pointer is decremented by one to 2098H, and the contents of the h register are copied to
memory location 2098H.The stack pointer register is again decremented by one to 2097H,and the
contents of the L register are copied to memory location 2097H.The contents of the register pair HL
are not destroyed.

For POP H
The contents of the top of the stack location shown by the stack pointer are copied in the L register
and the stack pointer register is incremented by one to 2098 H. The contents of the top of the stack
(now it is 2098H) are copied in the H register, and the stack pointer is incremented by one. The
contents of memory location 2097H and 2098 are not destroyed until some other data bytes are stored
in these location.
(11) Give Classification of 8085 Interrupts and its priorities.
Ans.
Interrupt: It means interrupting the normal execution of the microprocessor. When
microprocessor receives interrupt signal, it discontinues whatever it was executing.
It starts executing new program indicated by the interrupt signal.
Sequence of Steps Whenever There is an Interrupt 
 It pushes the content of PC (Program Counter) to stack.
 Then loads the vector address in PC and starts executing the Interrupt Service Routine (ISR)
stored in this vector address.
 At the end of ISR, a return instruction – IRET will be placed. When the IRET instructions
executed, the processors POP the content of stack to PC. 
 Hence the processor control returns to the main program after servicing the interrupt.
Five Hardware Interrupts in 8085
(1) TRAP
(2) RST 7.5
(3) RST 6.5
(4) RST 5.5
(5) INTR
Classification of Interrupts
(1) Maskable and Non-Maskable
(2) Vectored and Non-Vectored
(3) Edge Triggered and Level Triggered
(4) Priority Based Interrupts
Maskable Interrupts
Maskable interrupts are those interrupts which can be enabled or disabled. Enabling and
Disabling is done by software instructions. The interrupts can be masked by moving an
appropriate data to accumulator and then executing SIM instruction. (SIM - Set Interrupt
Mask).The status of maskable interrupts can be read into accumulator by executing RIM
instruction (RIM - Read Interrupt Mask).
List of Maskable Interrupts:
RST 7.5
RST 6.5
RST 5.5
INTR
-Maskable Interrupts
The interrupts which are always in enabled mode are called non maskable interrupts. These
interrupts can never be disabled by any software instruction.
TRAP is a non-maskable interrupt.

The interrupts which have fixed memory location for transfer of control from normal execution.
List of vectored interrupts:
RST 7.5
RST 6.5
RST 5.5
TRAP
 The addresses to which program control goes:

-Vectored Interrupts
The interrupts which don't have fixed memory location for transfer of control from normal execution is
called Non-Vectored Interrupts. The address of the memory location is sent along with the interrupt.
INTR is a non-vectored interrupt.

The interrupts which are triggered at leading or trailing edge are called edge triggeredinterrupts.
RST 7.5 is an edge triggered interrupt. It is triggered during the leading (positive) edge.

The interrupts which are triggered at high or low level are called level triggered interrupts.RST 6.5
RST 5.5, INTR are level trigger. TRAP is edge and level triggeredinterrupt

Whenever there exists a simultaneous request at two or more pins then the pin with higher priority is
Selected by the microprocessor. Priority is considered only when there are simultaneous requests. Priority
of interrupts:
Interrupt Priority

1. Hardware and Software Interrupts – When microprocessors receive interrupt signals through
pins (hardware) of microprocessor, they are known as Hardware Interrupts.
There are 5 Hardware Interrupts in 8085 microprocessor. They are – INTR, RST 7.5, RST
6.5, RST 5.5, TRAP
Software Interrupts are those which are inserted in between the program which means these
are mnemonics of microprocessor.
There are 8 software interrupts in 8085 microprocessor. They are – RST 0, RST 1, RST 2, RST
3, RST 4, RST 5, RST 6, RST 7.
2. Vectored and Non-Vectored Interrupts – Vectored Interrupts are those which have fixed
vector address (starting address of sub-routine) and after executing these, program control is
transferred to that address.
Vector Addresses are calculated by the formula 8 * TYPE
INTERRUPT VECTOR ADDRESS

TRAP (RST 4.5) 24 H

 INTERRUPT VECTOR ADDRESS

RST 5.5 2C H

RST 6.5 34 H

RST 7.5 3C H

For Software interrupts vector addresses are given by:

INTERRUPT VECTOR ADDRESS

RST 0 00 H

RST 1 08 H

RST 2 10 H

RST 3 18 H

RST 4 20 H

RST 5 28 H

RST 6 30 H

RST 7 38 H