‭[ 1 ] Antenna & Wave Propagation‬

‭ ourse Name :‬‭Antenna & Wave Propagation‬

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‭Course Code :‬
‭Credits : 3 (L-T-P : 3-0-0)‬
‭Syllabus:‬
‭ ) Antenna Fundamentals :- Effective Aperture, Gain, Bandwidth, Beamwidths,‬
1
‭Radiation Resistance, Polarization, Radiation Pattern, Reciprocity Theorem,‬
‭Effective Length, Antenna Temperature.‬
‭2) Antenna Arrays and Frequency Independent Antennas : Collinear, Broadside,‬
‭Endfire Arrays, Binomial, Dolph Tschebyscheff Arrays, Spiral and Log Periodic‬
‭Antennas‬
‭3) UHF and Microwave Antennas: Parabolic Reflector, Horn , Lens‬
‭Antennas, Microstrip Antennas and Arrays, Analysis and feed networks‬
‭4) Radio Wave Propagation: Ground, Space and Sky wave Propagation, Ionospheric‬
‭Layers, Analysis of EM wave Propagation in ionic medium, MUF and skip zone‬
‭5) Antennas for 5G Communication, Wave Propagation Models in Mobile‬
‭Environment‬

‭ eferences:‬
R
‭1. Antennas Theory and Analysis - By Balanis ( Wiley Publisher)‬
‭2. Antennas and Wave Propagation by K. D. Prasad‬
‭3. Antennas by Krauss ( TMH Publisher)‬

‭ ourse Name : Antenna and Wave Propagation Lab‬

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‭Course Code :‬
‭Credits : 1 (L-T-P: 0-0-2)‬
‭List of Experiments‬
‭ . To study and plot the radiation pattern of λ/2 Dipole antenna in azimuth plan on log/linear scale on‬
1
‭polar plot.‬
‭2. To study and plot the radiation pattern of folded Dipole antennas in azimuth plan on log/linear scale‬
‭on polar plot.‬
‭3. To study and plot the radiation pattern of Yagi (4el) antenna in azimuth plan on log/linear scale on‬
‭polar plot.‬
‭4. To study and plot the radiation pattern of the Square Loop antenna in azimuth plan on log/linear‬
‭scale on polar plot.‬
‭5. To study and plot the radiation pattern of Helix antenna in azimuth plan on log/linear scale on polar‬
‭plot.‬
‭6. To study and plot the radiation pattern of Micro Strip antenna in azimuth plan on log/linear scale on‬
‭polar plot.‬
‭7. To study and plot the radiation pattern of Log Periodic antenna in azimuth plan on log/linear scale‬
‭on polar plot.‬
‭8. To study and plot the radiation pattern of the End Fire antenna in azimuth plans on Log/linear scale‬
‭on polar plot.‬
‭9. To study and plot the radiation pattern of Broadside antenna in azimuth plans on Log/linear scale on‬
‭ olar plot.‬
p
‭10. To study resonant and non-resonant antenna and calculate the resonant frequency and estimate the‬
‭VSWR of the antenna.‬
‭11. Familiarization with basic operation of Vector Network Analyzer (VNA) and Use the VNA to‬
‭measure the complete S parameters of the components under test‬
‭[ 2 ] Digital CMOS IC‬

‭ ourse Name :‬‭Digital CMOS IC‬

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‭Course Code :‬
‭Credits : 3 (L-T-P : 3-0-0)‬
‭ yllabus:‬
S
‭Introduction to MOSFETs technology‬‭: Construction and‬‭working of MOSFET, Current-Voltage‬
‭Characteristics, and Performance metrics for digital design, Fabrication flow of CMOS n-well‬
‭process.‬
‭CMOS Inverter:‬‭Design and analysis of NMOS inverter‬‭(resistive, enhancement and depletion load),‬
‭CMOS inverters; Noise margins, rationing of transistor size, logic voltage levels, rise and fall of‬
‭delays,Propagation Delay, Power Consumption.‬
‭Combinational Circuits‬‭: Design of basic gates in NMOS‬‭technology; CMOS logic design styles:‬
‭static‬
‭CMOS logic (NAND, NOR gates), complex gates, Pass Transistor logic, Transmission gate, Dynamic‬
‭MOS design: pseudo NMOS logic, clocked CMOS (C2 MOS) logic, domino logic, NORA, Half and‬
‭Full adder), Multiplexer, XOR, XNOR.‬
‭Logical Effort:‬‭Logical effort of different digital‬‭circuit design, parasitic delay, Single stage and‬
‭Multistage with and without branch network.‬
‭Layout and stick diagram‬‭: Layout design rules: Lambda‬‭and micron based design rules-stick‬
‭diagram,‬
‭Layout design of different CMOS circuit, area estimation.‬
‭Sequential Circuits and Memory Design:‬‭Sequential‬‭MOS Logic and Memory Design: Static‬
‭latches;‬
‭Flip flops & Register.‬

‭References:‬
‭ .‬‭Sung-Mo Kang & Yusuf Leblebici, CMOS Digital Integrated‬‭Circuits Analysis and Design, Second‬
1
‭Edition, McGraw-Hill, 1999.‬
‭2.‬‭Rabaey, Chandrakasan and Milokic. Digital system‬‭design- A design perspective. Pearson‬
‭education, India.‬
‭3.‬‭Neil H.E.Weste and Kamran Eshraghian, Principles‬‭of CMOS VLSI Design, A System Perspective,‬
‭Pearson Education, India. 4. Ken Martin, Digital Integrated Circuits, Oxford Press.‬
‭4.‬‭CMOS Circuit Design, Layout and simulation: J.‬‭Baker, D.E. Boyce., IEEE press.‬

‭ ourse Name : Digital CMOS IC Lab‬

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‭Course Code :‬
‭Credits : 1 (L-T-P: 0-0-2)‬
‭List of Experiments‬
‭ . V characterization of Long channel N-MOSFET & P-MOSFET for using SPICE simulation.‬
1
‭2. V characterization of Short Channel N-MOSFET & P-MOSFET using a SPICE simulation.‬
‭3. VTC analysis of CMOS Inverter for different W/L Ratio of NMOS and PMOS.‬
‭4. Transient analysis of CMOS Inverter for input signal of equal rise and fall time.‬
‭5. Noise Margin Analysis of different NMOS based Inverter circuits such as Diode Connected Load,‬
‭Depletion Load, PMOS Load, etc.‬
‭6. Connect a 2 I/P NAND Gate to an identical NAND Gate such that the fan out is 1,2,5,10,50,100.‬
‭Plot the propagation Delay.‬
‭ . Connect a set of 7 inverters in a closed loop in the form of a clock. Estimate the clock frequency.‬
7
‭Determined experimentally change in clock frequency without load (i.e Cout/Cin), varying from‬
‭1, 20, 100.‬
‭8. Connect 3 I/P NAND gate a, b, c and connect to a capacitor such that fan out is 1. Find the rise‬
‭time of NAND gate for the I/P=000; 001; 011.‬
‭9. To design layout of CMOS inverter and followed by simulation.‬
‭10. To design a layout of 2 input NOR gate and followed by simulation.‬
‭11. To design a layout of 3 input NAND gate and followed by simulation.‬
‭12. Mini projects‬
‭[ 3 ] Embedded Systems‬

‭ ourse Name :‬‭Embedded Systems‬

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‭Course Code :‬
‭Credits : 3 (L-T-P : 3-0-0)‬
‭Syllabus:‬
‭ yllabus:‬
S
‭Embedded Computing-‬‭Microprocessors, embedded design‬‭process, system‬
‭description‬
‭formalisms. Instruction sets- CISC and RISC;‬
‭MBeD platform; ARM architectures and programming- Cortex M0 etc;‬
‭CPU fundamentals-‬‭programming I/Os, co-processors,‬‭supervisor mode,‬
‭exceptions, memory‬
‭management units and address translation, pipelining, superscalar execution,‬
‭caching, CPU power‬
‭consumption.‬
‭Embedded platform‬‭- CPU bus, memory devices, I/O devices,‬‭interfacing,‬
‭debugging techniques.‬
‭Realtime OS, timer & pulse width modulation, Serial and parallel communication,‬
‭digital I/O,‬
‭Analog I/O, interrupts, low power techniques‬
‭Hardware accelerators-‬‭CPUs and accelerators, accelerator‬‭system design.‬
‭Networks- distributed‬
‭embedded architectures, networks for embedded systems, network-based design,‬
‭Internet-enabled‬
‭Systems.‬

‭ eferences:‬
R
‭1)Wolf, W. Computers as components- Principles of embedded computing system‬
‭design.‬
‭Academic Press (Indian edition available from Harcourt India Pvt. Ltd., 27M Block‬
‭market,‬
‭Greater Kailash II, New Delhi-110 048.)‬
‭2)Vahid and T. Givargis. Embedded System Design: A Unified Hardware/Software‬
‭Introduction , Wiley, 2002.‬
‭3)Furber, ARM System-on-Chip Architecture, Pearson‬
‭4)ARM reference manuals for cortex M0+‬

‭ ourse Name : Embedded Systems Lab (Embedded Systems Design Lab)‬

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‭Course Code :‬
‭Credits : 1 (L-T-P: 0-0-2)‬
‭ ist of Experiments‬
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‭1. Write a C or Assembly program to interface 7 segments with 8051/ARM to display 0-9 and 0-99 on‬
‭Universal embedded system Board.‬
‭ . Write a C or Assembly program to interface 16*2 Char LCD module with 8051/ARM on Universal‬
2
‭embedded system Board.‬
‭3. Write a C or Assembly program to interface ADC 0809 IC with 8051/ARM and Read Value on‬
‭LCD on Universal embedded system Board.‬
‭4. Write a C or Assembly program to interface DAC 0808 IC with 8051/ARM and Sine and triangular‬
‭Wave on Universal embedded system Board.‬
‭5. Write a C or Assembly program to interface a DC motor with 8051/ARM and Control the RPM‬
‭using PWM on Universal embedded system Board.‬
‭6. Write a C or Assembly program to interface Stepper Motor with 8051/ARM and study the angle of‬
‭rotation on Universal embedded system Board.‬
‭7. Write a C or Assembly program to interface Serial Communication with 8051/ARM and Read the‬
‭Value of ADC on PC.‬
‭8. Write a C or Assembly program to interface RTC with 8051/ARM and Read the Time on LCD and‬
‭serial monitor on PC.‬
‭9. Write a C or Assembly program to interface Relay Buzzer with 8051/ARM and control and per‬
‭instruction.‬
‭10. Write a C or Assembly program to interface HEX KEYPAD with 8051/ARM and Read the Values‬
‭on LCD and serial monitor on PC.‬
‭11. Write a C or Assembly program to interface external EEPROM with 8051/ARM and store the‬
‭values of ADC.‬
‭[ 4 ] VLSI Testing & Testability‬

‭ ourse Name : VLSI‬‭Testing &Testability‬

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‭Course Code :‬
‭Credits : 3 (L-T-P : 3-0-0)‬
‭ yllabus:‬
S
‭Introduction to Digital Testing:‬‭Introduction, Test‬‭process and Test economics,- Functional vs.‬
‭Structural Testing Defects, Errors, Faults and Fault Modeling (Stuck at Faults, Bridging Faults,‬
‭transitor‬
‭fault, delay fault), Fault Equivalence, Fault Dominance, Fault Collapsing and Checkpoint Theorem‬
‭Fault Simulation and Testability Measures:‬‭Circuit‬‭Modelling and Algorithms for Fault‬
‭Simulation,‬
‭Serial Fault Simulation, Parallel Fault Simulation, Deductive Fault Simulation, Concurrent Fault‬
‭Simulation, Combinational SCOAP Measures and Sequential SCOAP Measures, Critical Path Tracing‬
‭C‭o ‬ mbinational Circuit Test Pattern Generation:‬‭Introduction‬‭to Automatic Test Pattern‬
‭Generation‬
‭(ATPG) and ATPG Algebras, Standard ATPG Algorithms, D-Calculus and D-Algorithm, Basics of‬
‭PODEM Random, Deterministic and Weighted Random Test Pattern Generation; Aliasing and its‬
‭effect on Fault Coverage.‬
‭PLA Testing‬‭, Cross Point Fault Model and Test Generation.‬‭Memory Testing- Permanent,‬
‭Intermittent‬
‭and Pattern Sensitive Faults‬
‭Sequential Circuit Testing and Scan Chains:‬‭ATPG for‬‭Single-Clock Synchronous Circuits,‬
‭Use of‬
‭Nine-Valued Logic and Time-Frame Expansion Methods, Complexity of Sequential ATPG, Scan‬
‭Chain‬
‭based Sequential Circuit Testing, Scan Cell Design, Design variations of Scan Chains, Sequential‬
‭Testing based on Scan Chains, Overheads of Scan Design, Partial-Scan Design Controllability and‬
‭Observability Scan Design, BILBO , Boundary Scan for Board Level Testing ; BIST and Totally self‬
‭checking circuits‬
‭Self Repairing circuits and BIST:‬‭Introduction to‬‭BIST architecture BIST Test Pattern Generation,‬
‭Response Compaction and Response Analysis, Memory BIST, March Test, BIST with MISR,‬
‭Neighbourhood Pattern Sensitive Fault Test, Transparent Memory BIST, Totally self checking‬
‭circuits,‬
‭Concept of Redundancy, Spatial Redundancy, Time Redundancy, Error Correction Codes. Recent‬
‭trends in VLSI Testing and Testability‬

‭References:‬
‭ ) Abramovici, M., Breuer, M. A. and Friedman, A. D. Digital systems testing and testable‬
1
‭design. IEEE press (Indian edition available through Jayco Publishing house), 2001.‬
‭2) Bushnell and Agarwal, V. D. VLSI Testing. Kluwer.‬
‭3) Agarwal, V. D. and Seth, S. C. Test generation for VLSI chips. IEEE computer society‬
‭press.‬
‭4) Hurst, S. L. VLSI testing: Digital and mixed analog/digital techniques. INSPEC/IEE, 1999‬
‭5) https://nptel.ac.in/courses/106103116/handout/mod7.pdf‬
‭6) http://ece-research.unm.edu/jimp/vlsi_test/slides/html/overview1.htm,‬
‭7) http://www.cs.uoi.gr/~tsiatouhas/CCD/Section_8_1-2p.pdf, Latest‬
‭[ 5 ] Computer Architecture‬

‭ ourse Name :‬‭: Computer Architecture‬

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‭Course Code :‬
‭Credits : 3 (L-T-P : 3-0-0)‬
‭Syllabus:‬
‭ ingle processor-‬‭basics of microprocessors,CPU control‬‭unit, Register Transfer and Micro‬
S
‭operations, assembler and Instruction set pipeline architecture.‬
‭16-bit, 32-bit /64-bit RISC and CISC processors ISA and assembly programming.‬
‭Memory organization-‬‭memory hierarchy, main memory,‬‭associative memory, cache memory,‬
‭virtual memory, memory management .‬
‭Input-output organization-‬‭peripheral devices . Bus‬‭interface. Data transfer techniques.‬
‭Direct memory access. I/O interrupts.‬
‭Multiprocessors-‬‭characteristics of microprocessors.‬‭Interconnection structures.‬
‭Interprocessor arbitration. Digital computer arithmetic- fixed point addition,subtraction,‬
‭multiplication and division. Decimal arithmetic. Floating point arithmetic.‬

‭References:‬
‭ ) Computer System Architecture-M. Morris Mano (PHI)‬
1
‭2) Computer Architecture- A quantitative approach (ARM ed) -Hennessy , Patterson (PHI) Computer‬
‭Organization -V. Carl. Hamacher (TMH)‬
‭3) Computer Organization and Architecture -John P Hayes (McGraw -Hill) Computer Organization‬
‭and‬
‭Architecture – William Stallings (Pearson)‬
‭4) Computer System Organization-A. S. Tanenbaum (PHI).‬
‭Universal Human Values & Ethics (Audit course)‬
‭ -T-P: 2-0-0 (2 Credits )‬
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‭Syllabus‬
‭A. Universal Human Values-‬
‭·‬‭Need, Basic Guidelines, Content and Process for‬‭Value Education‬
‭·‬‭The problem Twin goals: happiness and just order;‬‭the role of value education‬
‭·‬‭Paradoxes of happiness Concepts of good life – quality‬‭of life and subjective‬
‭well-being;‬
‭happiness, life satisfaction, and positive affect; studying the quality of life through‬
‭surveys;‬
‭and findings of quality The problem of social transformation Moral and institutional‬
‭approaches; and the inherent conflict between the two‬
‭·‬‭Human values and humanism: dilemmas and directions-‬‭Jeevan Vidya; human‬
‭values, “I”‬
‭and “Body” need for harmony in the self; harmony with the body; harmony in family,‬
‭society, nature and existence; evaluation of Jeevan Vidya.‬‭Implications of the above‬
‭Holistic‬
‭Understanding of Harmony on Professional Ethics‬
‭·‬‭Conceptualizing the relationship between man and‬‭society- Man and society;‬
‭theories of‬
‭man and society such as methodological individualism, structuralism, Gidden’s‬
‭theory of‬
‭structuration, and structural symbolic interactionism‬
‭·‬‭Religious and spiritual approaches to human happiness-‬‭Vedic, Jain and Buddhist‬
‭philosophies; Christianity; Islam; Zoroastrianism, and Sikhism‬
‭B. Ethics & Professionalism-‬
‭·‬‭Possibilities of transformation- Hope and hopelessness;‬‭transforming society;‬
‭·‬‭Ethical Theories, Meta ethical theories- Consequentialist‬‭and Non-consequentialist‬
‭Theories; Hedonism; Utilitarianism; Ethical Relativism: Is Anything Wrong at‬
‭all? Ethical Naturalism; Non-naturalism; Non-cognitive or Non-descriptivist Theories;‬
‭Intuitionism; Approach to an Adequate Theory; the Moral point of view; Why be‬
‭Moral?‬
‭·‬‭Professional ethics- The liberal society's values;‬‭Professions' nature and traits;‬
‭Professional Ethics' roots and conventions; Professionals require their own code of‬
‭behaviour.‬
‭·‬‭The connection between professional and broader‬‭ethical standards; The topic of‬
‭professional Ethics' autonomy and moral dilemma; Care practice, legal Ethics;‬
‭Environmentalism; Computer Ethics; Business Ethics‬
‭Text:‬
‭1. Human Values and Professional Ethics by R R Gaur, R Sangal, G P Bagaria,‬
‭Excel‬
‭Books, New Delhi, 2010‬
‭ . Weston, Anthony. A 21st Century Ethical Toolbox. New York: Oxford University‬
2
‭Press,‬
‭2008.‬
‭3. Hospers, John. An introduction to philosophical analysis. New Delhi: Allied‬
‭Publishers‬
‭Private Limited, 1967.‬

‭ ourse Name : Project Lab I‬

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‭Course Code :‬
‭Credits : 3 (L-T-P: 0-0-6)‬
‭List of Experiments/ activities‬
‭ esign, verification, prototyping and implementation of hardware/ software‬
D
‭Devices, circuits and systems based on software, hardware, algorithms, protocol, concepts in‬
‭emerging‬
‭areas such as AI, ML, IoT, Sensors, Smart Antennas, NOMA, Computer Vision, Computer‬
‭Networking,‬
‭Nano Devices, Smart Materials, Data Mining, Nano Photonics, Optical Wireless Communications,‬
‭Embedded Systems, Chip Design, Drone Technology and related areas‬