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Control Unit Part3

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12 views

Control Unit Part3

Uploaded by

ee23b029
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Control Unit for Contemporary

Instruction Set Processors


Part 3
Overview

⚫ Discussed basics of hardwired control.


⚫ Also presented the GCD algorithm and some
aspects of the architecture.
⚫ Will now discuss the classical method for
realizing a control unit for the GCD
processor.

2
Classical Method

⚫ The control circuit consists of some


combinational logic elements and sequential
logic elements (with smallest number of flip-
flops).
⚫ To this end, we need to construct a state table.
⚫ To identify the states for the table, look at the
procedure we have given for gcd. The procedure
is reproduced next.

3
GCD procedure

4
How many states ?

⚫ Four states labelled S0, S1, S2 and S3.


⚫ Start (S0): when Reset becomes 1, this state
is entered where the input numbers (X and
Y) are loaded into the registers.
⚫ Thereafter, we have either a swap or a
subtract. These define the next two states:
Swap (S1) and Subtract (S2).
⚫ When gcd has been calculated, we enter the
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last state, namely S3 (corresponding to End)
Assignment of bit strings to the states

⚫ We assign bit patterns to the states so that


we can draw the state table
⚫ S0: 0 0
⚫ S1: 0 1
⚫ S2: 1 0
Our state table will be constructed using
⚫ S3: 1 1 the Moore Model where the output
depends only on the present state

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The state table

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Explanation

⚫ The inputs and outputs are decided based on


what is coming into the control block and what is
going out (look at the architecture presented
earlier)
⚫ The transitions to various states are based on
the GCD algorithm.
⚫ If input control signal (XR > 0) = 0, then the while
loop should not be taken (we move to End
directly)
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More on the state table

⚫ When ((XR > 0) = 1), i.e., XR is indeed greater than zero, we


enter the while loop and make a transition to S1 (swap) if XR <
YR (i.e., (XR >= YR) = 0).
⚫ Otherwise, if XR >= YR is true (i.e., (XR >=YR) = 1), we
perform a subtraction (S2)
⚫ Note subtraction always follows a swap so all next state entries
in row 2 are S2. Next state entries for third row (S2) are same
as that of first row (S0).
⚫ With respect to output columns, note in Swap state, output in
Swap col will be 1 while in Subtract state, output in Subtract col
will be 1

9
What is the next step ?

⚫ The state table is not adequate to get the full


control circuit which has some combinational
logic elements and some sequential logic
elements.
⚫ In particular, we need to determine the
number of flip-flops our circuit will have so
that we can write the excitation table.
⚫ How many flip-flops will our circuit have ?
10
How many flip-flops will our circuit have ?

⚫ There are 4 states so two flip-flops are


adequate.
⚫ Our excitation table will have inputs, present
state, next state and the outputs as the
columns.
⚫ What are the inputs and outputs ? How do
we decide them ?

11
What are the inputs and outputs ?

⚫ The inputs are the signals that come from the


datapath block (to the control block).
⚫ The outputs are the signals that go to the
datapath block from the control block.
⚫ We’ll look at the architecture diagram again
to list the signals.

12
The architecture

13
On the excitation table …

⚫ We will choose D flip-flops for our circuit


(makes our design simple).
⚫ Goal is to obtain expressions for the next
state and outputs using the excitation table.
⚫ The excitation table derived from the state
table is shown next.

14
Excitation table

15
Assumptions to get equations

⚫ We want to use the excitation table to get the


equations for next state and outputs.
⚫ We assume the Moore model so our outputs
will depend only on the present state (and
not on the inputs).

16
Equations from excitation table

17
Final step: Drawing the circuit

⚫ We will draw an ALL-NAND circuit.


⚫ To this end, we need to rewrite the equations
we have got so far.
⚫ As an example, consider the equation for
next state for the second flip-flop. It can be
rewritten as shown next.

18
Next state via NAND

19
The overall circuit

20
Remarks on the circuit

⚫ The circuit is a direct consequence of the


equations presented.
⚫ On the left are the inputs to the control unit
(coming from the datapath unit) while on the
right (end), we see the control signals which
go as inputs to the datapath unit.
⚫ Please refer to the overall arrangement
(architecture) diagram as well.
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Reference

⚫ J. Hayes, Computer Architecture and


Organization, McGraw-Hill, 2017.

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