Pipelining

Slide courtesy: Smruti

Ranjan Sarangi

Slides adapted by: Dr Sparsh Mittal

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 Outline
 Overview of Pipelining
 A Pipelined Data Path

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Designing Efficient Processors

 Without pipelining, there is lot of waste

 We have 5 stages.
 What is the IF stage doing, when the MA stage is
active ?
 ANSWER : It is idling

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 The Notion of Pipelining

 Let us understand the car assembly line

 Is the engine shop idle, when the paint shop is
painting a car ?
 NO : It is building the engine of another car
 When this engine goes to the body shop, it
builds the engine of another car, and so on ….
 Insight :
 Multiple cars are built at the same time.
 A car proceeds from one stage to the next

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 Pipelined Processors
inst 5 inst 4 inst 3 inst 2 inst 1

Instruction Operand Execute Memory Register

Fetch Fetch Access Write
(IF) (OF) (EX) (MA) (RW)

 The IF, ID, EX, MA, and RW stages process

5 instructions simultaneously
 Each instruction proceeds from one stage
to the next
 This is known as pipelining
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 Advantages of Pipelining

 We keep all parts of the data path, busy all

the time
 Let us assume that all the 5 stages do the
same amount of work
 Without pipelining, every T seconds, an
instruction completes its execution
 With pipelining, every T/5 seconds, a new
instruction completes its execution

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 Design of a Pipeline
 Splitting the Data Path
 We divide the data path into 5 parts : IF, OF, EX,
MA, and RW
 Timing
 We insert latches (registers) between
consecutive stages
 4 Latches → IF-OF, OF-EX, EX-MA, and MA-RW
 At the negative edge of a clock, an instruction
moves from one stage to the next
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Pipelined Data Path with Latches

Latches

Instruction Operand Execute Memory Register

Fetch Fetch Access Write
(IF) (OF) (EX) (MA) (RW)

 Add a latch between subsequent stages.

 Triggered by a negative clock edge

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 The Instruction Packet
 What travels between stages ?
 ANSWER : the instruction packet
 Instruction Packet
 Instruction contents
 Program counter
 All intermediate results
 Control signals
 Every instruction moves with its entire state, no
interference between instructions
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 Outline

 Overview of Pipelining
 A Pipelined Data Path

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 IF Stage

instruction

instruction IF/OF Register

 Instruction contents saved in the instruction field

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 OF Stage
instruction

Control
Immediate and unit
branch target

branchTarget op2 instruction control

 A, B → ALU Operands, op2 (store operand),

control (set of all control signals)

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 EX Stage

pc branchTarget B A op2 instruction control OF-EX

aluSignals

flags
0 1 isBeq
Branch
isRet ALU unit isBgt
branchPC ?ags
isUBranch
isBranchTaken

pc aluResult op2 instruction control EX-MA

 aluResult → result of the ALU Operation

 op2, control, pc, instruction (passed from
OF-EX)

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 MA Stage
pc aluResult op2 instruction control EX-MA

mar mdr
isLd
Data memory Memory
unit
isSt

pc instruction control MA-RW

ldResult aluResult

 ldResult → result of the load operation

 aluResult, control, pc, instruction (passed
from EX-MA)

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 RW Stage

pc ldResult aluResult instruction control

4 isLd
10 01 00 isCall isWb
E
rd
0
Register
E enable A file
1
data ra(15) D
A address
D data

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 1

pc + 4 0

pc Instruction instruction
memory

pc instruction

rd rs2 ra(15) rs1

1 0 1 0 isSt
isRet Control
reg
Immediate and Register unit
file data
branch target
op2 op1
isWb
immx isImmediate
1 0

pc branchTarget B A op2 instruction control

aluSignals

flags
0 1 isBeq
Branch
isRet ALU unit isBgt
isUBranch

isBranchTaken
pc aluResult op2 instruction control

mar mdr
isLd
Data
Memory
memory unit
isSt

pc ldResult aluResult instruction control

4 isLd
isWb
10 01 00 isCall
rd
0

ra(15) 1
data

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 Abridged Diagram

IF-OF OF-EX EX-MA MA-RW

Control
unit Branch
unit Memory
unit
Fetch Immediate Register
and branch flags write unit
unit unit

Data
ALU
memory
op2 Unit
Instruction Register
memory file op1

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