Microprocessor and Microcontroller

UNIT V MICROCONTROLLER
PROGRAMMING& APPLICATIONS

5.1 Introduction
The function of the microprocessor or a micro controller is to accept data
from input devices such as keyboards, A/D converters, etc and send the results
to output devices such as LEDs, Printers and Video Monitors. These input and
output devices are called either peripherals or I/O devices. Designing 108C
circuits and writing instructions to enable the processor to communicate with
these peripherals is called interfacing. And the logic circuits are called I/O ports
or interfacing devices.

5.2 Data Transfer Instructions

The MOV – op-code involve data transfers within the 8051 memory.
The MOVX – op-code involve data transfer from external RAM
The MOVC – op-code involve data transfer from external ROM
PUSH & POP – op-code involves data transfer from stack and memory
locations.
XCH – op-code exchanges data between Accumulator and Registers

Data Transfer Instructions of 8051

Sl. Mnemonic Byte Machine Cycle
1. MOV A, Rn 1 1
2. MOV A, Direct 2 1
3. MOV A, @Ri 1 1
4. MOV A, #Data 2 1
5. MOV Rn, A 1 1
6. MOV Rn, Direct 2 2
7. MOV Rn, #Data 2 1
8. MOV Direct, A 2 1
9. MOV Direct, Rn 2 2
10. MOV Direct, Direct 3 2
11. MOV Direct, @Ri 2 2

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 12. MOV Direct, #Data 3 2
13. MOV @Ri, A 1 1
14. MOV @Ri, Direct 2 2
15. MOV @Ri, #Data 2 1
16. MOV DPTR, #Data (16) 3 2
17. MOVX A, @Ri 1 2
18. MOVX A, @DPTR 1 2
19. MOVX @Ri, A 1 2
20. MOVX @DPTR, A 1 2
21. PUSH Direct 2 2
22. POP Direct 2 2
23. XCH A, Rn 1 1
24. XCH A, Direct 2 1
25. XCH A, @Ri 1 1
26. XCHD A, @Ri 1 1

5.3 Logical Operations

The main application of 8051 microcontroller is that of machine control. A
large part of machine controls, making decisions based on the switch states,
and then turning external circuits ON or OFF is based on Boolean operators.
These operations are termed as Logical operations.

Byte Level Logical Operations

AND Operation
ANL Destination, Source
This instruction will perform a logical AND on the two operands and place
the result in destination. Normally the destination is Accumulator. The source
operand can be a register, location in memory or immediate data. Both the
source and the destination values are of single byte size.

Examples
I) MOV A, #39h; A = 39h
ANL A, #43h; 39H ANDed with 43h, A = 01h
Truth table of AND operation

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A B A ANDed
B
0 0 0
0 1 0
1 0 0
1

39h = 00111001
43h = 01000011
ANDed = 00000001
Now A = 01h
ii) MOV A, #32h; A = 32h
MOV R4, #50h ; R4 = 50h
ANL A, R4 ; A Anded with R4. A = 10h
32h = 00110010
50h = 01010000
ANDed = 0 0 0 1 0 0 0 0 Now A = 10h

OR Operation
Instruction: ORL Destination, Source
This instruction performs a logical OR on the two operands and place the
result in the destination. The destination is normally the Accumulator. The
source operand can be a register, any location in memory or immediate data.
Both the source and the destination values are of single byte size.

Example
I) MOV A, #39h ; Accumulator = 39h
ORL A, #43h ; 39h ORed with 43h, A = 7Bh
Truth table of OR operation

A B A ORed
B
0 0 0
0 1 1
1 0 1
1 1 1

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 39H = 00111001
43H = 01000011
ORed 01111011
Now A = 7Bh

ii) MOV A, #32h; Accumulator = 32h

MOV R4, #50h; Register R4 = 50h
ORL A, R4; 32H ORed withe 50h, A = 72h
32H = 00110010
50H = 01010000
ORed 0 1 1 1 0 0 1 0 Now A = 72h

EXOR Operation
Instruction: XRL Destination, Source
This instruction performs a logical XOR on the two operands and places the
result in the destination. The destination is normally the Accumulator. The
source operand can be a register, any location in memory or immediate data.
Both the source and the destination values are of single byte size.

Example
I) MOV A, #39h ; Accumulator = 39h
XRL A, #43h ; 39h ORed with 43h, A = 7Ah

Truth table of XOR operation

A B A XORed
B
0 0 1
0 1 0
1 0 0
1 1 1
39h = 00111001
43h = 01000011
XORed 01111010
Now A = 7Ah

ii) MOV A, #32h; Accumulator = 32h

MOV R4, #50h; Register R4 = 50h

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XRL A, R4; 32h ORed with 50h, A = 62h

32h = 00110010
50h = 01010000
XORed = 01100010
Now A = 62h

Complement Operation
Instruction CPL A
This instruction complements the contents of register A the Accumulator.
The complementation changes the 0s to 1s and the 1s to 0s. To perform the
complement operation, the data should be in Accumulator.

Example
MOV A, #55h ; Accumulator = 55h

CPL A ; 55hcomplemented to AAH, A = AAh

A = 0 1 0 1 0 1 0 1 A = 55h
CPL A = 1 0 1 0 1 0 1 0 A = AAh

5.4 Rotate and Swap Operations

The data in Accumulator can be rotated one bit in left or right by rotate
instruction. The carry flag CY also can be included with accumulator for rotate
instruction. When Accumulator alone is rotated, only 8 bits in A register is
rotated. When CY flag also included, then 9 bits are rotated.
The swap instruction is used to interchange the lower and upper nibble of
Accumulator. When swap instruction is executed the lower nibble of A register
becomes upper nibble, and upper nibble becomes lower nibble.

Instructions
RL A
Accumulator contents are shifted on bit to left and A7 to A0, A0 to A1, A1 to
A2 and so on...

7 6 5 4 3 2 1 0
A7 A6 A5 A4 A3 A2 A1 A0

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RLC A
Contents of Accumulator with CY flag shifted one bit left. A7 to CY, CY to A0,
A0 to A1 and so on...

7 6 5 4 3 2 1 0
CY
A7 A6 A5 A4 A3 A2 A1 A0

RR A
Accumulator contents shifted one bit to Right. A0 to A7, A7 to A6, A6 to A5
and so on...

7 6 5 4 3 2 1 0
A7 A6 A5 A4 A3 A2 A1 A0

RRC A
Contents of Accumulator with CY flag Shifted one bit right. A0 to CY, CY to
A7, A7 to A6 and so on...

7 6 5 4 3 2 1 0
CY
A7 A6 A5 A4 A3 A2 A1 A0
SWAP A ; Interchange the nibbles of Accumulator.

7 6 5 4 3 2 1 0
A7 A6 A5 A4 A3 A2 A1 A0

5.5 Bit Level Logical Operations

A Unique and powerful operation feature of the 8051 microcontroller is
single bit operation. Single bit instructions allow programmer to Set, Clear,
Move and Complement individual bits of a port, memory or register. Bit
operators yield compact program code that enhances program execution speed.
In 8051 some registers, a portion of RAM and I/O Ports are bit addressable.

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Instruction Function
SETB Bit Address Addressed bit set to 1
CLR Bit Address Addressed bit cleared to 0
CPL Bit Address Addressed bit complemented

Internal RAM bit Addressable

The availability of individual bit addresses in internal RAM makes the use of
RAM very efficient when storing bit information. Whole bytes do not have to be
used up to store one or two bits of data.
Of the 128-byte Internal RAM of the 8051, only 16 bytes of it addressable.
The bit addressable locations are 20h to 2Fh.

Example
SETB 05
The bit addressable RAM locations start from 20H. The 6th bit of RAM
location 20H is set to 1.

SFR Bit Addresses

All the special function registers (SFRs) may be addressed at the byte level
by using the direct address assigned to it, but some of the SFRs are addressable
at bit level. The bit addressable SFR and the corresponding bit addresses are as
follows;

SFR
Name HEX
Address
Accumulator
E0H F0H D0H
A E E6 E5 E4 E E E1 E0
7 3 2
B8H B0H A8H
Register
F7 F6 F5 F4 F3 F2 F1 F0
B A0H 98H
D D D5 D D D D1 D
PSW 7 90H
6 4 3 2 0
Interrupt Priority BF88H
BE BD B B BA B9
C B
PORT 3 P3 80H
B7 B6 B5 B4 B3 B2 B1 B0
Interrupt Enable IE
AF AE A A AB A A9
PORT 2 P2 D C A

SCO A7 A6 A5 A4 A3 A2 A1 A0
9F 9 9 9 9 9 99
N PORT 1 E D C B A
P1 97 96 95 94 93 92 91 90
TCO

N PORT
7
B
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t

A
d
d
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e
s
s

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Bit Addressable Accumulator

SETB ACC.6 ; 7th bit of Accumulator is set to 1
CLR ACC.7 ; 8th bit of Accumulator is set to 0

Bit Addressable I/O Ports

The 8051 has 4 I/O ports P0, P1, P2 and P3, each of 8 bits.
We can access either the entire 8 bits on any single bit without altering the
rest.
To access a port in a single bit, the syntax is
SETB Port number. Pin number
Port numbers are P0 for Port 0, P1 for Port 1, P2 for Port 2 and P3 for Port
3. Port pin numbers are 0 to 7.
Port's Bit P0 P1 P2 P3
D0 P0.0 P1.0 P2.0 P3.0
D1 P0.1 P1.1 P2.1 P3.1
D2 P0.2 P1.2 P2. P3.2
D3 P0.3 P1.3 P2.3 P3.3
D4 P0.4 P1.4 P2.4 P3.4
D5 P0.5 P1.5 P2.5 P3.5
D6 P0.6 P1.6 P2.6 P3.6
D7 P0.7 P1.7 P2.7 P3.7

Example
i) SETB P1.3; Port 1 Pin 3 is set to 1
ii) CLR P2.6; Port 2 Pin 6 cleared to 0
Bit Addressable Program Status Word

7 6 5 4 3 2 1 0
CY AC F0 RS1 RS0 0V ---- P
Program Status Word(PSW)

PSW.0 - P (Parity Flag) Shows the parity status of Accumulator

PSW.1 - Reserved for future use
PSW.2 - 0V (Over flow flag) Used in arithmetic function. When the result of
an arithmetic function is more than 8 bits in size, the OV flag set to 1.
PSW.3 - RS0 Register Bank select Bit 0
PSW.4 - RS1 Register Bank select Bit 1

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 RS0 RS1 Selected Register Bank
0 0 Register Bank 0
0 1 Register Bank 1
1 0 Register Bank 2
1 1 Register Bank 3
By default, RS0 and RS1 are set to 0 to select Register Bank0.
PSW.5 - F0 User Flag 0.
PSW.6 - AC Auxiliary Flag use in BCD arithmetic
PSW.7 - CY Carry Flag use in arithmetic functions.

Example
To select Register Bank 2, RS0 = 0 and RS1 = 1
SETB PSW.4
CLR PSW.3

Carry Bit related instructions

Instruction Function
SETB C Make CY = 1
car C Clear carry bit. CY = 0
CPL C Complement Carry bit
MOV bit, C Copy carry to bit status
MOV C, bit Copy bit status to carry
JNCRel Jump to Relative address if C = 0
JC Rel Jump to Relative address if C = 1
ANL C, bit AND CY with Bit and result in C
ANL C, /bit AND CY with complement of Bit and store
result in C
ORL C, bit OR CY with Bit and result in C
ORL C, /bit OR CY with complement of Bit and store
result in C

ANL C, Source bit

In this instruction the carry flag bit is ANDed with a source bit and the
result is placed in carry.

Example 1
Write a program to clear the accumulator if both bits P2.1 and P2.2 are
high, otherwise make accumulator FFh.

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MOV A, #0FFh; A = FFh

MOV C, P2.1; CY = P2.1
ANL C, P2.2; P2.2 and CY are ANDed. If both are 1 then
; Carry C is 1, otherwise 0
JNCOVER ; Jump to B1 if carry is not 1
CLR A ; If carry is 0 clear accumulator.
OVER:

Example 2
Write a program to clear the accumulator if P2.1 is high and P2.2 is low,
otherwise make accumulator FFh.
MOV A, #0FFh; A = FFh
MOV C, P2.1; CY = P2.1
ANL C, /P2.2; P2.1 ANDed with complement of P2.2
JNCOVER ; Jump to B1 if carry is 0
CLR A ; If carry is 0 clear accumulator.
OVER:

MOV destination bit, Source bit

This move instruction copies the source bit to the destination bit. In this
instruction one of the operands must be the Carry 'C'.

Example
MOV P1.2, C; State of carry bit is loaded to port 1 pin 2.
MOV C, P2.5; State of port 2 pin 5 is loaded to carry bit.

ORL C, Source bit

In this instruction the carry flag bit is ORed with a source bit and the result
is placed in the carry flag. Therefore, the carry flag bit is set to 1 if the source bit
is 1 otherwise carry flag is unchanged.

Write a program to clear the accumulator if P2.1 or P2.2 is high, otherwise

make
accumulator FFh.
MOV A, #0FFh; A = FFh
MOV C, P2.1; CY = P2.1
ORL C, P2.2; P2.2 and CY are ANDed. If both are 1 then
; Carry C is 1, otherwise 0

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 JNCOVER ; Jump to B1 if carry is not 1
CLR A ; If carry is 0 clear accumulator.
OVER:

5.6 Arithmetic Instruction Flags

There are four arithmetic instruction flags available in 8051
microcontrollers. There are Carry flag (CY)
1. Auxiliary carry flag (AC)
2. Overflow flag (OV)
3. Parity flag (PF)
The CY, AC and OV flags are Arithmetic flags. They are set to 1 or cleared to
0 automatically depending on the result of the Arithmetic Instructions.
The parity flag (pf) is affected by every instruction executed. The Parity Flag
will be set to1 if the number of 1s in the A register is odd and will be set to 0 if
the number of 1s in the A register is even.

5.7 Addition
Addition of two 8-bit numbers in 8051 involves the Accumulator (A
Register) to store the result of Addition. i.e., A register is used as a destination
Register. The source can be an immediate number, a Register, a direct address
and an indirect address.

There are two types of addition

i) Unsigned addition and
ii) Signed addition

Unsigned Addition
Unsigned numbers are defined as data in which all the bits are used to
represent data, and no bits are set aside for the positive or negative sign. This
means that the operand or data can be between 00h and FFh (i.e. 0 to 255
decimal).
Adding two unsigned numbers generates a carry flag (CY) when the sum
exceeds FFh. Auxiliary carry flag (AC) is set when there is a carry from bit D3
i.e. carry from lower nibble to higher nibble. Overflow flag (OV) is not used in
unsigned addition.

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Example
Decimal Hex. Binary
95 5Fh 01011111
189 BDh 10111101
284 1Ch
ALU of 8051 adds the above number as follows
01011111
10111101
carry 1 0 0 0 1 1 1 0 0 ==> 284 d
In the above example, there is carry from bit D6 to bit D7. Therefore, carry
flag (CY) set to 1. This shows that the sum is more than 255d and the carry is to
be adjusted as with the sum as 9-bit result. Since the 9-bit result cannot be
stored in single byte, the sum with carry is stored in two registers as 16-bit
data. The sum should be stored in one register as lower byte result and the
carry in another byte as higher byte result.

Signed Addition
Signed numbers are defined as data in which the MSB of the 8-bit data i.e.
D7 bit is used to represent the sign of the number. This means that the numbers
of size 0 to +127d can be represented as positive numbers. Numbers of size 0 to
-127d can be represented as negative numbers.
Representation of +ve numbers in signed form
i) + 5 ==> 0 0 0 00 1 0 1 D7-bit is 0 = +ve number
ii) + 32 ==>0 0 0 10 0 0 0 D7-bit is 0 = +ve number

Representation of -ve numbers in signed form

The magnitude of negative number is represented in its 2's Complement
form.
-5 can be represented as follows,
5 ==>0 0 0 00 1 0 1
1 1 1 11 0 1 0 (1's Complement of 5)
1 (+)
2' Complement 1 1 1 11 0 1 1 ==> FBh
In hex number -5 decimal is represented as FBh.
Addition of singed numbers involves the overflow flag (OV) and carry flag
(CY). Overflow

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Flag (OV) is set to 1 if either of the following two conditions occurs:
i) There is a carry from D6 to D7 but no carry from D7.
ii) There is a carry from D7 but no carry from D6 to D7.
Logically OV is expressed as follows. Overflow Flag is set when carry 6(C6)
XOR carry 7(C7).
OV = C6 XOR C7.
When OV set to 1, it indicates that the result of addition exceeds the largest
positive or negative number i.e. +127 to -127, and the result is not in true form.
The result should be in 9-bit. The result in A register is 8-bit only. To adjust the
sum to true form, the following action are to be taken by the programmer
depending on the status of Carry and Overflow flags.

Carry Overflow Action

Flag (CY) Flag (OV) To taken
0 0 None
0 1 Complement the sign.
1 0 None
1 1 Complement the sign.

Example
Add -1d with +27d.
-01(+)
+27
+26
-1d Should be loaded into 8051 in 2's complement form.
2' Complement of -1 is
11111110 1's complement of 1
1 (+)
1 1 1 1 1 1 1 1 2's complement of 1
-1d = 1 1 1 1 1 1 1 1 (2's Complement form of 1)
+27d = 0 0 0 1 1 0 1 1(+)
0 0 0 1 1 0 1 0 ==> 1Ah = +26
Carry flag (AC) = 1 (Carry from D7)
Overflow Flag (OV) = 0(Carry from D7, No carry from D6)
From the above table 3.1, it shows that the sum is true value and no
adjustment required.

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Example 2
Add +100d to +50d.
+100d ==> 64h
+ 50d ==> 32h
+150d ==> 96h
1(Carry from D7)
+100d = 0 1 1 00 1 0 0 (+)
+ 50d = 0 0 1 10 0 1 0
0 1 0 0 10 1 1 0
Carry flag (CY) = 0(No Carry from D7)
Overflow Flag (OV) = 1(Carry from D6, No carry from D7)
The Overflow flag is set to 1 indicates that the sum is not in true form. From
the result we can see that the D7 is 1. It shows that it is negative number which
is not true. The sum should be adjusted as per the table 3.1. The whole 8-bit is
taken as sum and the sign bit is complement of D7.
So, the adjusted result is 0 1 0 0 1 0 1 1 0 ==> +150 = 96h
Sign Data

Example 3
Add -30d with -50d.
30d =00011110
1's complement of 30d is 1 1 1 0 0 0 0 1
1(+)
2's Complement of 30d = 1 1 1 0 0 0 1 0 = E2h Same way,
2's Complement of 50d = 1 1 0 0 1 1 1 0 = ECh
-30d ==> E2h (2's complement of -30d)
-50d ==> CEh (2's complement of -50d)
-80d ==> 1B0h
1111
-30d = 1 1 1 0 0 0 1 0 (2's complement of 30d)
-50d = 1 1 0 0 1 1 1 0(+) (2's complement
of 50d)
1 1 0 1 1 0 0 0 0 ==> B0h = -80d
Carry flag (CY) = 1(Carry from D7)
Overflow Flag (OV) = 0(Carry from D6 and Carry from D7)
From the table 3.1, the overflow flag OV is 0 and carry flag CY is 1 the sum is
true value and no adjustment is needed. The accumulator content is in 2's
complement form of 80d.

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Example 4
Add -70d with -70d.
30d =01000110
1's complement of 70d is 1 0 1 1 1 0 0 1
1(+)
2's Complement of 70d = 1 0 1 1 1 0 1 0 = BAh
-70d ==> BAh (2's complement of -70d)
-70d ==> BAh (2's complement of -70d)
-140d ==> 17Ah
111
-70d = 1 0 1 1 1 0 1 0 (2's complement of 30d)
-70d = 1 0 1 1 1 0 1 0(+) (2's complement
of 50d)
1 0 1 1 1 0 1 0 0 ==> 74h
Carry flag (CY) = 1(Carry from D7)
Overflow Flag (OV) = 1(No Carry from D6 and Carry from D7)
From the table 3.1, The Overflow flag is set to 1 indicates that the sum is not
in true form. From the result we can see that the D7 is 0. It shows that it is
positive number which is not true. The sum should be adjusted as per the table
3.1. The whole 8-bit is taken as sum and the sign bit is complement of D7.
So, the adjusted result is 1 0 1 1 1 0 1 0 0 ==> 74h = -140d
Sign Data
The instruction used for addition of two 8-bit data can be given as,
ADD A, Source
Source - Immediate data or data in register.

Program of adding two 8-bit numbers:

MOV A, #0F5h; A = 75h
ADD A, #0Bh; A = 75h + 0Bh = 80h
75h ==> 01110101
0Bh ==> 0 0 0 0 1 0 1 1(+)
1 0 0 0 0 0 0 0 = 80h
CY = 0 OV = 0
After addition of two 8-bit data A = 80h.

5.8 Addition two 16-bit data

Since the architecture of 8051 is 8-bit, a 16- bit data required two bytes.
Lower byte is stored in one register/memory location and higher byte is stored

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in next register/memory location. Same way two 16-bit data are stored in four
register/memory location.
Initially the carry is to be cleared. To add 16-bit data first the lower bytes
are be added and the result is stored in a register/memory location. Then the
higher bytes are be added with the carry from first result. The sum in
accumulator is moved next to the lower byte result.

Example
A program to add two 16-bit numbers. The numbers are 3CE7h and 3B8Dh.
Place the sum in R6 and R7.
Higher Lower
Byte Byte
1
3C E7
3B 8D (+)
78 74

Program of adding two 16-bit numbers

CLR C ; Carry flag is cleared
MOV A, #0E7h ; A = E7h
ADD A, #8Dh ; A + 8Dh = 74h and CY = 1
MOV R6, A ; R6 = 74h
MOV A, #3Ch ; A = 3Ch
ADDC A, #3Bh ; A + 3Bh + CY = 78h
MOV R7, A ; R7 = 78h
ADDC instruction is used to add two data bytes along with the status of
Carry flag.

5.9 Subtraction
In microprocessor systems, subtraction is done by taking the 2's
complement of the number to be subtracted the subtrahend, and adding it to
another number the minuend. But in 8051 direct subtraction of two numbers is
possible. 8051 uses SUBB instruction for direct subtraction. Register A is the
destination address for subtraction, the source can be an immediate data, a data
in register, a data in direct address and data in an indirect address.
There are two types of subtraction.
i) Unsigned Subtraction
ii) Signed Subtraction

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Unsigned Subtraction
In unsigned subtraction all 8-bits are used for magnitude. The carry flag CY
is used as a borrow flag in subtraction. The Barrow flag CY should be set to 0
before starting subtraction of two 8-bit numbers. Overflow flag is not taken in
to account while doing unsigned subtraction.
If the source number is smaller than the number in A, the result will be in
true form with barrow flag is 0. If the source number is more than the number
in A, the result is a negative number. The barrow flag is set to 1 indicating that
the result is not in true form but in 2's complement form.

Example
Subtract 100d from 15d (15d - 100d).
15d (-) ==> 0 0 0 0 1 1 1 1 ==> 0Fh (-)
100d ==> 0 1 1 0 0 1 0 0 ==> 64h
- 85d ==> 1 1 0 1 0 1 0 1 1 ==> 1 ABh
Borrow flag =1
Since Barrow flag is set to 1, the answer is a negative number. Negative
number is always not in true form but in 2's complement form. Result ABh is 2's
complement of 85d or -85d = ABh.

Signed Subtraction
When numbers of like signs are subtracted, the result will not exceed
positive or negative magnitude limits of +127d or -128d and so the magnitude
and the sign of the result do not need to be adjusted. When unlike sign numbers
are subtracted the result may exceed the limit of 7-bit. When the result is more
than the limit, the over flow flag set to 1. Like signed addition, same action to be
taken. Refer table 3.1.
Example 1
Subtract +126d from 100d (100d - 126d).
Sign. Data
+100d (-) ==> 0 1 1 0 0 1 0 0 ==> 64h (-)
+126d ==> 0 1 1 1 1 1 1 0 ==> 7Eh
- 26d ==> 1 1 1 1 0 0 1 1 0 ==> 1 ABh
Borrow flag = 1
Overflow flag = 0 (Borrow to D7 and Borrow to D6)
Since the overflow flag is not set, the result is in true form. Result is -26d ==
ABh.

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Example 2
Subtract -116d from -061d (-061d - (-116d)).
-061d (-) ==> C3h (-) (2's Complement of 61)
-116d ==> 8Ch (2's Complement of 116)
+ 55d ==> 037h
-06d is represented in hex. as follows,
61d ==> 00111101
1's Complement of 61d ==> 1100 0010
1(+)
2's Complement of 61d 1 1 0 0 0 0 1 1 ==> C3h
-116d is represented in hex. as follows,
116d ==> 01110100
1's Complement of 116d ==> 1000 1011
1(+)
2's Complement of 116d 1 0 0 0 1 1 0 0 ==> 8Ch
Sign. Data
- 61d (-) ==> 1 1 0 0 0 0 1 1 ==> C3h (-)
-116d ==> 1 0 0 0 1 1 0 0 ==> 7Eh
+ 37d ==> 0 0 0 1 1 0 1 1 1 ==> 0 37h
Borrow flag = 0
Overflow flag = 0 (Borrow to D7 and Borrow to D6)
Since the overflow flag is not set, the result is in true form. Result is +37d ==
37h.

Example 3
Subtract +100d from -099d (-099d - (+100d)).
-99d (-) ==> 9dh (-) (2's Complement of 91)
+100d ==> 64h
-199d ==> 0 39h
-99d is represented in hex. as follows,
99d ==> 01100011
1's Complement of 99d ==> 1001 1100
1(+)
2's Complement of 99d 1 0 0 1 1 1 0 1 ==> 9Dh
Sign. Data
- 99d (-) ==> 1 0 0 1 1 1 0 1(-) ==> 9Dh (-)
+100d ==> 0 1 1 0 0 1 0 0 ==> 64h
-199d ==> 0 0 0 1 1 1 0 0 1 ==>0 39h

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 Borrow flag = 0
OV flag = 1(No Borrow to D7 and Borrow to D6)
Since the overflow flag is set, the result is in not true form (See the result.
The Sign bit is 0, indicating + 39, which is not true). The sum has to be adjusted
as per table 3.1. The sign bit D7 should be complemented. The sum is an 8-bit
data.
So, the adjusted result is 1 0 0 1 1 1 0 0 1 ==> 39h = -199d
Sign Data

Example 4
Subtract -52d from +87d (87d - (-52d)).
+87d (-) ==> 57h (-)
-52d ==> CCh (2's Complement of 51)
+139d ==> 1 8Bh
-52d is represented in hex. as follows,
52d ==> 00110100
1's Complement of 52d ==> 1100 1011
1(+)
2's Complement of 52d 1 1 0 0 1 1 0 0 ==> CCh
Sign. Data
+87d (-) ==> 0 1 0 1 0 1 1 1(-) ==> 57h (-)
-52d ==> 1 1 0 0 1 1 0 0 ==> CCh
+139d ==> 1 1 0 0 0 1 0 1 1 ==> 1 8Bh
Borrow flag = 0
Overflow flag = 1 (Borrow to D7 and No Borrow to D6)
Since the overflow flag is set, the result is in not true form (See the
result Sign bit is 1 indicating the sum is negative, which is not true.). The
sum has to be adjusted as per table 3.1. The sign bit D7 should be
complemented. The sum is an 8-bit data.
So, the adjusted result is 0 1 0 0 0 1 0 1 1 ==> 8Bh = +139d
Sign Data

Sample Program
CLR C ; CY = 0
MOV A, #3Fh ; A = 3Fh
MOV R3, #23h ; R3 = 23h
SUBB A, R3 ; A = 3Fh - 23h = 1Ch
; Flags CY = 0 AC = 0

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 Microprocessor and Microcontroller

3Fh (-) ==> 00111111

23h ==> 00100110
1Ch ==> 0 0 0 0 1 1 1 0 0

5.10 Multiplication
Multiplication operation use registers A and B as both source and
destination address for the operation. The 8051 supports byte by byte
multiplication only. The bytes are assumed to be unsigned data. The instruction
used for multiplication operation is as follows:
MUL AB ; Multiplies A by B and place the 16-bit
; result in registers B and A.
In byte by byte multiplication, one of the operands must be in register A and
the second operand must be in register B. After multiplication, the 16-bit result
is stored in registers A and B. The lower byte is in A and upper byte in B.
Before start of multiplication operation, carry flag is always cleared to 0.
The largest possible product is FFh x FFh. So, the largest possible result is
FE01h (FFh x FFh = FE01h). If the result of product is less than FFh, the result is
stored in register A only. If the result of product is more than FFh, the lower
byte result is stored in register A and upper byte result in register B. This
occasion the overflow flag is set to 1. So whenever overflow flag is set to 1, the
programmer should check the register B for upper byte result.

Sample Program 1
MOV A, #7Bh ; A = 7Bh
MOV b, #02h ; B = 02h
MUL AB ; 7Bh x 02h = F6h
7Bh x ==> 123d x
02h ==> 2d
F6h ==> 246d
Since the result F6h is less than FFh (246 < 255), the result is stored in
register A only and the overflow flag is 0.

Sample Program 2
MOV A, #7Bh ; A = 7Bh
MOV b, #0FE2h ; B = FEh
MUL AB ; 7Bh x FEh = 7A0Ah
7Bh x ==> 123d x
FEh ==> 254d

21
 7A0Ah ==> 31242d
Since the result 7A0Ah is more than FFh (31242 >255), the lower byte
result 0A is stored in register A and upper byte result 7Ah is stored in register B
and the overflow flag is 1.

5.11 Division
Division operation use registers A and B as both source and destination
address for the operation. The 8051 supports byte by byte division only. The
bytes are assumed to be unsigned data. The instruction used for division
operation is as follows:
DIVAB ; Divide A by B
In byte by byte multiplication, the numerator must be in register A and the
denominator in register B. After division the quotient is in the register A and
the remainder in register B. The denominator should not be 0. If the
denominator is 0, the overflow flag is set to 1 indicating that the division is
undefined. If the denominator is not 0, the overflow flag is 0 and CY is also 0.

Sample Program
MOV A, #95 ; A = 95d
MOV B, #10 ; B = 10d
DIVAB ; 95 / 10 , A = 9 and B = 5.
In the above program decimal 95 is loaded in A and decimal 10 is loaded in
B. After the instruction DIV AB is executed the quotient is stored in A and the
remainder is stored in B.

5.12 Binary coded decimal (BCD) Arithmetic

In BCD four bits are required to represent a decimal number from 0 to
9(0000 to 1001). Such numbers are called Binary Coded Decimal (BCD)
numbers. There are two types of BCD numbers.
i) Unpacked BCD
ii) Packed BCD

Unpacked BCD
In unpacked BCD, a decimal number is represented in an 8-bit binary. The
lower 4 bits shows the decimal number and the upper 4-bits are 0s.
Example 9 ==> 0 0 0 0 1 0 0 1
5 ==> 0 0 0 0 0 1 0 1

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 Microprocessor and Microcontroller

Packed BCD
In packed BCD two decimal numbers are represented in an 8-bit binary
number or in a byte. The lower 4-bits shows the unit digit and the upper 4-bits
shows the ten digits.

Example
59h ==> 0 1 0 1 1 0 0 1 59

Addition of BCD numbers

8051 Adds two BCD number like normal addition. So, the Adding two BCD
numbers results in a non-BCD number. To make the result to a BCD number 6
must be added to lower nibble or higher nibble. The instruction used to adjust
the result to BCD number is,
DAA ; Adjust for BCD addition
The added result should be placed in A register. Then only DA instruction
will work on A register. This instruction always assumes the numbers were in
BCD before the addition was done.
There are two flags are affected and they are Auxiliary carry flag (AC) and
Carry flag (CY). When lower nibble is more than 9, the Auxiliary flag (AC) set to
1 and when the higher nibble is more than 9, the Carry flag (CY) set to 1.

Simple program 1
Write a program to add two BCD numbers 17 and 28. Result should be in
BCD form.
Packed BCD number for 17 is 17h
Packed BCD number for 28 is 28h
MOV A, #17h ; A = 17h
ADD A, #28h ; A = 17h + 28h
DA A ; Adjust the result to BCD.
17h ==> 0 0 0 1 0 1 1 1 (+)
28h ==> 00101000
45h ==> 00111111
Flag AC is 1 (Lower nibble is more than 9)
Flag CY is 0 (Higher nibble is less than 9)
Since the AC flag is set to 1, the DAA instruction adds 6 to the lower nibble
and stores the result in A register.
0 0 1 1 1 1 1 1(+)
00000110

23
 0 1 0 0 0 1 0 1 ==> 45h
The result 45 is stored in A register in BCD form as 45h.

Simple program 2
Write a program to add two BCD numbers 52 and 87. Result should be in
BCD form.
Packed BCD number for 52 is 52h
Packed BCD number for 87 is 87h
MOV A, #52h ; A = 52h
ADD A, #87h ; A = 52h + 87h
DA A ; Adjust the result to BCD.
52h ==> 0 1 0 1 0 0 1 0 (+)
87h ==> 10000111
139h 1 1 0 1 1 0 0 1 ==> D9h
Flag AC is 0 (Lower nibble is 9)
Flag CY is 1 (Higher nibble is more than 9)
Since the CY flag is set to 1, the DA A instruction adds 6 to the higher nibble
and stores the result in A register.
1 1 0 1 1 0 0 1(+)
01100000
1 0 0 1 1 1 0 0 1 ==> 139h
The result 139 is stored in A register and B register. 39h in A as packed BCD
form and 1h in B as unpacked BCD.
The DA A instruction to be used only with BCD addition. When DA A
instruction is used, 8051 assumes the numbers added are in BCD. This
instruction will work only with ADD and ADDC instructions. It will not work
with other Subtraction, Multiplication and Division instructions

5.13 Arithmetic Operation Used by 8051.

Mnemonic Byte Machine Cycle
ADDA, Rn 1 1
ADDA, direct 2 1
ADDA, @Ri 1 1
ADDA, #Data 2 1
ADDC A, Rn 1 1
ADDC A, Rn 1 1
ADDC A, direct 2 1
ADDC A, @Ri 1 1
ADDC A, #Data 2 1

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 Microprocessor and Microcontroller

SUBB A, Rn 1 1
SUBB A, direct 2 1
SUBB A, @Ri 1 1
SUBB A, #Data 2 1
INC A, 1 1
INC Rn 1 1
INC direct 2 1
INC @Ri 1 1
DEC A, 1 1
DEC Rn 1 1
DEC direct 2 1
DEC @Ri 1 1
INC DPTR, 1 2
MUL AB 1 4
DIV AB 1 4
DA A 1 1

5.14 LOGICAL Operation Used by 8051.

Mnemonic Byte Machine Cycle
ANL A, Rn 1 1
ANL A, direct 2 1
ANL A, @Ri 1 1
ANL A, #data 2 1
ANL direct, A 2 1
ANL direct, #data 3 2
ORL A, Rn 1 1
ORL A, direct 2 1
ORL A, @Ri 1 1
ORL A, #data 2 1
ORL direct, A 2 1
ORL direct, #data 3 2
XRL A, Rn 1 1
XRL A, direct 2 1
XRL A, @Ri 1 1
XRL A, #data 2 1
XRL direct, A 2 1
XRL direct, #data 3 2
CLR A 1 1
CPL A 1 1

25
 RL A 1
RLC A 1 1
RR A 1
RRC A 1 1
SWAP 1

5.15 Data Transfer Instructions Used by 8051

Mnemonic Byte Machine Cycle
MOV A, Rn 1 1
MOV A, direct 2 1
MOV A, @Ri 1 1
MOV A, #data 2 1
MOV Rn, A 1 1
MOV Rn, direct 2 2
MOV Rn, #data 2 1
MOV direct, @Ri 2 2
MOV direct, #data 3 2
MOV @Ri, A 1 1
MOV @Ri, direct 2 2
MOV @Ri, #data 2 1
MOV DPTR, #data(16) 3 2
MOVX A, @Ri 1 2
MOVX A, @DPTR 1 2
MOVX @Ri, A 1 2
MOVC @DPTR, A 1 2
PUSH direct 2 2
POP direct 2 1
XCH A, Rn 1 1
XCH A, direct 2 1
XCH A, @Ri 1 1
XCHD A, @Ri 1 1

5.16 Boolean Variable Instructions Used by 8051

Mnemonic Byte Machine Cycle

CLR C 1 1
CLR bit 2 1

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 Microprocessor and Microcontroller

SETB C 1 1
SETB bit 2 1
CPL C 1 1
CPL bit 2 1
ANL C, bit 2 2
ANL C, /bit 2 2
ORL C, bit 2 2
C, /bit 2 2
MOV C, bit 2 1
MOV bit, C 2 2
JC rel 2 2
JNC rel 2 2
JB bit, rel 3 2
JNB bit, rel 3 2
JBC bit, rel 3 2

5.17 Program Branching Instruction

ACALL addr11 2 2
LCALL addr16 3 2
RET 1 2
RETI 1 2
AJMP addr 11 2 2
LJMP addr 16 3 2
SJMP rel 2 2
JMP @A+DPTR 1 2
JZ rel 2 2
JNZ rel 2 2
CJNE A, direct, rel 3 2
CJNE A, #data, rel 3 2
CJNE Rn, #data, rel 3 2
CJNE @Ri, #data, rel 3 2
DJNZ Rn, rel 2 2
DJNZ direct, rel 3 2
NOP 1 2

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5.18 Loop Instructions
Repeating a sequence of instructions, a certain number of times is called a
loop. In 8051, the loop action is performed by the instruction,
DJNZ reg, Label
In this instruction, the register is decremented one from a loaded number. If
the result is not 0, the program jumps to the target address referred by the
label.

Sample Program
MOV a, #0 ; A = 0 Clear the accumulator
MOV R2, #10 ; R2 = 10d
Again:
ADD A, #03 ; A = A + 03d = 03d
DJNZ R2, AGAIN
MOV R5, A ; Store the result in R5. R5 = 30
In the above program R3 register is used as counter. R2 is set to 10 initially.
In labelAGAIN, the accumulator gets add with 3. The contents of register are
decremented one by the instruction DJNZ R2. The loop is repeated till R2
becomes 0. There are 10 loops because 10 is loaded in R2. So, 10 times 3 is
added in Accumulator. Hence the result 30.

Jump Instructions
There are two types of Jump instructions used in 8051. They are,
i) Conditional jump instructions
ii) Unconditional jump instructions

Conditional Jump Instructions

These instructions check a condition and depending on the status of the
condition control is transferred to some label. Al conditional jumps are short
jumps, which means that the address of the target label must be within -128 to
+127 bytes of the contents of the program counter.
Some conditional jump instructions used in 8051 are:
Instruction Action
JZ label Jump to label address if A = 0
JNZ label Jump to label address if A is not equal to 0
DJNZ Rn, label Decrement Rn and jump to label if Rn # 0
JC label Jump to label address if Carry flag = 1

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 Microprocessor and Microcontroller

Instruction Action
JNC label Jump to label address if Carry flag = 0
JB bit, label Jump to label if bit = 1
JNB bit, label Jump to label if bit = 0
JBC bit, label Jump to label if bit = 1 and clear bit to 0

Instruction 1
JZ label ; Jump to label address if A = 0
In this instruction the content of register is checked. If it is 0, it jumps to the
address of label. Otherwise it goes to next instruction.
MOV A, R0 ; A= R0
JZ OVER ; Jump to label OVER if A = 0
MOV a, R1 ; A = R1
JZ OVER ; Jump to label OVER if A = 0

Over
In the above program, if either R0 or R1 is 0, it jumps to the label OVER.
This instruction is only to check the contents of register A.

Instruction 2
JNClabel ; Jump to label address if Carry CY = 0
In this instruction the Carry bit CY in Program Status Word (PSW) is
checked. If it is 0, it jumps to the address of label. Otherwise it goes to next
instruction. This instruction is mainly used in arithmetic operations.
MOV A, #0 ; A= 0
MOV R5, A ; A= R5
ADD A, #79h ; A = 0 + 79h = 79h
JNC OVER ; Jump to label OVER if C = 0
INC R5 ; Increment R5, R5 = R5 +1
OVER: ADD A, #0F5h A = A + F5h
In the above program, The Carry flag CY is cleared to 0. It jumps to the label
OVER and adds next data F5h. Incise if carry is set to 1 the register R5 will
incremented by one.

Unconditional Jump Instructions

The unconditional jump is a jump in which control is transferred
unconditionally to the target location. In 8051 there are two unconditional
jump instructions. They are

29
 1. LJMP (Long Jump)
2. SJMP (Short Jump)

LJMP (Long Jump)

Ljmp is an unconditional long jump. It is a 3-byte instruction in which the
first byte is the op-code and the other two bytes represent the 16-bit address of
the target location. The two-byte target address allows a jump to any memory
location from 0000h to FFFFh.

SJMP (Short Jump)

Sjmp is an unconditional short jump. It is a 2-byte instruction in which the
first byte is the opcode and the other byte represent the 8-bit address of the
target location. The 8-bit target address allows a jump to any memory location
from 00h to FFh.

Forward and Backward Jump

Forward jump refers to the transfer of control from the current address of
the Program Counter (PC) to a positive displacement. Address 0 to +127 bytes.
Backward jump refers to transfer of control from the current address of the
Program Counter(PC) to a negative displacement. Address 0 to -128 bytes.

5.19 Call and Subroutine

Subroutines are separate program segments used to perform tasks that are
need to be performed frequently. Subroutines are used to make the program
more structured and to save memory space. It avoids repeating of same
program. There are some instructions in 8051 which are used to call a
subroutine and they are,
1. LCALL (Long Call)
2. ACALL (Absolute Call)

LCALL (Long Call)

LCALL is a 3-byte instruction in which the first byte is the opcode and the
other two bytes represent the 16-bit address of the target label of subroutine.
Therefore, LCALL can be used to call subroutines located from 64K bytes of
memory space. (0000h to FFFFh). This instruction transfers the control to the
subroutine program and after the execution of subroutine it come back to the
instruction immediately below the LCALL. Whenever the processor executed

30
 Microprocessor and Microcontroller

the instruction LCALL, it automatically saves the address of the instruction

immediately below LCALL to the Stack.
Every subroutine has the last instruction RET. This instruction transfers the
control back to the address specified by the stack memory location. Address of
the stack memory location is hold by the stack pointer.

Sample Program
Write a program to toggle all the bits of port 1 by sending it the values 55h
and AA continuously. Add time delay between each toggle operation.
.org 0

Back
MOV A, #55h ; A = 55h = 0 1 0 1 0 1 0 1
MOV P1, A ; P1 = A = 0 1 0 1 0 1 0 1
LCALL DELAY ; DELAY subroutine is called
MOV A, #0AAh ; A = AAh = 1 0 1 0 1 0 1 0
MOV P1, A ; P1 = A = 1 0 1 0 1 0 10
LCALL DELAY ; DELAY subroutine is called
SJMP BACK
ORG 3000h

Delay
MOV R5, #0FFh ; R5 = FFh = 1 1 1 1 1 1 1 1
AGAIN: DJNZ R5, AGAIN ; Decrement R5. Repeat till R5 = 0
RET
END
In the above program the alternative pins of port 1 is set to 1 by loading
55h. After loading to port 1 a subroutine delay is called which is in address of
3000h. This subroutine is used to generate a time delay. During this delay the
port 1 pins hold the data. In this DELAY subroutine the register R5 is loaded
with FFh. DNJZ R5 makes a loop. This instruction decrement R5 and the loop is
repeated till R5 becomes 0. When R5 becomes 0, The next instruction is
executed where LCALL subroutine is called. It loads AAh to port 1, which means
toggle all port 1 pins. Again, the subroutine DELAY is called. The same action is
repeated again and again by the jump instruction SJMP BACK.

31
ACALL (Absolute Call)
ACALL is a 2-byte instruction in which the first byte is the opcode and the
second byte represent the 8-bit address of the target label of subroutine.
Therefore, aCALL can be used to call subroutines located from 2K bytes of
memory space. (00h to FFh). Like LCALL instruction, this instruction also
transfers the control to the subroutine program and after the execution of
subroutine it come back to the instruction immediately below the ACALL.
Whenever the processor executed the instruction ACALL, it automatically saves
the address of the instruction immediately below ACALL to the Stack.
ACALL subroutine has the last instruction RET. This instruction transfers
the control back to the address specified by the stack memory location. Address
of the stack memory location is hold by the stack pointer.

5.20 8279 Programmable Key Board and Display Interface

The 8279 is a general-purpose programmable keyboard / display interface
specially developed for processors. The 8279 has two sections namely
keyboard section and display section. The function of the keyboard section is to
interface the keyboard which is used as input device for the processor (CPU).
The purpose of the display section is to drive LED’s some important features
are simultaneous keyboard display operations, scanned sensor mode, scanned
keyboard mode, 8 – character keyboard FIFO, strobed input entry mode, 2 – key
lock out or N – key roll over with contact debounce, single 16 – character
display, dual 8 or 16 numerical display, interrupt output on key entry,
programmable scan timing and mode programmable from CPU.

Signal description of 8279

The 8279 is a 40 pin DIP IC. The pin diagram and signal flow diagram are
shown in figure 5.16a

32
 Microprocessor and Microcontroller

RL2 RL3 CLK IRQ RL4 RL5 RL6 RL7 VCC RL1 RL0
RESET CNTL/STB SHIFT SL3
RD WR DB0 DB1 DB2 SL2 SL1
DB3 DB4 SL0 OUT B0
DB5 DB6 DB7 OUT B1 OUT B2 OUT B3
VSS OUT A0
OUT A1 OUT A2
OUT A3 BD
CS
A0

8
2
7
9

Fig 5.1a - Pin diagram of 8279

Vss Vcc

IRQ RL 7 - RL
0
DB7 -
DB0 KEY
SHIFT
DATA
RD 8 CNTL/STB
2 SCAN
SL 3 - SL
WR 7
9 0 DISPLAY
A0 DATA
OUT
RESET A3 -
A0
CLK OUT
B3 -
B0
BD

CS

Fig 5.1b - Signal flow diagram of 8279.

Bi-directional data bus (DB7 – DB0)

These are 8-bit lines used for data transfer between 8279 and the CPU.
Common words are also transmitted through these lines.
Read (RD)
It is an active low signal which enables the read operation.
Write (WR)
It is an active low signal which enables the write operation.
Reset
When this pin is set in high it resets the 8279.

33
Clock (CLK)
The clock signal is used to generate internal timing for the system.
Interrupt Request (IRQ)
When this line goes to high indicates that a valid key data is available in the
FIFO RAM.
Return Lines (RL7 – RL0)
These lines are inputs to 8279. They are connected to the columns of the
matrix keyboard. These lines have active internal pull-up resistors to keep high
until a switch closure pulls one of the lines low.
Buffer Address (A0)
When this line goes low it indicates data transfer takes place. a high on this
line indicates command word.
Chip Select (CS)
It is an active low signal, which enables the communication between 8279
and processor (CPU).
Shift
The shift line reads the status of shift key of the key board.
The control line reads the status of control key. It is high until a switch
closure pulls it low. In the strobed input mode this line acts as a strobe line that
enters the data into the FIFO RAM.

Scan Lines (SL3 – SL0)

These four scan lines are used to scan the key switch or sensor matrix and
the display digits.

Display outputs Out A0 – Out A3 and Out B0 – Out B3

These 8 output lines (two 4-bit output ports) provide the 8 – bit segment
information for the display digits.

5.21 Block diagram of 8279

The block diagram of 8279 is shown in figures. It consists of four major
sections. They are
1) Key board section
2) Display section
3) Scan section
4) CPU interface section

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 Microprocessor and Microcontroller

Return

SHIFT
Deboun
Keybo
Sensor
FIFO/

ard
A

FIFO/Sen
sor RAM
8x8

Sc
an
RD
WR

Buffer
DATA

Timin
Contr
ol &

Timi

B
ng
16 x 8

Displ
pla
Dis

8
ay

Out A0
- A3
Disp

Addr
lay

Fig. 5. 2 Block Diagram of 8279

Key board section
The Key board section includes return buffers, key board debounce and
control and 8 x 8 FIFO / Sensor RAM. The return lines RL0 – RL7 are used to
form the columns of a key board matrix. It has two additional inputs shift and
control / strobe. The key board debounce and control unit debounce the key
board entries. The two operating modes of key board section and 2 keys lock
out and N – key roll over. In the 2 – key lock out mode, if two keys are pressed
simultaneously, only the first key is re-cognized. In the N – key roll over mode
simultaneously keys are recognized and their codes are stored in FIFO RAM.
The key board section also hasan 8 x 8 FIFO (First In first out) RAM. The 8 x
8 FIFO RAM can store eight key board entries. The status of the shift key and
control key are also stored along with key code. When a key is pressed, the
corresponding 8 – bit key code is loaded into the first location of the FIFO RAM.

35
Then the interrupt request line (IRQ) is made high to indicate that the FIFO
RAM is not empty.

Display section
The display section consists of 16 x 8 display RAM and display address
registers. The display address registers hold the address of the word currently
being writer or read by the CPU and two 4 – bit nibbles being displayed.
The 8279 can drive a maximum of 16 display digits. the 16 x 8 (16 numbers
of 8-bit buffer RAM) display RAM holds the 8 – bit data for 16 display digits.
The 16 display digits are multiplexed.
The display section of 8279 has eight output lines divided into two groups
Out A0 – A3 and Out B0 – B3. These lines provide the 8 – bit segment
information for the display digits. The blank line BD is used to blank the display.

Scan section
The scan section consists of a scan counter and four scan lines (SL0 – SL3).
This scan counter can be operated in two modes namely encoded mode and
Decoded mode. In encoded mode, the counter provides a binary count which
can be decoded to provide the scan lines for the key board or display. (i.e.). The
scan lines periodically output 0 to 15).
In the decoded mode the scan counter itself is a decoder. (That is the least
significant two bits are decoded and decoded outputs are available in the scan
lines SL3 – SL0).
The four scan lines are common to key board and display. These lines are
used to form the digit drivers of a multiplexed display and the rows of a matrix
key board.

CPU Interface section

The CPU interface section consists of Data buffer, I/O control, control and
timing registers, One Interrupt Request line (IRQ). The data buffer has 8 – bit bi
– directional data lines DB7 – DB0 to transfer data between 8279 and the CPU
of the processor. The I/O control signals RD, WR, CS, and A0 are used for read /
write data to 8279. The 8279 has an interrupt request line (IRQ). this signal is
used to interrupt the processor to indicate the availability of data.

Programming of 8279
The 8279 can be programmed to perform various functions through eight
command words. D5, D6 and D7 are the code of command word.

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 Microprocessor and Microcontroller

Key board / Display mode set(Code 000)

D7 D6 D5 D4 D3 D2 D1 D0

0 0 0 D D K K K

Code

Where DD specifies the display mode and

KKK specifies the keyboard mode.
DD
0 0 8 No. of 8-bit character display mode - left entry
0 1 16 No. of 8-bit character display mode - left entry
1 0 8 No. of 8-bit character display mode - right entry
1 1 16 No. of 8-bit character display mode - right entry
KKK
000 - Encoded Scan keyboard - 2 key lockout
001 - Decoded Scan keyboard - 2 key lockout
010 - Encoded Scan keyboard - N key Roll over
011 - Decoded Scan keyboard - N key Roll over
100 - Encoded Scan sensor matrix
101 - Decoded Scan sensor matrix
110 - Strobed input, Encoded display scan
111 - Strobed input, Decoded display scan

Program Clock(Code 001)

D7 D6 D5 D4 D3 D2 D1 D0

0 0 1 P P P P P

Code
Where P P P P P are the prescaler value from 2 to 31. The programmable
prescaler divides the input clock to get basic internal frequency around
100KHz, so that the specified scan and debounce times are obtained.

37
Read FIFO / Sensor RAM(Code 010)
D7 D6 D5 D4 D3 D2 D1 D0

0 1 0 AI X A A A

Code
Where X is don’t care, AI stands for auto increment and AAA is sensor RAM
address. 3-bit of AAA is used to address eight location of FIFO/Sensor RAM.
This command sets up the 8279 to read the FIFO/Sensor RAM and used in the
case of sensor matrix mode.

Read display RAM(Code 011)

D7 D6 D5 D4 D3 D2 D1 D0

0 1 1 AI A A A A

Code
Where AI is for auto increment flag and AAAA is the address of display
RAM. 4-bit of AAAA is used to address 16 locations of display RAM. This
command sets up the 8279 to read the display RAM.

Write Display RAM(Code 100)

D7 D6 D5 D4 D3 D2 D1 D0

1 0 0 AI A A A A

Code
Where AI is for auto increment flag and AAAA is the address of display
RAM. 4-bit of AAAA is used to address 16 locations of display RAM. This
command sets up the 8279 to write the display RAM.

Display write inhibit / blanking(Code 101)

D7 D6 D5 D4 D3 D2 D1 D0

1 0 1 X IW IW BL BL

CODE

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 Microprocessor and Microcontroller

Where IW is for inhibit write and BL stands for blank. This command is
used to inhibit writing in A or B nibble of the display RAM and to blank the
display selectively.

Write Display RAM(Code 110)

D7 D6 D5 D4 D3 D2 D1 D0

1 1 0 CD CD CF CF CA

CODE
Where CD is clear display, CF is Clear FIFO Status and CA is clear all. This
command is used to clear the display RAM and the FIFO status at the time of
initialisation. The display RAM can be set to all ones, all zeros are hex 20 as
follows,

CD CD CD
1 0 X All zeros
1 1 0 AB = 20h (0010 0000b)
1 1 1 All ones
0 X X Inhibit clear display

End Interrupt(Code 111)

D7 D6 D5 D4 D3 D2 D1 D0

1 1 1 E X X X X

CODE
Where X is don't care. In the sensor matrix mode, this command lowers the
INT line and enables further writing into RAM. In the N key roll over mode, this
command forces the chip in a special error mode if the E bit is set to 1.

5.22 Interfacing Stepper Motor

Stepper motor is a special type of DC motor. For every electrical pulse given
stepper motor rotates certain no. of degrees. It is used in digital control systems
such as robotics, dot matrix printers, disk drives etc. The stepper motor has a
permanent magnet rotor shaft surrounded by a stator. The stator windings are
energised by electrical pulses. The most common stepper motors have four
stator windings. Series of pulses are applied to the input of stator windings. The

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axis of air gap magnetic field setup around according to the input pulses. The
axis of rotor magnetic field follows the stator axis of air gap magnetic field.
The direction of rotation is formed by the stator poles. When the polarity of
stator windings is changed the direction of the current also changed and
causing the reverse rotation of rotor. The sequence of pulses applied to each
stator winding, the direction of rotating is determined. Degree of rotation is
determined by the no. of stator poles and no. of rotor poles.

A A

Average North
N N
N S
C S N D C S N D
N
S
Average South
S S

B B
Fig. 5.3 Rotor alignment in stepper motor

From the figure the switching is called 4-step switching sequence. After
completing a sequence, the same windings will be ON and rotation continuous.
No. of steps per revolution is depend upon the degree of rotation. degree of
rotation = 360 degree / no. of rotor pole x no. of stator poles

A COM COM
B
C
D

Fig. 5.4 Stator winding in stepper motor

Example
No. of rotor poles = 5
No of stator poles = 4
Degree of rotation = 360o/ 5 x 4
= 18o
No. of steps/revolution = 360/18
= 20 steps

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 Microprocessor and Microcontroller

Interfacing Stepper Motor

Since the 8051 lacks sufficient current to drive the stepper motor windings,
we must use a driver to energize the stator. Instead we could have used
transistors as drivers. The port of 8051 is buffered and connected to stator
winding of stepper motor through separate drivers. The sequence of pulses is
programmed to determine the direction of rotation. The clockwise and anti-
clockwise rotations are done by changing the steps sequence of the stator
windings.
8051 ULN Stepper Motor
2003
1 16
P
2 15
1.
3 14
0
4 13
P

CO COM
M +5V
Fig 5.5 Interfacing Stepper motor to 89C51

Software Design
Program to rotate the stepper motor continuously. Stepper motor
connected to 89C51.
MOV A, #66h ; Load step sequence in Accumulator

Back
MOV P1, A ; Issue sequence to motor
RR A ; Rotate right clockwise
ACALL STEP ; Goto subroutine called STEP
SJMP BACK ; Continue the rotation
STEP: ; This subroutine is to determine the delay between
steps.
MOV R2, #64h ; 100 decimal loaded in R2
S1: MOV R3, #FFh ; 255 decimal loaded in R3
S2: DJNZ R3, S2 ; Keep decrement R3 to 0
DJNZ R2, S1 ; Keep decrement R2 to 0
RET

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5.23 Interfacing DC Motor
The microcontroller-based DC motor speed control system is shown in fig.
To measure the speed of the motor, a circular disk with several slots is attached
to the spindle of the motor. An LED and photo transistor assembly are used to
generate pulse train with frequency related to the speed of the motor. Each
rotation of the spindle, the photo transistor is obstructed to the light emitted by
the LED n times. Where n is the number of slots on the circular disk. By using a
suitable pulse shaper, it is converted into a TTL compatible square wave. The
square wave is applied to 89C51 through RXD pin. No. of square waves are
counted to measure the speed of motor.
To alter the speed a variable DC voltage is applied to the armature of motor.
Variable DC voltage is generated with a help of DAC. Input to the DAC should be
programmed in 89C51. The desired speed is set by program. The 89C51 keep
varying input to DAC till measured speed is equal to desired speed. Measured
speed and desired speed are displayed in LED display.

SDK - 85
8155
+5V TIMER IN
PA 0 - 7

LED

PULSE SHAPER AND LED DRIVER

PHOTO TRANS

Q1 +5V

MOTOR DRIVER
DC MOTOR
DAC

Fig. 5.6 Speed Control of DC motor

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