Microprocessor and Microcontroller

UNIT IV MICROCONTROLLER 8051

4.1 Introduction
Microprocessors are playing an important role in various industries and
influencing our day-to-day life more strongly than one can imagine. Basically,
microprocessor is a single chip Very Large Scale Integrated (VLSI) digital
circuit. The term microprocessor comes from the merger of micro-electronics
technology. Microprocessor is defined as Arithmetic Logic Unit (ALU) and
Control Unit (CU) on a single chip. The Central Processor Unit (CPU) consists of
an Arithmetic Logic Unit (ALU) and Control Unit (CU), So microprocessor can
act as CPU. To have a minimum system configuration, microprocessor should
be connected with external memory, I/O ports etc.
Similarly, the microcontroller can be defined as a complete microprocessor
system on a single chip which includes the CPU (microprocessor), Memory
(RAM, ROM), I/O ports, Serial interface etc. Microcontrollers are developed to
replace the microprocessor in low cost products.

4.2 Block Diagram of Microcontroller

I/O Port
AL

I/O Port

Internal ROM
Interr
upt
Circu

Cloc
kt

Program Counter

Fig. 4.1 Block diagram of Micro Controller

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 Fig. 4.1 shows the block diagram of a typical microcontroller, which is a true
computer on a single ship. It has all features found in a microprocessor CPU,
ALU, Program Counter, Stack Pointer and Registers. In added to the above
feature, it has internal ROM, RAM, Parallel I/O ports, Serial I/O port and timers.
Like microprocessor it is a general-purpose device, which reads the data,
perform limited calculations and logical operations and control the
environment based on the result of calculations/logical operations.
The important use of a microcontroller is to control the operation of
machines using a program stored in ROM memory and does not change its
operation over the life time of the system.
Many of the instructions are coupled with pins on the integrated circuit
package. Thus, the pins are programmable, which means pins of
microcontroller are accessible by the programmer and can be set as per the
requirement.

Architecture of Microcontroller 8051

The Intel 8051 is an 8-bit single chip 40 pin Dual in Package (DIP) IC. It is
available in N channel metal oxide (CMOS) silicon construction. It is designed
for complicated real time instrumentation and industrial controls. It operates
on 12MHz clock and single +5V supply.
Fig. 1.4 shows the architecture of 8051 microcontroller. It shows all the
features such as memories, I/O ports, Timers, Serial data communication,
Interrupt control, registers etc.

CPU
Microcontroller 8051 has an 8-bit CPU. It consists of Accumulator (A
Register), B register, Arithmetic Logic Unit (ALU) and Control Unit (CU). It is
used to perform basic mathematical calculations and Logical operations. 8051
CPU can process 8-bit data only.

Memory
The 8051 has internal RAM and ROM memories. 128 bytes of RAM and
4Kbytes of ROM are available with 8051. Internal RAM has 4 register banks
each having 8 registers.

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I/O Ports
8051 consist of four 8-bit ports. They are port 0, port 1, port 2 and port 3.
These ports can be programmed either input or output port. These ports are
arranged in thirty-two input/output pins.

Timer/Counter
There are two timers timer 0 and timer 1 provided in 8051. Both timers are
16 bits wide. Timers are programmed to generate desired time delays.

Registers
In the CPU of 8051, registers are used to store information temporarily.
The majority of 8051 registers are 8-bit registers. Some of the widely used
general purpose registers are A (Accumulator), B, R0, R1, R2, R3, R4, R5, R6, R7,
Data Pointer and Program Counter. Only two registers Data pointer (DPTR)
register and Program Counter (PC) are 16-bit wide.

Special Function Registers or Control registers

A group of specific internal registers use for some special functions is called
Special Function Registers (SFR). SFRs hold the control bits of ALU operation,
Port operation, Timer operation, Serial communication, Interrupt Control,
Memory management etc.
Addresses of SFRs are between 80h and FFh. Typical SFRs are TCON, TMOD,
SCON, PCON, IP and IE.

Oscillator and Clock Circuit

The 8051 has an on-chip oscillator but requires an external resonant tank
circuit to determine the clock frequency. Normally the external resonant tank
circuit is a quartz crystal and two 30PF capacitors. The crystal circuit is
connected to pins XTAL1 and XTAL2. The crystal frequency is the basic clock
frequency i.e. 12MHz. Clock pulses generated are used to synchronise the
internal operations.

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 VCC VSS

Program Address Register

Program Counter Internal ROM
DPTR Buffer

P1.1 tO P1.7 P2.1 tO P2.7 P0.1 tO

Po
La
Fig. 4. 1 Architecture of
ACC Stack Pointer

Po
La
B
Register
PCON SCON TMODTCON
Temp 2 Temp 1
1

TH1 TL1 TH0 TL0

Microprocessor and
Po
SBUF SBUF Serial
IE Port
IP and Timer Blocks

La
Interrupt,
ALU

PSEN PSW
ALETiming

La
Instruc

Po
EA and Control

tion
RST

Osc

Fig. 1.4 ARCHITECHTURE OF MICRO CONTROLLER 8051

 Dr. N. Karuppiah & Dr. S. Ravivarman

XTAL2 18
C1
8051
Crystal

XTAL1 19
C2

P2 P1 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2
P2

State 1 State 2 State 3 State 4 State 5 State 6 One Machine Cycle

Address
Latch
Enable(ALE 8051 Timing
)
Fig. 4.2 Crystal Oscillator Circuit

Interrupts
There are five interrupts available in 8051, in which three are internal
interrupts and two are external interrupts. Three internal interrupts are timer
0(TF0), timer 1(TF1) and serial I/O port (RI or TI) interrupts. Two external
interrupts are INT0 and INT1.

Serial Data Communication

The 8051 transfers and receives data serially at many different baud rate
(Data transfer of bits per second). In 8051 the Serial communication is in full
duplex mode. If the data are transmitted and received simultaneously is called
full duplex mode. Two 8-bit SBUF registers are used to have full duplex mode.
One SBUF is used for Transmission and another SBUF is used for reception.

4.3 8051 Pin Configuration

The 8051 microcontroller is packaged in 40 pin dual in line package (DIP).
Out of 40 pins, 16 pins are single function pins and 24 pins may be used for one
or two entirely different function.

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Port 1 Bit 0 1 P1.0

+ 5V
Port 1 Bit 1
Port 0 Bit 0
Port 1 Bit 2
Port 0 Bit 1
Port 1 Bit 3
Port 0 Bit 2
Port 1 Bit 4
Port 0 Bit 3
Port 1 Bit 5
Port 0 Bit 4
Port 1 Bit 6
8
0 Port 0 Bit 5
Port 1 Bit 7
5 Port 0 Bit 6
Reset i/p 1 Port 0 Bit 7
Port 3 Bit 0
External
Port 3 Bit 1
Enable
Port 3 Bit 2
Address Latch
Port 3 Bit 3
Enable Program
Port 3 Bit 4 Store Enable Port 2
Port 3 Bit 5 Bit 7
Port 3 Bit 6 Port 2 Bit 6
Port 3 Bit Port 2 Bit 5
7 Crystal Port 2 Bit 4
i/p2 Port 2 Bit 3
Crystal Port 2 Bit 2

i/p1 Port 2 Bit 1

Groun Port 2 Bit 0

d

Fig. 4.3 Pin Diagram of 8051

Single Function Pins (16 Pins)

Pin No. Designation Function
20 Vss Supply Pin, Ground
40 Vcc Supply Pin, +5V
9 RST Reset Input
18, 19 Xtal1, Xtal2 Crystal Input Pins
29 PSEN Program Store Enable
30 ALE Address Latch Enable
31 EA External Enable
1 to 8 P1.0 to P1.7 I/O pins Port 1
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Dual Function Pins (24 Pins)

I/O PORT
AD0 - AD7

Internal Bus
I/O PORT

I/O PORT A8 - A15

I/O PORT

Alternate
function

Fig. 4.4 Dual Function Pins

Out of 32 I/O lines of four ports, 8 lines of port 1 are used as single I/O
function only. The remaining 24 pins of port 0, port 2 and port 3 are used for
dual functions. Port 0 pins used for I/O function and lower address and data
multiplexed port for external memory. Port 2 pins used for I/O function and
higher address for external memory. Port 3 pins used for I/O functions and
Alternative uses.

Vcc
Pin 40 provides supply to the chip. The voltage source is +5V.

GND
Pin 20 is Ground.

Xtal1 and Xtal2

External crystal with two 30PF capacitor is connected to these pins. The
crystal frequency determines the basic clock frequency of 8051.

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RST
Pin 9 is RESET pin. It is an active high input pin and normally low. Upon
applying a high pulse to this pin, 8051 terminate all activities and go to reset
condition.

EA
Pin 31 is External enable pin (EA). When this pin is connected to Vcc, the
CPU access internal memory. When EA pin connected to ground, the CPU access
the program/data from external memory.

PSEN
This is an output pin. PSEN stands for Program Store Enable. An active low
pulse in this pin enables the external ROM. This pin is connected to OE of
external ROM chip.

ALE
This is an active high output pin. ALE stands for Address Latch Enable. ALE
used to demultiplex the lower byte address of external memory and data from
port 0. When ALE is high, port 0 is connected to external memory address latch.
When ALE is low, port 0 carries the data.

Program Counter (PC)

The Program Counter (PC) is a 16-bit pre-settable up counter used as a
memory pointer. The Program Counter (PC) keeps track of program execution.
To execute a program, the starting address of the program is loaded in Program
Counter (PC). The instruction in an address pointed by the PC is fetched and
executed by the CPU. When an instruction is fetched from memory, the
Program Counter (PC) is automatically incremented by one to point the next
location of memory where next instruction/data is stored.

Data Pointer (DPTR)

Data pointer is a 16-bit register made up of two 8-bit registers. They are
Data Pointer Higher order byte (DPh) and Data Pointer Lower byte (DPl)
registers. DPTR holds a 16-bit address of external memory. This register is
under control of program instructions and can be specified by its 16-bit name
(DPTR) of 8-bit name (DPh or DPl). DPTR does not have single internal address,
DPh and DPl are assigned separate address.

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General Purpose Registers

8051 has 34 general purpose working registers.

Accumulator (A register)
The Accumulator (A register) is used for many operations like Addition,
Subtraction, Multiplication, Division and Boolean bit logical operations. It is also
used for data transfer between 8051 and external memories, I/O devices.

B Register
The B register is used to do arithmetic operations with A register. B register
may be used to store the data and it has no other functions.
Flags register, Program Status Word (PSW)
Flags are single bit register and used to store the result of certain function
after executing instruction. Flags are grouped inside PSW and PCON registers.
PSW register contains math flags and PCON contains general user flags. Math
flags are grouped in PSW and they are Carry(C), Auxiliary Carry (AC), Over flow
(OV), and Parity (P). The general user flags are GF0 and GF1 which are grouped
in PCON register.
7 6 5 4 3 2 1 0

CY AC F0 RS1 RS0 0V ---- P

Program Status Word(PSW)

Fig. 4.5

Bit Symbol Function

0 P Parity Flag
1 -- User Definable Bit
2 OV Overflow Flag
3 RS0 Register Bank Select Bit 0
4 RS1 Register Bank Select Bit 1
5 F0 User Flag
6 AS Auxiliary Carry Flag
7 CY Carry Flag

Carry Flag (CY)

This flag bit is used in arithmetic, jump, rotate and Boolean instructions.
This flag is set whenever a carry is obtained.

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Auxiliary Carry Flag (AC)

This flag bit is used in BCD arithmetic operations. This flag is set whenever
a carry is obtained in bit 4. This flag is considered only for BCD addition,
otherwise the status of flag is ignored.

Parity Flag (P)

This parity flag bit is used to show the number of 1s in the accumulator
only. If the accumulator register contains an odd number of 1s, then this flag set
to 1. If accumulator contains even number of 1s, then this flag cleared to 0.

Overflow Flag (OV)

This flag bit is used to detect errors in signed arithmetic operations. This
flag is set whenever the result of signed number operation exceeds 7 bits,
causing the higher order bit to overflow into the sign bit.

4.4 Internal Memory Organisation

For the CPU to process information, the data must be stored in RAM or
ROM. 8051 has internal 128 bytes RAM and 4Kbytes ROM for these functions.
RAM is called data memory and ROM is called program memory. Although both
RAM and ROM uses same address, the selection of memory depends upon the
instruction used. This type of architecture is called Harvard Architecture.

Internal RAM
8051 has 128-byte internal RAM and called data memory. RAM is a read-
write memory and processor can read data or write data to this memory space.
These 128 bytes are divided into three groups and they are Register Banks, Bir
addressable registers and General purpose. Internal organisation of RAM is
given in fig. 1.9
There are four register banks available in 8051 are Bank 0, Bank 1, Bank 2
and Bank 3. By default, or on reset Bank 0 is selected. To select other Banks RS0
and RS1 in PSW is to set accordingly. Unselected register banks are used for
general purpose. The address of four register banks occupies from 00h to 1fh.

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7F
2F
7F
Genera 2E 7F 78
l 77 70
30 Purpos
e Area 6F 68
2D 67 60
Bit
2F Addressabl 5F 58
2C
e Area 2 57 50
B
Registe 4F 48
20 r Bank
1F 47 40
3 29 3F 38
18 Registe 28 37 30
r Bank
2 27 2F 28
10 Registe 26 27 20
0F
r Bank 25 1F 18
1
24 17 10
08 R7
R6 0F 08
07 23
06 R5 07 00
05 22
R4 30
04 R3
BIT ADDRESSABLE GENERAL PURPOSE
R2 RAM LOCATIONS
21 RAM LOCATIONS
R1
03
02 Register20
01 Bank 0
00

Fig. 4.6 Internal RAM Organisation

Addresses from 20h to 2Fh are bit addressable area. A bit in this area may
specified by its bit address. Addressable bits are useful when the program need
to set or reset a single function (On or OFF).
Address from 30h to FFh are used as general-purpose area. Locations in
this area can be addressed byte wise.

Internal ROM
8051 has 4Kbyte of ROM. Program memory (ROM) is read only memory.
The CPU reads program from this memory and execute it. CPU cannot write
data inside this memory. Address of internal ROM is from 000h to FFFh. Above
these address the CPU will access external memory.

4.5 The Stack and Stack Pointer

The stack is a section of internal RAM used by the CPU to store information
temporarily. This information could be data or an address. The CPU needs this
storage area since there are only limited number of registers. The register to
access the stack is called Stack Pointer. It is an 8-bit register and it can point an
address location between 00h to FFh. Stack pointer is used to hold the address
of Top of the Stack. The address held in the SP is the location in internal RAM

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where the last byte of data was stored by a stack operation.

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CPU Action CPU Action

Store Data SP = OA SP = OA
SP = OA Get Data

SP = 09
Store Data SP = O9
Get Data
SP = O9

SP = O8
Store Data
Get Data
SP = O8 SP = O8

SP = 07

SP = O7 SP = O7
Storing Data on the
Stack (Increment Internal Getting Data from the
then store) RAM Stack (Get then
decrement)

Fig. 4.7 Stack Operation

When data is to be placed on the stack, the SP increments one before

storing the data on the stack. When the data is retrieved from the stack, the SP
decrements one after retrieving the data. Detailed stack operation shown in fig.
4.7

4.6 Special Function Registers (SFR)

There are 21 Special Function Registers used in 8051. Addresses of these
SFRs are between 80h and FFh. Not all addresses from 80h to FFh are not used.
The unused addresses are reserved for future use.
Out of 21 Special function registers, eleven are bit addressable registers and
ten are byte addressable registers. Bit addressable SFRs are TCON, SCON, IE, IP,
PSW, ACC, B, P0, P1, P2 and P3. Byte addressable registers are SP, DPh, DPl,
PCON, TMOD, TL0, TH0, TL1, TH1 and SBUF.
Special function register can be either accessed by its name or by its
address. The addresses of the Special function registers are shown in fig.1.8

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Fig. 4.8 Special Function Register

4.7 External Memory

In many systems the internal ROM and RAM is not sufficient. In this case
external RAM and ROM may be used. Since the Program Counter (PC) and Data
Pointer (DP) are 16-bit, maximum of 64Kbytes of external memory can be
added to 8051 system.
The CPU of 8051 address the external memory on two occasions. Firstly,
when the address bus exceeds FFFh and secondly the pin EA is grounded. When
pin EA is grounded internal memory is not addressed. Since same address is
used for both external RAM and ROM the selection of RAM or ROM is done by
instruction method. The control bit PSEN goes low to fetch program from
external ROM. Data cannot be written in this memory. Control bits RD and WR
goes low to enable external RAM. RD signal used to read the data from RAM and
WR used to write data from RAM.

4.8 Input/Output Pins and Ports

The Input / Output sections of 8051 includes four I/O ports. The four ports
are port 0, port 1, port 2 and port 3. Each port is 8-bit port having 8 pins and

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has D-type o/p latch for each pin. The Special Function Register (SFR) for each
port is made up of these eight latches, which can be address for that port. The
port latches should not be confused with the port pins. The data in the latches
does not have to be the same as that on port pins. The data in latch buffer and
the data of ports pins can be read independently. To make any port as input or
output it must be programmed. To make a port as input port, the port latch
should be written with all 1s. By default, the port is defined as output port.
I/O operation of ports (P0, P1, P2, and P3)
I/O operation of all ports i.e. port 0, port1, port 2 and port 3 are same.
Except port 1 all other ports are having alternate function. Each port figures
shows the operation of both I/O operation and alternate function also. Common
figure of all port I/O function are shown in fig. 1.9

Rea
d
Latc
h Contr VCC
ol Extern
Signal al FET
s Pullu
p

Pin 0
Tri State

B Buffer

U Pin 7

S
Contr
Tri SFR ol
State ‘D’
Logic
Buffe Latc
r h

Rea
d
Pin
Fig. 4.9 I/O operation of 8051 Ports

Output Operation
Except port 0 other ports have pull up resistors. Pull up resistor are
connected to Vcc to make the pin high. To make port 0 as output port, external
pull up resistors of 10K are to be connected to port pins. Each port has eight D

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type output latch for each pin. These eight latches are called as port SFR latch.
The data to be sent out is loaded into port SFR latch buffer. Where ever 0s are
loaded in latch, the high output from Q drives the concerned FET drivers

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 Dr. N. Karuppiah & Dr. S. Ravivarman

through control circuit and makes the corresponding pins low. Where ever 1s
are loaded in latch, output of Q is low and the control circuit cut off the FET
driver. The port pins are made 1 by external pull up resistors. Thus, the 0s and
1s written in port latch are transferred to port pins.
Note: It may be noted that the data in latch buffer and port pins may not be
the same always. There are two sets of tri-state buffers used to read the latch or
pin. When upper set of tri-state buffer is enabled by read latch signal, the latch
data are transferred to internal bus. When the lower set of tri-state buffer is
enabled by read pin data signal, the data of pin are transferred to internal bus.

Input Operation
When a port to be used as an input port, all 8-bits of port latch are to be
programmed with 1s. If a pin is to be set as input pin then corresponding latch
bit is to be set to1. When latch is set to 1, the output of Q is low and FET drivers
are in cut-off state. The pin is in float condition. The data in port pins are
connected to input buffers. When control signal read pin data goes high, the
contents of port are transferred to internal bus.

Port 0
Control Signal Address / Data
Read latch bit

VCC
BUS
D Q
Control Logic Pin
0.x
CLKQ
Write to Latch
PORT SFR Latch

Read pin Data

Fig.4.10 I/O operation of Port 0

Port 0 has dual function as I/O port and Address/Data bus for external
memory. When external memory is not used, port 0 is used as simple I/O port.
When external memory is used, port 0 is used as address bus and data bus.
Lower byte address and data are multiplexed in this port. ALE signal is used to
demultiplex the address from this port. ALE goes high, when this port contains

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address. After addressing ALE goes low and the port become data bus. To read
the data from external memory logic 1 is written to all port SFR latches.
Port 1
Port 1 is not dual function port as port 0. It is used only for simple I/O
operation of data. So, control circuit is not used and the output of SFR latch is
directly connected to FET drivers. The Pin configuration diagram of port 1 is
shown in fig. 1.11
It has internal pull up resistors to drive the output device and no need to
connect external pull up resistors like port 0. The data to be send out is loaded
to the SFR latch of port1.
Read latch bit VCC

BUS
Pin 1.x
D Q

CLK Q
Write to Latch
PORT SFR Latch

Read pin Data

Fig.4.11 Pin Configuration of port 1

Where ever thedata are 0 the Q output of latch is high and drives the FET
driver. The output pin goes low. Where ever data are 1 the Q output of latch is
low and the FET driver is in cut-off condition. The pull up resistor make the
output pin high.
To program the port 1 as input port, the SFR latch buffer should be set to 1.
The low output from the Q of latch isolates the FET drivers and pull up
resistors. The pins of port 1 are connected to input buffer. When read pin signal
enabled, data available in port pins are transferred to internal bus.

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Port 2
Control Signal Address
Read latch bit

BUS VCC
Internal FET
Pullup

D Q Pin 2.x
Control Logic
CLKQ
Write to Latch
PORT SFR Latch

Read pin Data

Fig. 4.12 Pin Configuration of Port 2

Port 2 is similar to port 0 having dual function. In addition to I/O operation

it can address external memory also. When 64K external memory is connected,
16-bit address is required. Lower byte address is carried by port 0 and higher
byte address is carried by port 2. Since data is 8-bit, only address is carried in
this port. I/O operation of this port is like port 0. By default, this port is an
output port. To make this port as input port the port SFR latch buffer should be
set to all 1s.

Port 3

Alternate Output
VCC
Read latch bit
Internal FET
BUS Pullup

D Q Pin
3.x
CLKQ
Write to Latch

PORT SFR Latch

Read pin Data

Alternate Input
Fig. 4.13 Pin Configuration of Port 3

Port 3 is also having dual function. In addition to I/O operation it has

alternate function also. I/O operation of this port is like other ports. Each pin of

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port 3 may be individually programmed either I/O pin or alternate function.

The alternate uses of port 3 is as follows,

Pin Pin SFR

Alternate function
no. name register
P3.0 RXD Serial input data SBUF(RD)
P3.1 TXD Serial output data SBUF(WR)
P3.2 INT0 External Interrupt 0 TCON.1
P3.3 INT1 External Interrupt 1 TCON.3
P3.4 T0 External Timer 0 clock TMOD
P3.5 T1 External Timer 1 clock TMOD
External RAM write
P3.6 WR ----
enable
External RAM read
P3.7 RD ----
enable

4.9 Addressing Modes

The CPU of 8051 can access data in various ways. The data could be in a
register, or in memory, or to be provided as an immediate value. These various
ways of accessing data are called addressing modes.
The 8051 provides a total of five distinct addressing modes. They are as
follows:
1. Immediate addressing mode
2. Register addressing mode
3. Direct addressing mode
4. Register indirect addressing mode
5. Indexed addressing mode

Immediate addressing mode

In immediate addressing mode the source operand is part of the
instruction. The data stored in the immediate next location where the op-code
is stored is transferred to destination. The data must be preceded by the # sign.
This addressing mode can be used to load information into any of the register,
including the DPTR register.

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Simple Example
i) MOV A, #35h; Load the 8-bit hexadecimal number 35
; intoAccumulator (A Register)
ii) MOV R4, #25h; Load the 8-bit hexadecimal number 25
; into register R4
Note
In the above instruction, 25h is loaded into register R4. We do have four
register banks in the internal RAM memory of 8051, starting from Bank 0 to
Bank 3. Each bank consists of 8 register namely R0 - R7. But the default register
bank is bank 0. Hence the 8-bit hex number 25h is loaded into register R4 of
Bank 0.
iii) MOV B, #40h; Load the 8-bit hex. number 40h into
; B register
iv) MOV DPTR, #4521h; Load the 16-bit hex. number
; 4521 into Data Pointer Register (DPTR)
Although the DPTR register is a 16-bit register, it can also be accessed as
two 8-bit registers namely DPh and DPl.
DPL is the low byte register and DPH is the high byte register.
Hence 4521h is loaded into DPTR register as DPL = 21h
and DPh = 45h

DPH( 8 BIT) DPL(8

bit)

45H 21H

The above instruction can also be expressed as

MOV DPL, #21h
MOV DPH, #45h
MOV 3Ah, #65h; The 8-bit data 65h is loaded into
; RAM location 3Ah.
65H 65H

Immediate DATA General Purpose RAM

In the above instruction the data is send immediate to the RAM location
having address as 3Ah.
MOV P1, #55h ; Load the 8-bit hex number 55
; into port P1.

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Register addressing mode

In register addressing mode data transfer takes place between a register to
a destination. The destination can be a register or any RAM memory location.

Simple Example
MOV A, R0 ; Copy the contents of register R0
; into Accumulator.

R7
R6
R5
R4
R3
R2
R1
R0 Accumulator
Register Bank 0

MOV R2, A ; Copy the contents of Accumulator

; (A register) into register R2.

R7
R6
R5
R4
R3
Accumulator R2
R1
R0
Register Bank 0

MOV 56h, A ; Copy the contents of the A register

; in to RAM location 56 h

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 Dr. N. Karuppiah & Dr. S. Ravivarman

7F
7E
7D

Accumulator
55
54
53
36
35
34
33
32
31
30
General Purpose RAM

In register addressing mode, Data can only be moved between register of

same size.

Example
MOV DPTR, A is invalid. Because DPTR is a16 bit register and
Accumulator is an8-bit register. Hence the source and destination registers
must match in size. But this instruction,
MOV DPTR, #3542h
MOV R7, DPL
MOV R6, DPH are valid.
In register addressing mode, data can only be moved between accumulator
and register Rn (where n = 0 to 7). But the movement of data between Rn
register is not allowed.

For Example
MOV R4, R7 is invalid.
In the immediate addressing mode and register addressing mode, the
operands are either tagged along with the instruction itself or inside one of the
registers.

Direct Addressing Mode

Direct addressing mode is used to access the data stored either in RAM or in
register of the 8051 by specifying its address.
In this mode, the data is in a RAM location whose address is known, and this
address is given as a part of the instruction.

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Simple Example
Accessing the contents of Register Bank
The registers R0 to R7 of register bank 0 can be accessed in direct
addressing mode as,
MOV A, 04h ; Copy the contents of RAM
; location 04h (R4 of register
bank ; 0) in to
accumulator
MOV A, 02h ; Copy the contents of RAM
; location 02h (R2 of register
bank ; 0) into
accumulator

Accessing the contents of general-purpose RAM

The memory locations of general-purpose RAM ranges from 30h - 7Fh. Any
data present in these locations can be accessed as
MOV R2, 40h ; Copy the contents of RAM
; location 40h into register R2.
MOV R0, 7Fh ; Move the contents of RAM
; location 7Fh into register R0.
Accessing the contents of special function register
The special function register has addresses between 80h and FFh. The data
in any of the special function register can be accessed by specifying its address.
Example
MOV A, 8Ah ; Copy the contents of TL0(SFR)
; into Accumulator
8AH - Address of TL0(Special function register)

Register indirect addressing mode

In this type of addressing mode, a register is used as a pointer to the data.
Only the registers R0 and R1 are used for this purpose. The registers R2 to R7
cannot be used in this type of addressing mode.
The registers R0 and R1 holds the data addresses of RAM locations from
where the data is to be moved. These registers should be preceded by @ sign.

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Simple Examples
MOV A, @R0 ; Copy the contents of RAM

; location whose address is held by

; register R0 into Accumulator.
R
7
R Accumulator
6
R
5
R
4 40 DATA
H Memory address 40H
R
3
R
2
R
1
R
0
Register Bank
0
ii) MOV B, @R1 ; Copy the contents of RAM
; location whose address is held by
; register R1 in to B
Register.
Advantages
Looping is possible in register indirect addressing mode.

Limitations
The registers R0 and R1 which are used in this mode are 8 bits wide,
therefore their use is limited to access any information in internal RAM (Scratch
pad memory 30h to 7Fh or special function register). The data in external RAM
or in code space of on-chip ROM cannot be accessed.

4.10 External data moves (Indexed addressing mode)

Indexed addressing mode can be used to access data from external memory
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(i.e. external RAM or ROM). Normally we use a MOV instruction to access data
from internal RAM. The external data moves (i.e. from external RAM or from
external ROM) uses MOVX and MOVC instructions.

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Data Bus
ReadWriteReadWrite
A Register Data

External RAM
R0 or R1PC + A Internal and External ROM
PC + A

DPTR
DPTR + A
PC + A
PC + A
PC + A

8051

Accessing data (or) moving data from external RAM

The data moves from external RAM uses MOVX instruction. All the external
data move must involve the Accumulator, or A register. Only the registers R0
and R1 are used to access data from external RAM addresses ranging from 00h
to FFh. For accessing data from higher order addresses ranging from 0000h to
FFFFh, data pointer register (DPTR) can be used.

Simple Example
MOVX A, @R1; Copy the contents of data from external
; RAM location whose 8-bit address is
held ; in register R1 to
A Register.

R1 Register
8 bit address of external RAM location 3AH
External RAM

3AHData

Accumulator
Read data move

8051

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MOVX A, @DPTR ; Copy the contents of data from

; external RAM location whose
; 16-bit address is held in DPTR
to ; Accumulator

DPTR Register
16 bit address
External RAM
of external Rn
AM locatio
4025H
Data
4025H

Accumulator
Read data move

8051

Both the above instructions are referred to as read Data moves i.e., data
from external RAM is moved to accumulator of 8051.

MOVX @DPTR, A ; Copy the contents A register to

; external RAM location whose
; address is stored in Data
pointer ; register
DPTR.

DPTR Register
16 bit address of external RAM location 4025H
External RAM

4025H

Data in Accumulator

Write data move

8051

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MOVX @R0, A ; Copy the contents of Accumulator to

; external RAM location whose address
; is stored in register R0.

R0 Register
8 bit address of external RAM location 3AH
External RAM

3AH

Data in Accumulator

Write data move

8051
Both the above instructions are referred to as write data moves. i.e., the
data from accumulator of 8051 is moved to external RAM.

4.11 Code memory read only data moves

Data move from external ROM to accumulator (A Register) uses MOVC
instruction. The address of the ROM location from where the data has to be
read is given by the instruction, @ A+DPTR, @ A + PC. MOVC instruction
is normally used with internal or external ROM and can address 4K of internal
or 64K of external ROM.

Accessing data from external ROM

Use of data pointer DPTR in read only data move
Instruction MOVC A, @A + DPTR
DPTR - Data pointer holds a 16-bit address or a 16-bit data
Accumulator - Holds an8-bit data
@ A + DPTR - Addition of 16 bits (address or data) in DPTR and 8-bit data
in Accumulator results in another 16-bit address. This newly formed 16-bit
number is the address of the external ROM location from where the data is to
be read.

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Example
MOV DPTR, #2234h ; DPTR = 2234h
MOV A, #66h ; A = 66h
MOVC A, @A + DPTR ; A = 2234h + 66h
: = 229Ah
The contents of ROM location 229Ah is moved to Accumulator.
Use of PC (Program Counter) in read only data move.

Instruction
MOVC A, @A + PC
PC - Program counter holds a 16-bit address. The program counter is
incremented by 1 before it is added to Accumulator's content.
A - Holds an8-bit data
@ A + PC - Addition of 16-bit address in the program counter incremented
by 1- and 8-bit data in Accumulator results in another 16-bit address. This
newly formed 16-bit address is the address of the external ROM location from
where the data is to be read.

Example
MOV A, #60h ; A = 60h
MOVC A, @A + PC
IF the program counter holds an address 4000H then first it is incremented
by 1 before it is added with the 8-bit data in accumulator.
i.e., PC = 4000h + 1 = 4001h

@ A + PC - 4001h + 60h = 4061h

The contents of the external ROM location 4061h is moved to Accumulator.

4.12 Stack in 8051

The stack is a section of RAM used by the CPU to store information
temporarily. This information could be Data or address. The CPU needs this
storage area since there are only a limited number of registers.

Accessing of stack in 8051

The register used to access the stack is called the stack pointer register. The
SP register is only 8-bit wide, which means that it can take values of 00h to FFh.
When 8051 is powered up, the SP register contains value 07. This means that
RAM location 08 is the first location being used for the stack by the 8051. The

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storing of a CPU register in the stack is called a PUSH. The retrieving of the
contents of the stack back into a CPU register is called POP.
In 8051, RAM locations 08H to 1FH can be used for stack. The locations 20H
- 2FH of RAM are reserved for bit addressable registers and must not be used
by the stack. That means the stack in 8051 has only 24 bytes, but by using a
special instruction,
MOV SP, #xx (xx Ranges from 30h - 7Fh)
i.e., the RAM locations from 30h to 7Fh can be also used as stack.

Pushing on to the stack

A PUSH instruction copies data from any of the registers to the stack. The
stack pointer is incremented by 1 before the data is copied to the stack.

Popping of the stack

A POP instruction copies data from the stack location to any of the registers
in the CPU of 8051. The stack pointer is decremented by 1 after the data is
copied to any of the registers.

Example
MOV R6, #32h
MOV R1, #25h
MOV R4, #0A2h
PUSH 6
PUSH 1
PUSH 4
When 8051 is powered up the stack pointer (SP) points to the location 07h
(SP = 07h).
PUSH 6 ; Push the contents of register R6 to stack. Whenever 8051
executes a PUSH instruction the first step involved is the stack pointer (SP)
incremented by 1. Therefore, stack pointer becomes 08H. The 8-bit data 32H is
stored in memory location 08H.
Before PUSH operation
After PUSH 6 operation

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PUSH 1 ; Push the contents of register R1 to stack. Before pushing it to

the stack, Stack pointer (SP) incremented by 1 and becomes 09h. The 8-bit data
25h is stored in stack location 09h.

After PUSH 1 Operation

PUSH 4; Push the contents of register R4 to stack. Before pushing it to the

stack, Stack pointer (SP) incremented by 1 and becomes 0Ah. The 8-bit data
A2h is stored in stack location 0Ah.
After PUSH 4 Operation

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MOV 81h, #30h

MOV R0, #0ACh
PUSH 00h
PUSH 00h
POP 01h
POP 80h
First instruction MOV 81H, #30H loads the 8-bit hex. number 30h into stack
pointer (Address of stack pointer is 81H). i.e., the stack pointer is loaded with
30h. By this instruction addresses above 30h are used as stack.
MOV R0, # 0ACh ; Load the data Ache into register R0
PUSH 00h ; Push the contents of R0(address of R0 is 00H)
into stack. First the stack pointer is incremented by 1 and becomes 31h.
After incrementing by 1, the contents of register R0 i.e., ACH is moved to
stack location 31h.

After Push 00h

The next instruction also PUSH 00h. When this instruction executed, the
stack pointer incremented by one and become 32h. The Contents of register R0
i.e. ACh is move to stack location 32h.

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After PUSH 00h

POP 01h ; Whenever 8051 executes POP instruction, the contents from
the stack location where the Stack Pointer points (Stack Pointer points to the
top of the stack) is moved. i.e., Data ACh in stack location 32h is moved to
R1(01h is address of register R1).
R1 = ACh. After moving the data, the stack pointer decremented by 1 and
becomes 31h.
After POP 01h

POP 80h ; Stack pointer points to the location 31h. The

contents of this location are moved to Port0 (80H is memory address of Port0)
Port 0 = ACh. After moving the data ACh, the stack pointer decremented by 1
and become 30h.
After POP 80h.

Simple program containing both PUSH and POP instructions.

MOV R0, #66h ; R0 = 66h

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MOV R3, #7Fh ; R3 = 7Fh

MOV R7, #5Dh ; R7 = 5Dh
PUSH 0 ; SP = 07 + 1 = 08, Data 66h in R0 moved
; to Stack location 08H. Stack 08h
= 66h
PUSH 3, ; SP = 08 + 1 = 09, Data 7Fh in R3 moved
; to stack location 09h. Stack 09h
= 7Fh
PUSH 7, ; SP = 09 + 1 = 0A, Data 5Dh in R7 moved
; to stack location 0Ah.

POP 0, ; SP = 0Ah. Data 5Dh in stack 0Ah is

; moved to register R0. SP = 0A -
1 = 09h ; and R0 = 5Dh.
POP 7, ; SP = 09h. Data 7Fh in stack 09h is moved to
; register R7. SP = 09 - 1 = 08h
and R7 = 7Fh.
POP 3, ; SP = 08h. Data 66h in stack 08h is moved to
; register R3. SP = 08 - 1 = 07h.
Before executing the program
R0 = 66h
R3 = 7Fh
R7 = 5Dh
After executing the program
R0 = 5d
R3 = 66h
R7 = 7Fh

4.13 Data Exchanges

There is some specific instruction set in 8051which facilitates the exchange
of data between the Accumulator (Register A) and any other register or any
other memory location. These instructions can only exchange the data internal
to 8051 and not externally.

Instruction
XCH A, Source Byte ; The source byte can be any
; register or internal RAM
location.

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Examples
XCH A, R3 ; Exchanges the contents of R3 register with ; Accumulator
XCH A, 40h ; Exchanges the data in memory location 40H ; with
Accumulator
XCH A, @R0 ; Exchanges the contents of a memory location

whose address stored in register R0 with Accumulator

Illustrative Example
MOV A, #65h ; A = 65h
MOV R2, #97h ; R2 = 97h
XCH A, R2 ; Now A= 97h and R2 = 65h

Instruction
XCHD A, @Rn
The XCHD instruction exchanges only the lower nibble of A with the lower
nibble of the data present in RAM location pointed by Rn while leaving the
upper nibble in both places intact.
A nibble consists of 4 bits. Normally a Byte is represented by 8 bits or 2
nibbles as lower nibble and higher nibble.
MOV 40H, #97h; RAM location 40h = 1001 0111(97h)
MOV A, #12h; Accumulator = 0001 0010(12h)
MOV R1, #40h; R1 = 40h (RAM Location)
XCHD A, @R1
R1 points the memory location 40H where the data is stored. The lower
nibble in memory location 40H is exchanged with the lower nibble of
Accumulator. i.e., before the program executed
40H = (97h) 1001 0111
Accumulator = (12h) 0001 0010
After the execution of program,
40H = (92h) 1001 0010
Accumulator = (17h) 0001 0111

4.14 Interrupts and Returns

An interrupt is a hardware or program generated call. Just as an ACALL and
LCALL instructions are used to access the subroutine, similarly an interrupt
sets interrupt flag. This interrupt flag calls a subroutine programmed in

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memory location called interrupt vector. There are five interrupt flags and their
corresponding interrupt vector addresses are as follows;
Interrupt Flag Addresses of interrupt
Flags Name subroutine vectors.
IE0 External interrupt 0 0003h
TF0 Timer 0 overflow flag 000Bh
IE1 External interrupt 1 0013h
TF1 Timer 1 overflow flag 001Bh
R1 or T1 Serial Interrupt flag 0023h
The interrupt subroutine is placed at these memory locations. Whenever an
interrupt flag is set to 1, the Program Counter (PC) suspends the main program
and jumps automatically to the interrupt subroutine vector address without
separate subroutine call. The last instruction of an interrupt subroutine is RETI.
When the interrupt subroutine is executed the RETI instruction clears the
interrupt flag to 0 and resumes the main program where the interrupt occurs.
Interrupt enabled subroutine has the following events:
i) Internal generated or external hardware generated interrupt signal
set the interrupt flags to 1.
ii) When interrupt flag set to 1 the processor suspends the main
program and stores the next address of main program to stack.
iii) The program Counter jumps to interrupt subroutine vector and
activates the interrupt subroutine.
iv) After execution of interrupt subroutine, the RETI instruction reset
the interrupt flag to 0, which was set by the interrupt signal.
v) The processor resumes the main program where the interrupt
suspends the program. The address is taken from the stack.

Sample Program
SJMP OVER
.ORG 0003h ; IE 0 interrupt vector
LJMP XINT ; Jump to label of XINT
.ORG 000Bh ; TF0 interrupt vector
LJMP TINT ; Jump to label TINT
OVER: MOV SP, #40h ; Staring address of stack is 40h
-------
-------
XINT: ------- ; IE 0 Interrupt Subroutine
-------

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RETI
TINT: ------- ; TF 0 Interrupt Subroutine
-------
RETI
END
Assembler directives of 8051
Some widely used 8051 directives are as followers:

ORG (origin)
The ORG directive is used to indicate the beginning of the address. The
number that comes after ORG can be either in hex or in decimal. Some
assemblers use '' .ORG '' instead of ''ORG'' for the origin directive.

EQU(Equate)
This is used to define a constant without occupying a memory location. The
EQU directive does not set aside storage for a data item but associates a
constant with a data label so that when the label appears in the program, its
constant value will be substituted for the label.

For example
count EQU 25
-------
MOV R3, # count
whenever the label count appears in the program segment it is replaced by
a constant value 25.

End
This indicates the assembler the end of the source (ASM) file. The end
directive is the last line of an 8051 program, meaning that in the source code
anything the end directive is ignored by the assembler. Some assembler used ''
END'' instead of '' END''.

4.15 Timer / Counter

In earlier days the control circuit of electrical machines used to have
pneumatic timers. These pneumatic timers are two types as ON delay timer and
OFF delay timer. Present days electronic timers are replaced pneumatic timers.
Electronic timers are more accurate, reliable and efficient than pneumatic
timers. PLC based control circuit, Microprocessor based control circuit and

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Microcontroller based control circuits are using electronic timers.

Microcontroller 8051 based control circuit is much cheaper and easy to handle
than PLC based control circuit and Microprocessor based control circuit.
Microcontroller 8051 has two timer/counters namely timer 0 and timer 1.
Size of each timer is 16 bits wide. Since the architecture of 8051 is 8 bits, the
timers are separated into two 8bit registers. The timer 0 is divided into low
byte of timer 0 (TL0) and high byte of timer 0 (TH0). Same way timer 1 as TL1
and TH1.

Timer 0 divided as

TH0 TL 0
HIGHER 8 BIT LOWER 8 BIT

Timer 1 divided as

TH1 TL 1
HIGHER 8 BIT LOWER 8 BIT
Fig 4.14 Timer Registers

The timer registers TL0, TL1, TH0 and TH1 can be addressed by its location
like any other registers A, B, Rn etc. The addresses of timer registers TL0, TH0,
TL1, TH1 and Special Function Register related to timer TMOD and TCON are
given in fig. 1.15.

TH1 8DH
TH0 8CH
TL1 8BH
TL0 8AH
TMO 89H
D 88H
TCO FUNCTION
TIMER SPECIAL
REGISTER AND ADDRESSES
Fig. 4.15 Timer SFRS and Addresses

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Each timer clock or by external clock. When internal clock is used, it is

called Timer and when external clock is used it is called as Counter.

Timer / Counter Operation

The control logic diagram of Timer shown in figure.Timer 0 and Timer 1 are
presettable and any 16-bit can be loaded. If the timer is loaded with any 16-bit,
then the timer will start counting from that 16-bit to FFFFh. The 16-bit should
be loaded in to two bytes as higher byte and lower byte. The lower byte should
be loaded into TL0/1and higher byte to TH0/1. For example, to load 3820h in
to timer, 20h should be loaded into TL0/1 and 38h should be loaded into
TH0/1.
MOV TL0, #20H ;20H loaded to TL0 of timer 0
MOV TH0, #38H ;38H loaded to TH0 of timer 0

Internal Clock
12

Timer Enable
C/T = 0
Timer 0 or 1Timer Flag
External Clock
T0 or T1
C/T = 1
TR0 or TR1
in TCON

Gate in TMOD

INT0/1
Fig. 4.16 Logic diagram of Timer

Timer can be addressed by its location also. The above instruction can be
written as follows,
MOV 8AH, #20H ;8AH is address of TL0
MOV 8CH, #38H ;8CH is address of TH0
When timer 0 enabled it will start counting from 2038h to FFFFh. Both
timers are controlled by two special function registers TMOD and TCON
registers. The TMOD register is a byte addressable and only used to set the
modes of both timers. TCON register has control bits and over flow flags for
both timers.

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TMOD (Timer Mode) Special Function Register

Gate C/T M1 M0 Gate C/T M1 M0
Timer1 Timer 0
Fig.4.17 TMOD Special Function Register

The lower nibble of TMOD register is used to set the mode of Timer0 and
the higher nibble is used to set the mode of Timer1.
Gate: (Timer enable bit internal/external)
By referring fig. 4.3 the Gate bit in TMOD register is set to enable timer.
When Gate is set to 0 by the programmer, the timer is start and stop by control
bit TR1/0 in TCON register. Gate set to 0, the timer is start and stop by external
control signal INT0/1.
C/T: (Counter/ Timer Bit)
This bit is used to select the clock pulse to timer registers. C/T cleared by 0.
When C/T is set to 1, the timer is receiving clock frequency from external pins
T0/1(P3.5&P3.4) and act as counter.
M0 & M1:(Mode selection Bits)
These bits are used to set the operation modes of timers. Lower nibble M0
and M1 are for timer0 and Higher nibble M0 and M1 for timer1.

M1 M0 Mode
0 0 Mode 0 (13-bit timer mode)
0 1 Mode 1(16-bit timer mode)
1 0 Mode 2 (8bit - auto-reload)
1 1 Mode 3 (8-bit Split timer)
To set the timer mode all 8 bits are to be set by an instruction. With a single
instruction, single timer or both timers can be set.

Example
MOV TMOD, #01H ;0000 0001 - mode 1 of timer 0 is set
MOV TMOD, #20H ;0010 0000 - mode 2 of timer 1 is set
MOV TMOD, #21h ;0010 0001 - mode 1 of timer 0 and
; mode 2 of timer1 are set.

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TCON (Timer Control) Special Function Register

7 6 5 4 3 2 1 0

TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

Fig. 4.18 TCON Special Function Register

The lower nibble bits IT1, IE0, IT1 and IE1 are control bits of interrupts.
Higher nibble bits TR0, TF0, TR1 and TF1 are control bits and flags of timers.

TCON.0 (IT0)
External interrupt 0 signal type control bit. When set to 1, external
interrupt flag IE0 raised by low active INT0 (Level triggering). When it is
cleared by 0, external interrupt flag IE0 raised by high to low level INT0(Edge
transient triggering).

TCON.1 (IE0)
External interrupt 0 edge flags. When external interrupt INT0 received on
port P3.2, this flag is raised to 1. It is cleared when Interrupt Service Routine
(ISR) of external interrupt 0 is executed.

TCON.2 (IT1)
External interrupt 1 signal type control bit. When set to 1, external
interrupt flag IE1 raised by low active INT1 (Level triggering). When it is
cleared by 0, external interrupt flag IE1 raised by high to low level INT1(Edge
transient triggering).

TCON.3 (IE1)
External interrupt 1 edge flags. When external interrupt INT1 received on
port P3.3, this flag is raised to 1. It is cleared when Interrupt Service Routine
(ISR) of external interrupt 1 is executed.

TCON.4 (TR0)
Timer 0 start/stop bit. When set to 1, the timer 0 is start counting. On clear
by 0 the timer stops. The content of timer 0 does not cleared by this bit.

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TCON.5 (TF0)
Timer 0 over flow flag. When timer 0 is overflow with FFFFh and goes to
0000H with next pulse, this flag TF0 is raised by the timer 0. These flags are
cleared when Interrupt Service Routine of timer 0 is executed.

TCON.6 (TR1)
Timer 1 start/stop bit. When set to 1, the timer1 is start counting. On clear
by 0 the timer 1 stops. The content of timer 1 does not cleared by this bit.

TCON.7 (TF1)
Timer 1over flow flag. When timer 1 is overflow with FFFFH and goes to
0000H with next pulse, this flag TF1 is raised by the timer 1. These flags are
cleared when Interrupt Service Routine of timer 1 is executed.

4.16 Modes of Timer / Counter operations

Both timer 0 and timer 1 of 8051 can be operated in 4 modes mode 0, mode
1, mode 2 and mode 3. These modes are set by M0 and M1 bits in TMOD
register. The detail functions of all modes are as follows,

Mode 0: (16-bit Timer mode)

M0 and M1 are set to 0. In this mode all 16 bits of timer are not used. It is a
13-bit timer mode. 5 bits of TLx and 8 bits of THx are used to form 13-bit timer.
When the timer is started in this mode, it is counting from loaded value to
1FFFh.
Crystal Frequency
Fla 12

7 6 5 4 32 1 04 32 1 0
8 bits of TH x 5 bits TLx
Fig. 4.19 Mode 0 of timer

Mode 1:(13-bit Timer mode)

M0 set to 1 and M1 is set to 0. In this mode the timer is working as 16-bit
register. TLx and THx are connected serially to form 16-bit timer. When the
timer is started, it counts from loaded value to FFFFh.

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Crystal Frequency
12
Flag

Fig. 4.20 - Mode 1 of Timer (16 bit)

Mode 2:(8-bit Auto reload timer mode)

M0 set to 0 and M1 set to 1. In this mode the timer is divided into two 8-bit
registers as TLx and THx. The TLx is used as 8bit timer and THx is used to load
the preset value for TLx register. THx loading the value automatically when TLx
timer flag is set. When the timer started it counts from loaded value to FFH.

12
8 bits of TH x
7 65 43 21 0
Flag
Au to Reload
8 bits of TL x
7 6 5 43 2 1 0
Fig. 4.21 Mode 2 of Timer (Auto Reload)

Mode 3:(8-bit separate timer mode)

Both M0 and M1 are set to 1. In this mode Timer0 is split into two separate
8-bit timers. TL0 as a separate timer and TH0 as separate timer. The timer
overflow flag of timer1 (TF1) is used by TH0. So, in this mode timer1 will not
have any Flag.
12

Flag 8 BITS OF TH0

TF1 76 54 32 10

Flag
TF0 7 6 5 4 3 2 1 0
8 bits of TL 0
Fig. 4.22 Mode 3 of timer

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Simple program using Timer/Counter

Programming of Timer

Crystal Time
Frequen C/T = 0 r
Enabl
e
Timer

T0/1
External Clk
Flag
TR0/1
Start/Stop
Fig 4.23 Timer logical circuit

The logical circuit of timer is shown in fig. 4.23. Timers are used to get
desired time delays. Both timer0 and timer1 can be programmed at the same
time to get two different time delays. Before programming, the preset value to
be loaded in timer to be calculated for the delay required.
For example, if 0000h is loaded in timer and started with internal clock, it
requires 65535 clock-pulses to reach FFFFh (Decimal equivalent to FFFFh is
65535). When time rolls over from FFFFh to 0000h the timer flag set to 1. So,
the maximum delay is the time period of 65535 pulses. Time period for one
pulse is 1micro-sec when 12MHz crystal is used.
Total time delay is 65535 x 1 = 65535 micro-sec

Example
Find Maximum delay achieved when 6MHz crystal is used.
Maximum delay achieved when a 6 MHz crystal used can be calculated as
follows,
Time period for one clock T = 1/ F
F = Crystal frequency / 12
= 6 / 12
= 500 KHz

Time period for one pulse = 1/ 500 x 10 3

= .000002Secs or 2 Sec
If one clock time period is 2 Secs, then time period for 65535 clock are 2 x
65535 =1.131mSec

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Example Program
A program to get largest delay using internal clock. Output should be
available at port1 pin 3. A 12MHz crystal is used. Timer 0 to be used.

CLR P1.3 ; Clear port 1 pin 3

MOV TMOD, #01H ; Timer 0, mode 1
; Timer 1 off
MOV TL0, #00H ; 00H loaded in TL0 register
MOV TH0, #00H ; 00H loaded in TH0 register
SETB P1.3 ; Port1 pin 3 made high
SETB TR0 ; Timer started

Repeat:
JNB TF0, REPEAT; Keep track timer flag TF0
CLR TR0 ; When TF0 set stop timer
CLR P1.3 ; Port 1 pin 3 to low
CLR TF0 ; Clear timer flag TF0
When the above program is executed, port 1 pin 3 high for 65535 secs and
goes to low.
The first instruction makes the output pin port1.3 to low. TMOD register is
loaded with 01H. It is 0000 0001b. M0 of Lower nibble is set to 1, so the timer 0
in mode 1. Gate bit is set to 0 to start/stop the timer by TR0 in TCON register.
Since C/T of timer 0 is set to 0, the internal clock is routed to timer. Next
instruction loads 0000H in both timer registers TL0 and TH0.
SETB P1.3 set the port 1 pin 3 to high and SETB TR0 starts the timer to
count from the loaded value 0000H. When timer is counting the flag TF0 is
under track by the instruction JNB TF0, REPEAT. This instruction is repeated
till the flag TF0 set to 1. When the timer 0 rolls over from FFFFH to 0000H the
flag TF0 set to 1 and the processor jump to next instruction. Then CLR TR0
stops the timer, and the flag TF0 and pin p1.3 are cleared by CLR P1.3.
Port1 pin 3 goes to high and remains in high for a duration, when timer
counts from 0000H to FFFFH. There are 65535 clock pulses used to count up to
FFFFH. Since 12Mhz crystal is used, time duration of one pulse is 1 sec. Total
time duration for 65535 is 65535 sec or 65.535mSec.So, the port 1 pin 3 was
high for 65.535msec.

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4.17 Counter programming

Crystal Timer
Frequen Enable

Count
C/T = 1 er
T0/1 COUNTER
External Clk
TR0/1
Start/Stop
Flag

Fig. 4.24 Counter logic diagram

When the timer receives external clock frequency, then it is called as

counter. To activate timer with external clock, the C/T bit in TMOD register
required to be 1.

Counter Programming
MOV TMOD, #05H ; Timer 0 selected, C/T is set to 1
MOV TL0, #00H ;
MOV TH0, #00H ; 0000h is loaded in timer registers
SETB P3.4 ; P3.4 set as I/p for ext. clock.
SETB TR0 ; Timer 0 started

Repeat
MOV A, TL0 ; Contents of TL0 moved to A reg.
MOV P2, A ; Contents of A reg. moved to P2
JNBTF0, REPEAT ; Keep load TL0 to P2 till TF0 = 1
CLR TR0
CLR TF0

Fig.4.25

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The fig. 4.25 shows the counter action when the program is executed. 8
LEDs are connected to port 2 to visualise the counting of TL0. When one clock
pulse is available at pin P3.4, TL0 counts up 01h. The contents of TL0 is moved
to P2. Thus, the LEDs connected to P2 shows the status of TL0. Let us analyse
the program,
TMOD register is set to timer 0, mode 1 and C/T = 1, so that the timer will
run on external clock from pin P3.4. Timer register is loaded with 0000h to
start from beginning. The timer is started by the instruction SETB TR0.
When the first clock pulse is available at pin P3.4, the TL0 counts up one to
01H. Now 01H is moved to accumulator and then to port 2 by MOV A, TL0 and
MOV P2, A instructions respectively. The corresponding LED glows when 01h
available at port 2. This action is repeated till timer flag TF0 is set to 1.

Time delay Error

When a program is executed to get a desired delay, the actual delay
available at output pin is more than the desired delay. This extra delay is due to
instructions in loop. To get accurate delay overhead delay should be taken into
account while calculating initial load value of timer.
Actual delay - Desired delay
Error = Desired delay
Example
Program to create a continuous square wave of 50% duty cycle on port P3.1
using timer 1. Desired time delay is 110 Sec. Crystal frequency is 12MHz

Solution
Calculation of initial loading number for timer.
Timer Clock is 12 MHz / 12
= 1 MHz

Time period for each clock is 1/1 x 10-6

= 1 Sec
Time delay required is 110 Sec. To get 110 Sec delay timer should be
loaded with -110. The hex number for -110 is FF92.

Program
MOV TMOD, #10h ; mode 1 of timer is set
MAIN: MOV TH1, #FFh; Initial value FF is set

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MOV TL1, #92h ; Initial value 92 is set

CPL P1.3 ; Toggle P1.3 pin

ACALL DLAY ; Subroutine DELAY call

SJMP MAIN ; Keep continue

DELAY:
SETB TR1 ; Timer 1 started
REPEAT:
JNB TF1 REPEAT ; Repeat till TF1 is set
CLR TR0 ; Stop Timer 1

CLR TF1 ; Flag bit TF1 cleared

RET

Calculation of actual delay by including overhead instructions. No. of

machine cycles used in loop to be calculated.

Instruction No. of Machine Delay

Cycles in  Sec
Main:
MOV TH1, #FFH 02 02
MOV TL1, #92H 02 02
CPL P1.3 01 01
ACALL DLAY 02 02
SJMP MAIN 02 02

Daly: SETB TR1 01 01

Repeat:
JNB TF1 REPEAT 110 110
CLR TR0 01 01
CLR TF1 01 01
RET 01 01
Total delay is 123

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From the above calculation, the actual delay is 123 Sec. The program is
made to for 110 Sec delay. 13 Sec more than the desired delay is due to overhead
instruction in loop.

4.18 Interrupt
When 8051 executes a program, a signal which suspend the program is
called interrupt. When an interrupt occurs, the Program Counter (PC) loads
with interrupt service routine (ISR) vector. Then the 8051 processor starts to
execute Interrupt Service Routine. On completion of ISR the processor come
back to main program where the break occurred. Interrupt may be generated
from inside 8051 or may come from outside of 8051. Interrupt generated inside
8051 is called internal interrupt and interrupt from outside is called external
interrupt.
There are five interrupts provided in 8051. Three interrupts are internal
interrupts and two are external interrupts. Internal interrupts are Timer0over
flow flag (TF0), Timer1 over flow flag (TF1) and serial port interrupt(R1orT1).
Two external interrupts are INT0 (port 3.2) and INT1(port 3.3).
Each interrupt source causes the program to jump to Interrupt Service
Routine in one of the absolute address of program memory. When an interrupt
occurs, a call is then done to appropriate memory location called ISR vectors.
The list of ISR vectors are as follows,
Interrupt Name ISR Vector Address (in Hex.)
External Interrupt 0(IE0) 0003H
Timer Overflow Flag 0(TF0) 000BH
External Interrupt 1(IE1) 0013H
Timer Overflow Flag 1(TF1) 001BH
Serial Interrupt (T1 or R1) 002BH
Three special function registers IE (Interrupt Enable), IP (Interrupt
Priority) and TCON (Timer Control) are used in 8051 to have a complete
interrupt function.
IE (Interrupt Enable) Special Function Register
7 6 5 4 3 2 1 0
EA ---- ---- ES ET1 EX1 ET0 Ex0

Fig. 4.26 IE Special Function Register

This register is a bit addressable and is used to enable concern interrupt. If

the interrupt bit in this register is not set, then the 8051 CPU will not execute

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the Interrupt Service routine even any of the interrupt occurs. The description
of each bit of this register is as follows,
IE.0 EX0 (Enable external interrupt 0). Programming this bit to 1,
external interrupt INT0 raises the external edge flag IE0 in TCON register.
External Interrupt edge flag IE0 causes the CPU to execute Interrupt service
routine.
IE.1 ET0 (Enable timer0 over flow flag). When this bit is set to 1 by
program, it enables the timer over flow flag TF0.
IE.2 EX1 (Enable external interrupt 1). Programming this bit to 1,
external interrupt INT1 raises the external edge flag IE1 in TCON register.
External Interrupt edge flag
IE1 causes the CPU to execute Interrupt service routine.
IE.3 ET1 (Enable timer1 over flow flag). When this bit is set to 1 by
program, it enables the timer over flow flag TF1.
IE.4 ES (Enable serial port interrupt). When this bit is set to 1 by
program, serial reception flag (R1) or serial transmission flag(T1) in SCON
register are enabled.
IE.5, IE.6 They are kept for future use.
IE.7 EA (Enable interrupt bits). Set to 0 by program disables all
interrupts. Should be set to 1 to enable one or all interrupts. IP (Interrupt
Priority) Special Function Register
7 6 5 4 3 2 1 0
---- ---- ---- PS PT1 PX1 PT0 PX0

Fig. 4.27 IP Special Function Register

IP.0 PX0 - External interrupt 0 INT0 priority bit.

IP.1 PT0 - Timer 0 over flow flag (TF0) priority bit.
IP.2 PX1 - External interrupt 1 INT1 priority bit.
IP.3 PT1 - Timer 1 over flow flag (TF1) priority bit.
IP.4 PS - Serial port interrupt priority bit.
Any one of these bits is set to 1 given more priority than set to 0. If more
than one bit is set to 1, then the following priority is used in 8051,
1. EX0 External Interrupt 0 (INT0)
2. ET0 Timer 0 over flow flag (TF0)
3. EX1 External Interrupt 1 (INT1)
4. ET1 Timer 1 over flow flag (TF1)
5. ES Serial interrupt RI or TI

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External Interrupts (INT0, INT1)

External interrupt pins P3.2(INT0) and P3.3(INT1) are used by i/o devices
or other external circuit. These pins are active low. When INT0 or INT1 goes
low, interruptflags IE0 or IE1 in TCON register are set to 1 respectively in two
different ways. Refer the fig. 1.28
LEVEL TRIGGER EA EX 0/1
IT0 = 0 TCON

INT0/1

IE0/1
IT0 = 1 TCON TCON 000B
ISR
Interrupt Flag

EDGE TRIGGER
Fig 4.28 External Interrupt logical Diagram
Low level signal in INT0/1 set the IE0/1 interrupt flag to 1 when IT0/1 bit
in TCON register is set to 0. If the IT0/1 bit in TCON register is set to 1, a high to
low transition of INT 0/1 set the IE0/1 flag to 1. When the interrupt flag IE0/1
is set, CPU executes interrupt service routine. On completion of ISR the
interrupt flags are cleared and the main program resumed.
Timer flag interrupt TF0 and TF1
Interrupt Flag
EA
000BH
TF0
ISR

ET0

Interrupt Flag

001BH
TF1
ISR
ET1

Fig. 4.29 Timer interrupt diagram

When timer/counter over flows from FFFFH to 0000H, the corresponding

timer over flow flag TF0/1 is set to 1. Bits EA and Enable timer overflow flag
(ET0/1) in IE register are set to 1 by program causes a timer interrupt. The CPU
of 8051 executes Interrupt Service Routine. On completion of ISR timer over
flags TF0/1 are cleared. The logical diagram of timer interrupt is shown in
fig.1.16

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Serial interrupt (RI or TI)

EA ES
Serial Interrupt

TI
RI ISR
Fig. 4.30 Serial Interrupt logical diagram

Serial communication is slow compared to parallel communication. Serial

data flags T1 and R1 are in SCON special function registers. These flags are
ORed and serial data interrupt is produced. This interrupt is enabled only when
serial interrupt bit ES and EA bit in IE register are set to 1. Although interrupt
service routine is executed by the CPU 0f 8051, the T1 and R1 flags are not
cleared by the ISR. These flags are to be cleared by the programmer in program.

Reset
Reset is also considered as interrupt because whenever active high is
available at (RST)pin 9 of 8051, the CPU stops executing the program and goes
to reset condition. The program counter jumps to 0000H. On reset of CPU, the
special function registers have their reset value. Unlike another interrupt the
program counter cannot resume the main program but the program restarted.
So, it is called non maskable interrupt.
Including reset, there are six interrupts available in 8051.
Program using interrupts
Program to get continuously 8-bit data from port 0 and send to port2, while
creating square wave of 200 micro-sec on port1 pin 1. Crystal frequency is
12Mhz.
ORG 0000H
LJMP HERE
.ORG 000BH ; timer interrupt vector

CPL P1.1
RETI
.ORG 0030H; Main program started from this address

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HERE: MOV TMOD, # 02H ; Timer 0, mode 2(Auto reload)

MOV P0, #0FFH; Port 0 made as input

MOV TH0, #38H; To get 200msec the TH0
; loaded with 38H
MOV IE, #82H ; EA & timer interrupt ET0 are set
SETB TR0 ; timer 0 started

Back:
MOV A, P0 ; port 0 data load to A register
MOV P2, A ; contents of A reg. moved to P1

SJMP Back
From the above program, the main program stored in ROM location 0030
onwards. Timer interrupt vector is 000BH. Timer 0 is set to mode 2(Auto
reload). MOV P0, #0FFH makes Port P0 as input port by writing all 1s to Port 0
latch buffers.
Since 12MHz crystal is used, one count required 1micro-sec.To get a 200
micro-secdelay 200 counts required by timer. The initial value to load the timer
is FFH - C8H (C8H is equivalent to 200) = 37. One extra clock pulse to be added
for roll over to FFH to 00H.
i.e., 37 + 1 = 38.
Interrupt enable register IE is loaded with 82H to enable EA bit and ET0 bit.
Master interrupt enable bit and timer interrupt enable bits are set.
SETB TR0 starts the timer and the subroutine BACK keep transferring data
from P0 to P2 via Accumulator.
Whenever the timer 0 rolls over, the timer flag TF0 set to 1 and enable
timer interrupt. The CPU suspend the BACK subroutine and execute timer ISR
loaded at 000BH. The CPL P1.1 toggles the previous state of P1.1. RETI clears
the timer flag and the program is resumed.
Subroutine HERE keep generating 200 Sec square pulses and subroutine
BACK keep transferring data from P0 to P2 till reset is pressed.

4.19 Serial Communication

8051 connected to other circuits and i/o devices via four ports P0, P1, P2
and P3. Each port having 8 pins and totally 32 pins used for data transfer. Data
transferred via these ports are byte wise (8-bit at a time.) This type of
communication called parallel communication.

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Apart from parallel communication, 8051 provides serial communication

also. In serial communication data transfer takes place bit wise. i.e. one bit at a
time. Since single bit is transferred from and to, only one wire is sufficient to
have serial communication.
The advantages of serial communication are,
 Single data line is used instead of wire strips
 Serial communication is much cheaper than parallel
 Since single line is used the data can be transferred to
 very large distance.
 Telephone wire can be used for transfer of data
The disadvantage of serial communication is, it is a slow process since the
data are transferred bit wise. To increase the speed of the serial communication
baud rate should be increased.

Baud rate
Baud rate means number of bits per second. The common baud rates used
by digital serial communication are 1200, 2400, 4800, 9600 and 19200. To
achieve these baud rate 11.0592MHz crystal is used.

Baud rate setting

Mode 0
Timer
Mode 1

Baud Rate

SBUF

Fig. 4.31 Logical diagram of Baud rate

Since we required different baud rate depend upon the circuit connected to
8051, system clock frequency alone cannot be used. To achieve different baud
rate timers are used. 8051 employs UART (Universal Asynchronous Receive
and Transmit) to determine the baud rate. The clock frequency in 8051 is 1/12
of crystal frequency. i.e. 11.0592/12 = 921.58Khz. The UART divides this

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frequency as per mode is selected. The mode of serial communication is set by

SM0 and SM1 bit in SCON special function register. When mode 0 is set, the
UART divides the clock by 32 and in mode 1 by 16. Due to this the baud rate of
mode 1 is double than the baud rate of mode 0. With the crystal having
11.059Mhz, the preset value to be loaded in timer to get different baud rate at
different mode is as follows,

Baud Rate Preset Value in Timer

SMOD 0 Smode1 HEX Decimal
1200 2400 E8 -24
2400 4800 F4 -12
4800 9600 FA -6
9600 19200 FD -3

SBUF (Serial Buffer) Register

8051 uses register SBUF to hold the data to be either transferred or
received. SBUF is physically two 8-bit registers as Write only SBUF and Read
only SBUF. The data to be transmitted is loaded to SBUF write only and
transmitted out via pin TXD(P3.1) of 8051. During reception, the data available
at pin RXD(P3.0) is loaded to SBUF read only.
SCON (Serial Control) Special Function Register.
This register SCON controls the serial data communication. It is an 8 bit
register and bit addressable. The address of this register is 98H.
7 6 5 4 3 2 1 0
SM0 SM1 SM2 REN TB8 RB8 TI RI
SCON Special Function Register
Fig 4.32

SCON.0 (RI)Receive interrupt flag. This interrupt flag is set to 1 when SBUF
receives the stop bit. RI flag should be cleared by the programmer.
SCON.1 TI (Transmit interrupt flag). This flag is raised to 1 when SBUF
transmits stop bit. This flag also not cleared by ISR and to be cleared by the
programmer.
SCON.2 RB8(Received bit 8). This bit is not used in mode0. in mode 1 the
stop bit is set this bit and in mode 2 & 3 bit 8.
SCON.3 TB8(Transmit bit 8). This bit is not used in mode 0&1. In mode 2&3
this bit is set/cleared by the programmer when the bit 8 is transmitted.

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SCON.4 REN (Receive Enable). Set to 1 this bit enables the serial reception.
To disable reception, set to 0.
SCON.5 SM2 (Multi processor communication bit): This bit is used for multi-
processor communications in mode 2 & 3.
SCON.6 & SCON.7 SM0 & SM1(Serial mode bits): Set/Cleared to select serial
mode. The selection of modes are as follows,

SM0 SM1 Mode Description

SBUF used as shift
0 0 0
register
Variable baud, 8-bit
0 1 1
UART
baud = f/32 or f/64, 9-
1 0 2
bit UART
baud rate variable, 9-
1 1 3
bit UART

The Power Mode Control (PCON) Special Function Register

7 6 5 4 3 2 1 0

SMOD ---- ---- ---- GF1 GF0 PD IDL

Fig.4.33 PCON Register

PCON Special function register is not bit addressable. The functions of each
bit in PCON register is as follows,
PCON.0 - (IDL)Idle mode bit.
PCON.1- (PD)Power down bit. This bit is used as handshaking signal to
other processors connected to 8051. Set to 1 by program to enter power down
configuration for CHMOS processors.
PCON.2 - (GFO) General purpose user flag 0. As per requirement of the
programmer, this bit can be either set or cleared in program.
PCON.3 - (GF1) General purpose user flag 1. As per requirement of the
programmer, this bit can be either set or cleared in program.
PCON.4 - 6 Not used
PCON.7 - (SMOD) Serial mode baud rate bit. Set to 0 by program to use the
baud rate set by timer 1. Set to 1 by program the timer 1 baud rate is doubled
for mode 1,2 and 3.

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Modes of Serial Communication

Mode 0:

Sto D7 D0 Star
0 1 0 0 0 0 0 1 Mar
SPACE p
Bit LSB t k
Bit
Fig. 4.34 Mode 0 timing

Mode 0 uses SBUF as an 8-bit shift register that transmits and receives data
on port 3.0, while using port 3.1 to output the shift clock. Fig. 5. shows the
timing for the rate transmission and reception of data of a character. When data
is written into SBUF, the LSB is transmitted first. Data is transmitted with the
speed of baud rate.
The receiver is enabled when bit 5 in SCON(REN) is enabled. At the end of
reception interrupt flat RI will set. Mode 0 is the only mode that controls when
reception can take place. Enabling reception also enables the clock pulses that
shift the received data into the receiver.

MODE 1 (Standard 8-bit UART mode)

This mode is used normally to communicate in 8-bit ASCII code. Only 7-bits
are needed to encode the entire set of ASCII characters. The 8th bit can be used
for even or odd parity or ignored completely. asynchronous data transmission
requires a start and stop bit to enable the receiving circuitry to detect the start
and finish of a complete character. A total of 10 bits needed to transmit the 7bit
ASCII character, as shown if fig. 4.21.

Idle State Idle State

Start Bit Stop Bit
1 2345678

Fig. 4.35 Mode 1 Asynchronous 8-bit mode1

MODE 2 and 3
Idle State Idle State
Start Bit Stop Bit
1 23456789

Fig. 4.36 Mode 1 Asynchronous 9-bit mode2 & 3

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These modes are identical except for the baud rate. Mode 2 uses a baud rate
of f/32 if SMOD is cleared or f/64 if SMOD is set. Baud rate for mode 3 are
programmable using the overflows of timer1 exactly as for data mode1.
Data transmission using mode 2 and 3 features 11 bits per character as
shown fig. 4. A data begins with a start bit, and the 10th bit of data is
programmable bit followed by stop bit. The 10th bit is programmed in SCON.3.

Serial Data Transmission

Before the data transmitted, the baud rate and mode should be set in SCON
special function register. The data of a byte to be transferred is loaded in write
only SBUF. Depend upon the mode selected in SCON register SBUF frames the
data with start and stop bits. Baud rate from timer is clocking SBUF to transmit
loaded data bit wise. The data transmission is via port3 pin1(TXD). During
transmission the TI flag is 0. When last stop bit is transmitted the TI flag in
SCON is set. The program has to track the TI flag and when it is set, the next
data of a byte should be loaded to SBUF. If the data is loaded before the TI flag
raised, the previous data in SBUF will be over written by the new data. The
programmer should clear the TI flag after loading SBUF.

Serial Data Reception

In serial data reception the port3 pin0 (RXD) is set as input pin by SETB
P3.0 instruction. The REN bit in SCON is also set to 1. The data available in P3.0
is loaded in to SBUF. After receiving last stop bit the flag RI in SCON register is
raised. After receiving the stop bit the SBUF register reframe the data. As soon
as the RI flag is raised the data in SBUF should be shifted to Accumulator
immediately for further process. Otherwise, next data available in P3.0 will
overwrite SBUF and the old data will be lost. The RI flag has to be cleared by the
program after moving the data from SBUF to Accumulator.

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