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Syllabus - CPLD and Fpga Architecture and Applications

This document outlines the course content for a semester course on CPLD and FPGA architecture and applications. The course covers the following topics: 1. Programmable logic devices including PLDs, PALs, PLAs and their applications using CPLDs from Altera and AMD. 2. Field programmable gate arrays (FPGAs) including logic blocks, routing architecture and design flow. Case studies on Xilinx and Altera FPGAs. 3. Finite state machines including state transition tables, state encoding, and realization of state machines using PALs and microprogramming. 4. FSM architectures including non-registered PLD designs and one-hot encoding methods

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1K views1 page

Syllabus - CPLD and Fpga Architecture and Applications

This document outlines the course content for a semester course on CPLD and FPGA architecture and applications. The course covers the following topics: 1. Programmable logic devices including PLDs, PALs, PLAs and their applications using CPLDs from Altera and AMD. 2. Field programmable gate arrays (FPGAs) including logic blocks, routing architecture and design flow. Case studies on Xilinx and Altera FPGAs. 3. Finite state machines including state transition tables, state encoding, and realization of state machines using PALs and microprogramming. 4. FSM architectures including non-registered PLD designs and one-hot encoding methods

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vasuvlsi
Copyright
© Attribution Non-Commercial (BY-NC)
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JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY, HYDERABAD DEPARTMENT OF ECE M.Tech.

(VLSI) I Semester 2005/06 CPLD AND FPGA ARCHITECTURE AND APPLICATIONS (ELECTIVE I) UNIT I Programmable logic : ROM, PLA, PAL, PLD, PGA Features, programming and applications using complex programmable logic devices Altera series Max 5000/7000 series and Altera FLEX logic 10000 series CPLD, AMDs CPLD (Mach 1 to 5); Cypres FLASH 370 Device Technology, Lattice pLSIs Architectures 3000 Series Speed Performance and in system programmability. UNIT II FPGAs: Field Programmable Gate Arrays Logic blocks, routing architecture, Design flow, Technology Mapping jfor FPGAs, Case studies Xilinx XC4000 & ALTERAs FLEX 8000/10000 FPGAs: AT & T ORCAs (Optimized Reconfigurable Cell Array): ACTELs ACT-1,2,3 and their speed performance. UNIT III Finite State Machines (FSM): Top Down Design State Transition Table, state assignments for FPGAs. Problem of initial state assignment for one hot encoding. Derivations of state machine charges. Realization of state machine charts with a PAL. Alternative realization for state machine chart suing microprogramming. Linked state machines. One Hot state machine, Petrinetes for state machines basic concepts, properties. Extended petrinetes for parallel controllers. Finite State Machine Case Study, Meta Stability, Synchronization. UNIT IV FSM Architectures and Systems Level Design: Architectures centered around non-registered PLDs. State machine designs centered around shift registers. One Hot design method. Use of ASMs in One Hot design. K Application of One Hot method. System level design controller, data path and functional partition. UNIT V Digital Front End Digital Design Tools for FPOGAs & ASICs: Using Mentor Graphics EDA Tool (FPGA Advantage) Design Flow Using FPGAs Guidelines and Case Studies of paraller adder cell, paraller adder sequential circuits, counters, multiplexers, parallel controllers. SUGGESTED BOOKS: 1. P.K.Chan & S. Mourad, Digital Design Using Field Programmable Gate Array, jPrentice Hall (Pte), 1994. 2. S.Trimberger, Edr., Field Programmable Gate Array Technology, Kluwer Academic Publicatgions, 1994. 3. J. Old Field, R.Dorf, Field Programmable Gate Arrays, John Wiley & Sons, Newyork, 1995. 4. S.Brown, R.Francis, J.Rose, Z.Vransic, Field Programmable Gate Array, Kluwer Pubin, 1992.

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