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Verilog III

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12 views12 pages

Verilog III

Uploaded by

Sai Amith
Copyright
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We take content rights seriously. If you suspect this is your content, claim it here.
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VERILOG -2

28-10-22
CS/ECE/EEE/INSTR F215 (DIGITAL DESIGN)
PROF. ANITA AGRAWAL, BITS, PILANI- K.K.BIRLA GOA CAMPUS
INTEGER CONSTANTS

ANITA AGRAWAL CS/ECE/EEE/INSTR F215 10/29/2022 6:46 PM 2


INTEGER CONSTANTS

 Integer constants/numbers: decimal by default.


 Preceded by a minus sign for negative value. Default:
unsigned integer.
 Other number systems: hexadecimal, octal, binary should be
specified as such,

 'b or 'B : binary (0,1)


 'o or 'O : octal (0-7)
 'h or 'H : hex (0-9, A-F or a-f)
 'd or 'D : decimal (0-9)
10/29/2022 6:46 PM 3
ANITA AGRAWAL CS/ECE/EEE/INSTR F215
UNSIZED INTEGERS

 Integer default size (unsized): 32 bits (compiler defined)


 Sized value: must be preceeding the base declaration.
 Must be an unsigned decimal number
 Should specify the number of bits required to represent the number.
 If the specified integer constant requires less bits than the specified
size, it is:
 left padded with zeros
 left padded with ’x’ or ‘z’ if leftmost is ‘x’ or ‘z’

ANITA AGRAWAL CS/ECE/EEE/INSTR F215 10/29/2022 6:46 PM 4


OPERATORS

ANITA AGRAWAL CS/ECE/EEE/INSTR F215 10/29/2022 6:17 PM 5


 Refer pp 362-363 Morris Mano, 4th Edition
 Table 4.12 pp 180

ANITA AGRAWAL CS/ECE/EEE/INSTR F215 10/29/2022 6:51 PM 6


OPERATOR PRECEDENCE

ANITA AGRAWAL CS/ECE/EEE/INSTR F215 10/29/2022 6:17 PM 7


CLASSES OF SIGNALS

 Each signal may be of type


net :
register
 Nets represent physical connection between hardware elements.
 Do not have any storage capacity
 Values are either determined by the values of the drivers (signal sources) or
by high impedance (when the net is not connected to any driver).

10/29/2022 6:17 PM
ANITA AGRAWAL CS/ECE/EEE/INSTR F215
VECTORS

 input B;
 input[15:0] bus;
 input [31:0] bus A, bus B;
 reg clock;
 reg [0:30] address;
ANITA AGRAWAL CS/ECE/EEE/INSTR F215 10/29/2022 6:17 PM 9
VECTOR PART SELECT

 bus A[5] // bit #5 of vector bus A

 bus A[3:0]// 4 least significant bits of


bus A

ANITA AGRAWAL CS/ECE/EEE/INSTR F215 10/29/2022 6:17 PM 10


VARIABLE VECTOR PART SELECT

 [starting bit +:width] part select increments from starting bit


 [starting bit -:width] part select decrements from starting bit

ANITA AGRAWAL CS/ECE/EEE/INSTR F215 10/29/2022 6:17 PM 11


EXAMPLES

reg [255:0] data1


reg [0:255] data2
byte = data1[31-:8]; // data[31:24]
byte = data1[24+:8]; //data[31:24]

ANITA AGRAWAL CS/ECE/EEE/INSTR F215 10/29/2022 6:17 PM 12

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