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Verilog I

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Verilog I

Uploaded by

Sai Amith
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© © All Rights Reserved
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DIGITAL DESIGN

CS/ECE/EEE/INSTR F215

INTRODUCTION TO VERILOG
PROF. ANITA AGRAWAL

BITS –Pilani, K.K.Birla Goa campus


23-09-22
Goals of the Lecture
• What is HDL?
• Do we really need HDL?
• The world before HDL
• The importance of HDL
• Different types of HDLs
• Verilog vs VHDL
• Introduction to Verilog
Sep 25, 2022 Anita Agrawal CS/ECE/EEE/INSTR F215 2
In the beginning, designs involved just a few gates. It was possible to verify these
circuits on paper or with breadboards.

As designs grew larger and more complex, paper or breadboard method became
difficult.

Designers thought of using some language which could describe the gate level models
(hardware).

Sep 25, 2022 Anita Agrawal CS/ECE/EEE/INSTR F215 3


Hardware Descriptive Language (HDL)

….The language of hardware engineers!!!

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Features of HDLs
• Designing with HDLs. is analogous to computer programming.

• Behavioral, RTL statements provide concise representation of design in


contrast to schematic logic

• No need for logic optimization using K-maps or other techniques.

• Design cycle time reduces drastically.

Sep 25, 2022 Anita Agrawal CS/ECE/EEE/INSTR F215 5


• Design is portable from one vendor to another

• Technology independent

• Can be used for all designs from SSIs to VLSIs.

Sep 25, 2022 Anita Agrawal CS/ECE/EEE/INSTR F215 6


Types of HDLs

There are several HDL languages in use today. Abel, Palasam and
Cupl used for less complex devices & Verilog & VHDL used for larger
CPLDs. & FPGA devices.

Sep 25, 2022 Anita Agrawal CS/ECE/EEE/INSTR F215 7


A bit of history…..
Verilog HDL is a hardware descriptive language developed in 1984-1985 by
Philip Moorby who needed a simple, intuitive & effective way of describing
digital circuits for modeling, simulation & analysis purposes.

• Became property of Gateway design Automation which was later acquired by


Cadence Design Systems

• From 1990, Cadence opened the language to the public which led to the
standardization of the language by IEEE in 1995.

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• Another HDL: VHDL

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Our focus…………….

Verilog!!!

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Design Specification

Design Entry
HDL/Schematic editor

Functional Simulation/Logical Verification

Logic Synthesis

Gate Level Netlist IC DESIGN PROCESS


FLOW DIAGRAM
System partitioning

Floor planning, Place & Route


No, if 1st iterations
No, 1st O.K failed
Design routed?
No, 1st O.K No, if 1st iterations
failed
Timing Simulation & Timing Analysis

Sep 25, 2022


Fusing or fabrication into the chip 11
Functional Simulation
• It is the representation of the structure and
behaviour of a digital logic system through the
use of computer.
• It interprets the HDL description and produces
readable output.
• It allows the detection of functional errors in a
design
• The stimulus that tests the functionality of the
design is called a ‘test bench’

Sep 25, 2022 Anita Agrawal CS/ECE/EEE/INSTR F215 12


Logic Synthesis
• It is the process of deriving a list of components and their
interconnections called a ‘netlist’ from the model of a digital
system that is described in HDL.

• The netlist can be used to fabricate an IC or to layout a


PCB.

Sep 25, 2022 Anita Agrawal CS/ECE/EEE/INSTR F215 13


Timing Simulation
• Allows you to check, in real time, that the design of your
device meets all of the functional and timing requirements
you expect of it.

• It confirms that the fabricated IC will operate at a


specified speed

Sep 25, 2022 Anita Agrawal CS/ECE/EEE/INSTR F215 14


Verilog!!!
• Very much akin to C.
• Design entry of a logic circuit is done by writing a verilog
code.
• Signalsin the circuit can be represented as variables in the
source code.
• Logicfunctions are expressed by assigning values to these
variables.

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• Verilog code is plain text.

• Sharing and reuse of verilog described circuits.

• Offers modularity

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How to write a verilog code???

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One Language…. Many Coding Styles

• Because of the wealth of verilog language constructs, each


circuit can be specified in several ways, according to the
designer's needs.
• Using primitives and lower-level module instantiation (structural
style)
• Specification of output signals in terms of the input signal
transformations (dataflow style)
• Specifying algorithmically the expected behavior of the circuit
(behavior style).

Sep 25, 2022 Anita Agrawal CS/ECE/EEE/INSTR F215 18


Structural Style

• The structural style verilog specification represents the actual physical


circuit implementation at the gate level and higher.

• It resembles the schematic drawing with components connected by signal.

• The functionality of the design is hidden inside the components.

Sep 25, 2022 Anita Agrawal CS/ECE/EEE/INSTR F215 19


• Since
logic gate is the most popular component, Verilog has
a predefined set of logic gates known as primitives

• Any digital circuit can be built from these gate primitives

• Verilogoffers a set of 14 logic gate primitives that can be


used to structurally specify the circuits

Sep 25, 2022 Anita Agrawal CS/ECE/EEE/INSTR F215 20


VERILOG CODE
SYNTAX

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keyword interface

module module_name (portlist);

port declarations;

Verilog statements
-----------; body
-----------;
-----------;

endmodule

keyword
Sep 25, 2022 Anita Agrawal CS/ECE/EEE/INSTR F215 22
Port/Signal Specification
• The syntax of a signal declaration is quite simple,
it starts with a keyword denoting the type of the
signal, followed by the signal name.

Signal Type Signal Name

22/09/06
Some important points
• Verilog model consists of 100 keywords.
• keywords predefined lowercase identifiers
that define the language constructs
• Comments:
• single line: //abnnmm…….
• Multi-line comments: /* */

• Case-sensitive

22/09/06
Signal Declaration
•The declaration of the signal must start with a keyword
denoting the signal
•Legal keywords are input, output, wire, tri, tri1, tri2,
supply1, supply0, integer, real etc..
•All letters must be lowercase
•A blank space follows the keyword
•All declarations are terminated with a semicolon

22/09/06
Signal Name
• Signal name cannot start with a $ or a number
• Cannot contain space inside
• It
cannot be of the reserved keywords type, for
ex. Wire, tri etc……
• More than one signal of the same type can be
written with the same keyword, in the same line
separated by commas.

22/09/06
Signal Specification

• Verilog syntax allows you to declare internal signals


anywhere in the body.

22/09/06
Example
G1
G3

G2
module Simple_Circuit(A, B, C, D, E);
output D, E;
input A, B, C;
wire w1;
and G1 (w1, A, B);
not G2 (E, C);
or G3 (D, w1, E);
endmodule
Sep 25, 2022 Anita Agrawal CS/ECE/EEE/INSTR F215 28
Gate Delays
• In Verilog, the propagation delay is specified of a gate is specified in
terms of time units and a symbol #.
• Number is a dimensionless quantity
• Association of time unit with physical time is made using ‘timescale compiler
directive.
• ‘timescale 1ns/100 ps.
• 1 ns: unit of measurement for time delays
• 100 ps: Precision with which the delays are rounded off.
• If no timescale used: default time (1 ns ) is used.
Sep 25, 2022 Anita Agrawal CS/ECE/EEE/INSTR F215 29
How to tackle Propagation delays
• You can include delays in your code. This will be the delay
in addition to the propagation delay that the gate
requires to change the output when the input signal
changes.

• The delays have to be used in the format #(delay )

Sep 25, 2022 Anita Agrawal CS/ECE/EEE/INSTR F215 30


How to tackle propagation delays

module Simple_Circuit_prop_delay(A, B, C, D, E);


output D, E;
input A, B, C;
wire w1;
and #(30) G1 (w1, A, B);
not #(10) G2 (E, C);
or #(20) G3 (D, w1, E);
endmodule

Sep 25, 2022 Anita Agrawal CS/ECE/EEE/INSTR F215 31

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